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| author | Nick Clifton <nickc@redhat.com> | 2009-12-02 20:26:30 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2009-12-02 20:26:30 +0000 |
| commit | 03ee1b7f8eb5cee9654e9d789e0c46a098bed895 (patch) | |
| tree | 44760d80f8168eb6f7d0b59222cfaf3f584b1cd3 /opcodes | |
| parent | 8cebebb9a2f399f50f4284797528fb952dd80576 (diff) | |
| download | gdb-03ee1b7f8eb5cee9654e9d789e0c46a098bed895.zip gdb-03ee1b7f8eb5cee9654e9d789e0c46a098bed895.tar.gz gdb-03ee1b7f8eb5cee9654e9d789e0c46a098bed895.tar.bz2 | |
PR gas/11013
* arm-dis.c (thumb32_opc): Adjust disassembly of QADD, QDADD, QSUB
and QDSUB.
* gas/arm/arch7em.d: Update expected disassembly.
* gas/arm/thumb32.d: Likewise.
* config/tc-arm.c (do_t_simd2): New function.
(insns): Use do_t_simd2 for QADD, QDADD, QSUB and QDSUB.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 7 | ||||
| -rw-r--r-- | opcodes/arm-dis.c | 8 |
2 files changed, 11 insertions, 4 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index e5c2f44..4899711 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,10 @@ +2009-12-02 Nick Clifton <nickc@redhat.com> + Richard Earnshaw <rearnsha@arm.com> + + PR gas/11013 + * arm-dis.c (thumb32_opc): Adjust disassembly of QADD, QDADD, QSUB + and QDSUB. + 2009-11-30 Massimo Ruo Roch <massimo.ruoroch@polito.it> PR gas/11030 diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index 38e1b66..a871d23 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -1364,10 +1364,10 @@ static const struct opcode32 thumb32_opcodes[] = {ARM_EXT_V6T2, 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"}, + {ARM_EXT_V6T2, 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"}, + {ARM_EXT_V6T2, 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"}, + {ARM_EXT_V6T2, 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"}, {ARM_EXT_V6T2, 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"}, {ARM_EXT_V6T2, 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"}, |