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| author | Renlin Li <renlin.li@arm.com> | 2015-04-15 17:44:03 +0100 |
|---|---|---|
| committer | Jiong Wang <jiong.wang@arm.com> | 2015-04-15 17:44:03 +0100 |
| commit | f0fba320ab5effaff5255b5526a37f0987637e3e (patch) | |
| tree | e4ab43f2d1f1ddf54122d348fe41d343fa6b79d3 /opcodes | |
| parent | 6282837972a5c7b89968319caf821fcbd2a166bb (diff) | |
| download | gdb-f0fba320ab5effaff5255b5526a37f0987637e3e.zip gdb-f0fba320ab5effaff5255b5526a37f0987637e3e.tar.gz gdb-f0fba320ab5effaff5255b5526a37f0987637e3e.tar.bz2 | |
[ARM] Disassembles SSAT and SSAT16 instructions incorrectly for Thumb-2
2015-04-15 Renlin Li <renlin.li@arm.com>
opcodes/:
* arm-dis.c (thumb32_opcodes): Define 'D' format control code,
use it for ssat and ssat16.
(print_insn_thumb32): Add handle case for 'D' control code.
gas/testsuite/:
* gas/arm/arch7em.d: Adjust required ssat and ssat16 immediate field.
* gas/arm/thumb32.d: Likewise.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 6 | ||||
| -rw-r--r-- | opcodes/arm-dis.c | 10 |
2 files changed, 14 insertions, 2 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 832e843..ffec856 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,9 @@ +2015-04-15 Renlin Li <renlin.li@arm.com> + + * arm-dis.c (thumb32_opcodes): Define 'D' format control code, + use it for ssat and ssat16. + (print_insn_thumb32): Add handle case for 'D' control code. + 2015-04-06 Ilya Tocar <ilya.tocar@intel.com> H.J. Lu <hongjiu.lu@intel.com> diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index c626bc9..1585a4f 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -2471,6 +2471,7 @@ static const struct opcode16 thumb_opcodes[] = %X print "\t; unpredictable <IT:code>" if conditional %<bitfield>d print bitfield in decimal + %<bitfield>D print bitfield plus one in decimal %<bitfield>W print bitfield*4 in decimal %<bitfield>r print bitfield as an ARM register %<bitfield>R as %<>r but r15 is UNPREDICTABLE @@ -2731,7 +2732,7 @@ static const struct opcode32 thumb32_opcodes[] = {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4d, %16-19r"}, + 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), @@ -2839,7 +2840,7 @@ static const struct opcode32 thumb32_opcodes[] = {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), - 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4d, %16-19r%s"}, + 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), @@ -5679,6 +5680,11 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) value_in_comment = val; break; + case 'D': + func (stream, "%lu", val + 1); + value_in_comment = val + 1; + break; + case 'W': func (stream, "%lu", val * 4); value_in_comment = val * 4; |