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| author | Maciej W. Rozycki <macro@imgtec.com> | 2017-05-12 01:09:36 +0100 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@imgtec.com> | 2017-05-12 01:12:10 +0100 |
| commit | a4f89915135f6760917c01dc783de5b674234d84 (patch) | |
| tree | 7361b054783a02df06643a4e1cd23e0607fb4680 /opcodes | |
| parent | de428bc53335d88c21eda38a823d5a4008468e52 (diff) | |
| download | gdb-a4f89915135f6760917c01dc783de5b674234d84.zip gdb-a4f89915135f6760917c01dc783de5b674234d84.tar.gz gdb-a4f89915135f6760917c01dc783de5b674234d84.tar.bz2 | |
MIPS16/opcodes: Make the handling of BREAK and SDBBP consistent
Disassemble the MIPS16 BREAK and SDBBP instruction's immediate operand
in the hexadecimal rather than decimal numeral system and add respective
operandless variants with an implicit 0 operand, making our handling of
these instructions consistent with how we have processed their regular
MIPS and microMIPS counterparts since forever.
opcodes/
* mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
type to hexadecimal.
(mips16_opcodes): Add operandless "break" and "sdbbp" entries.
binutils/
* testsuite/binutils-all/mips/mips16-extend-insn.d: Adjust BREAK
and SDBBP disassembly.
gas/
* testsuite/gas/mips/mips16.d: Adjust BREAK disassembly.
* testsuite/gas/mips/mips16-64@mips16.d: Likewise.
* testsuite/gas/mips/mips16-64.d: Likewise.
* testsuite/gas/mips/mips16-64@mips16-64.d: Likewise.
* testsuite/gas/mips/mips16-macro.d: Likewise.
* testsuite/gas/mips/mips16-64@mips16-macro.d: Likewise.
* testsuite/gas/mips/mips16-sub.d: Likewise.
* testsuite/gas/mips/mips16-32@mips16-sub.d: Likewise.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 6 | ||||
| -rw-r--r-- | opcodes/mips16-opc.c | 4 |
2 files changed, 9 insertions, 1 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 770b65d..02408b2 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,9 @@ +2017-05-12 Maciej W. Rozycki <macro@imgtec.com> + + * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand + type to hexadecimal. + (mips16_opcodes): Add operandless "break" and "sdbbp" entries. + 2017-05-11 Maciej W. Rozycki <macro@imgtec.com> * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs", diff --git a/opcodes/mips16-opc.c b/opcodes/mips16-opc.c index 7c8a0be..29e9d9d 100644 --- a/opcodes/mips16-opc.c +++ b/opcodes/mips16-opc.c @@ -56,7 +56,7 @@ decode_mips16_operand (char type, bfd_boolean extended_p) case '2': HINT (3, 8); case '3': HINT (5, 16); case '4': HINT (3, 21); - case '6': UINT (6, 5); + case '6': HINT (6, 5); case 'L': SPECIAL (6, 5, ENTRY_EXIT_LIST); case 'M': SPECIAL (7, 0, SAVE_RESTORE_LIST); @@ -230,6 +230,7 @@ const struct mips_opcode mips16_opcodes[] = {"bne", "x,y,p", 0, (int) M_BNE, INSN_MACRO, 0, I1, 0, 0 }, {"bne", "x,I,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1, 0, 0 }, {"bnez", "x,p", 0x2800, 0xf800, RD_1, CBR, I1, 0, 0 }, +{"break", "", 0xe805, 0xffff, TRAP, SH, I1, 0, 0 }, {"break", "6", 0xe805, 0xf81f, TRAP, SH, I1, 0, 0 }, {"bteqz", "p", 0x6000, 0xff00, RD_T, CBR, I1, 0, 0 }, {"btnez", "p", 0x6100, 0xff00, RD_T, CBR, I1, 0, 0 }, @@ -358,6 +359,7 @@ const struct mips_opcode mips16_opcodes[] = /* MIPS16e additions; see above for compact jumps. */ {"restore", "M", 0x6400, 0xff80, WR_31|NODS, MOD_SP, I32, 0, 0 }, {"save", "m", 0x6480, 0xff80, NODS, RD_31|MOD_SP, I32, 0, 0 }, +{"sdbbp", "", 0xe801, 0xffff, TRAP, SH, I32, 0, 0 }, {"sdbbp", "6", 0xe801, 0xf81f, TRAP, SH, I32, 0, 0 }, {"seb", "x", 0xe891, 0xf8ff, MOD_1, SH, I32, 0, 0 }, {"seh", "x", 0xe8b1, 0xf8ff, MOD_1, SH, I32, 0, 0 }, |