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| author | Nick Clifton <nickc@redhat.com> | 2013-03-20 16:36:34 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2013-03-20 16:36:34 +0000 |
| commit | 795b8e6bf35ad70e7da086831ad01d4b0660ba2d (patch) | |
| tree | 5b813493203eae5edc27c2ce3fa38af106fd2a77 /opcodes | |
| parent | e3f1ad4fd2e99bd226f19f88c513f13f3434de44 (diff) | |
| download | gdb-795b8e6bf35ad70e7da086831ad01d4b0660ba2d.zip gdb-795b8e6bf35ad70e7da086831ad01d4b0660ba2d.tar.gz gdb-795b8e6bf35ad70e7da086831ad01d4b0660ba2d.tar.bz2 | |
* include/opcode/tic6x.h: add tic6x_coding_dreg_(msb|lsb) field coding type in
order to encode separately the msb and lsb of a register pair ; this will be
needed to encode the opcodes the same
way as Ti assembler does.
* gas/config/tc-tic6x.c: handle tic6x_coding_dreg_(msb|lsb) field coding types
and use it to encode register pair numbers when required.
* opcodes/tic6x-dis.c: decodes opcodes that have individual msb and lsb halves
in src1 & src2 fields ; discard the src1 (lsb) value and only use src2 (msb),
discarding bit 0, to follow what Ti SDK does in that case as any value in the
src1 field yields the same output with SDK disassembler.
* include/opcode/tic6x-opcode-table.h: modify absdp, dpint, dpsp, dptrunc,
rcpdp and rsqrdp opcodes to use the new field coding types.
* gas/testsuite/gas/tic6x/insns-c674x.d, gas/testsuite/gas/tic6x/insns-c674x.s
: add test case for the newly generated opcode but keep the old ones as they
seem legit as per Ti disassembler output.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 11 | ||||
| -rw-r--r-- | opcodes/tic6x-dis.c | 12 |
2 files changed, 20 insertions, 3 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 66556f1..a678a70 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,6 +1,15 @@ +2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com> + + PR gas/15095 + * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have + individual msb and lsb halves in src1 & src2 fields. Discard the + src1 (lsb) value and only use src2 (msb), discarding bit 0, to + follow what Ti SDK does in that case as any value in the src1 + field yields the same output with SDK disassembler. + 2013-03-12 Michael Eager <eager@eagercon.com> - * opcodes/mips-dis.c (print_insn_args): Modify def of reg. + * opcodes/mips-dis.c (print_insn_args): Modify def of reg. 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de> diff --git a/opcodes/tic6x-dis.c b/opcodes/tic6x-dis.c index 05626df..73ac2e0 100644 --- a/opcodes/tic6x-dis.c +++ b/opcodes/tic6x-dis.c @@ -1,6 +1,5 @@ /* TI C6X disassembler. - Copyright 2010 - Free Software Foundation, Inc. + Copyright 2010-2013 Free Software Foundation, Inc. Contributed by Joseph Myers <joseph@codesourcery.com> Bernd Schmidt <bernds@codesourcery.com> @@ -632,6 +631,15 @@ print_insn_tic6x (bfd_vma addr, struct disassemble_info *info) operands_addresses[op_num] = fp_addr + signed_fld_val; break; + case tic6x_coding_regpair_msb: + if (opc->operand_info[op_num].form != tic6x_operand_regpair) + abort (); + operands_text[op_num] = TRUE; + snprintf (operands[op_num], 24, "%c%u:%c%u", + (func_unit_side == 2 ? 'b' : 'a'), (fld_val | 0x1), + (func_unit_side == 2 ? 'b' : 'a'), (fld_val | 0x1) - 1); + break; + case tic6x_coding_reg_shift: fld_val <<= 1; /* Fall through. */ |