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| author | Andre Vieira <andre.simoesdiasvieira@arm.com> | 2019-04-15 11:29:14 +0100 |
|---|---|---|
| committer | Andre Vieira <andre.simoesdiasvieira@arm.com> | 2019-04-15 12:30:33 +0100 |
| commit | f1c7f42126274d48f6b0a929e4e15a32193997c6 (patch) | |
| tree | e7d52e61a7c5e91e8decb2a32454e44ff3d90d51 /opcodes | |
| parent | 4389b29a5af431eeac517272b66560e12df3c430 (diff) | |
| download | gdb-f1c7f42126274d48f6b0a929e4e15a32193997c6.zip gdb-f1c7f42126274d48f6b0a929e4e15a32193997c6.tar.gz gdb-f1c7f42126274d48f6b0a929e4e15a32193997c6.tar.bz2 | |
[binutils, ARM, 7/16] New BFX and BFLX instruction for Armv8.1-M Mainline
This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils.
This patch adds the BFX and BFLX instructions.
ChangeLog entries are as follows :
*** gas/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (T16_32_TAB): New entries for bfx and bflx.
(do_t_v8_1_branch): New switch cases for bfx and bflx.
(insns): New instruction for bfx and bflx.
* testsuite/gas/arm/armv8_1-m-bf-exchange.d: New.
* testsuite/gas/arm/armv8_1-m-bf-exchange.s: New.
* testsuite/gas/arm/armv8_1-m-bf-exchange-bad.s: New
* testsuite/gas/arm/armv8_1-m-bf-exchange-bad.l: New
* testsuite/gas/arm/armv8_1-m-bf-exchange-bad.d: New
*** opcodes/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
Arm register with r13 and r15 unpredictable.
(thumb32_opcodes): New instructions for bfx and bflx.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 6 | ||||
| -rw-r--r-- | opcodes/arm-dis.c | 9 |
2 files changed, 15 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 3c782d1..e4de1d7 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,11 @@ 2019-04-15 Sudakshina Das <sudi.das@arm.com> + * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an + Arm register with r13 and r15 unpredictable. + (thumb32_opcodes): New instructions for bfx and bflx. + +2019-04-15 Sudakshina Das <sudi.das@arm.com> + * arm-dis.c (thumb32_opcodes): New instructions for bf. 2019-04-15 Sudakshina Das <sudi.das@arm.com> diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index d4a9375..08af171 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -2730,6 +2730,7 @@ static const struct opcode16 thumb_opcodes[] = %<bitfield>W print bitfield*4 in decimal %<bitfield>r print bitfield as an ARM register %<bitfield>R as %<>r but r15 is UNPREDICTABLE + %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE %<bitfield>c print bitfield as a condition code %<bitfield>'c print specified char iff bitfield is all ones @@ -2749,6 +2750,10 @@ static const struct opcode32 thumb32_opcodes[] = /* Armv8.1-M Mainline instructions. */ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 0xf040e001, 0xf860f001, "bf%c\t%G, %W"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), + 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), + 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"}, /* ARMv8-M and ARMv8-M Security Extensions instructions. */ @@ -6056,6 +6061,10 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) value_in_comment = val * 4; break; + case 'S': + if (val == 13) + is_unpredictable = TRUE; + /* Fall through. */ case 'R': if (val == 15) is_unpredictable = TRUE; |