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authorAndre Vieira <andre.simoesdiasvieira@arm.com>2019-04-15 11:06:30 +0100
committerAndre Vieira <andre.simoesdiasvieira@arm.com>2019-04-15 12:29:35 +0100
commite12437dc862690eeaa4a487fee35a237703d2b29 (patch)
tree308949d90e4b742fd3363a90988fc365881914a5 /opcodes
parente0991585ade56ff86a382978bb3b0268d6e1f31c (diff)
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[binutils, ARM, 3/16] BF insns infrastructure with new bfd_reloc_code_real for fallback branch
This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This adds infrastructure for the Branch Future instructions (BF, BFX, BFL, BFLX, BFCSEL). These are the first instructions in ARM that have more than one relocations in them. This is the first infrastructure patch that adds a new bfd_reloc_code_real enum for the fallback branch offset. This is common for all such instructions and needs to be resolvable by the assembler. ChangeLog entries are as follows : *** bfd/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * reloc.c (BFD_RELOC_THUMB_PCREL_BRANCH5): New enum. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. *** gas/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (md_pcrel_from_section): New switch case for BFD_RELOC_THUMB_PCREL_BRANCH5. (v8_1_branch_value_check): New function to check branch offsets. (md_appdy_fix): New switch case for BFD_RELOC_THUMB_PCREL_BRANCH5. (tc_gen_reloc): Likewise. *** opcodes/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
Diffstat (limited to 'opcodes')
-rw-r--r--opcodes/ChangeLog4
-rw-r--r--opcodes/arm-dis.c8
2 files changed, 12 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 5027e9a..fc9697b 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2019-04-15 Sudakshina Das <sudi.das@arm.com>
+
+ * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
+
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index e38296e..0ed893b 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -2713,6 +2713,7 @@ static const struct opcode16 thumb_opcodes[] =
%E print the lsb and width fields of a bfc/bfi instruction
%F print the lsb and width fields of a sbfx/ubfx instruction
+ %G print a fallback offset for Branch Future instructions
%b print a conditional branch offset
%B print an unconditional branch offset
%s print the shift field of an SSAT instruction
@@ -5862,6 +5863,13 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
}
break;
+ case 'G':
+ {
+ unsigned int boff = (((given & 0x07800000) >> 23) << 1);
+ func (stream, "%x", boff);
+ }
+ break;
+
case 'b':
{
unsigned int S = (given & 0x04000000u) >> 26;