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| author | Robert Suchanek <robert.suchanek@mips.com> | 2019-04-09 17:30:26 +0800 |
|---|---|---|
| committer | Chenghua Xu <paul.hua.gm@gmail.com> | 2019-04-09 09:56:48 +0000 |
| commit | 7e96e219a4fc703282ea5b0cc8845a96c01ca030 (patch) | |
| tree | 5407cdb45929c212b56e239ccf81dc933894fb61 /opcodes | |
| parent | 2b0c8b019996b23fb4717687f5e7ac8c5620c089 (diff) | |
| download | gdb-7e96e219a4fc703282ea5b0cc8845a96c01ca030.zip gdb-7e96e219a4fc703282ea5b0cc8845a96c01ca030.tar.gz gdb-7e96e219a4fc703282ea5b0cc8845a96c01ca030.tar.bz2 | |
[MIPS] Add RDHWR with the SEL field for MIPS R6.
In Release 6 of the MIPS architecture [1], instruction RDHWR supports
a 3rd operand to serve as the 3-bit select field for the hardware
register.
[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
Instruction Set Manual", Imagination Technologies Ltd., Document
Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2
"Alphabetical List of Instructions", pp. 332-334
opcodes/
* mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
gas/
* testsuite/gas/mips/mips.exp: Run hwr-names test.
* testsuite/gas/mips/hwr-names.s: Add test cases for RDHWR with
the SEL field.
* testsuite/gas/mips/mipsr6@hwr-names.d: New file.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 4 | ||||
| -rw-r--r-- | opcodes/mips-opc.c | 1 |
2 files changed, 5 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 27557eb..b6d4de3 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,7 @@ +2019-04-09 Robert Suchanek <robert.suchanek@mips.com> + + * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel. + 2019-04-08 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Consolidate AVX512 BF16 entries. diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index 837da6b..91f6027 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -1781,6 +1781,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO, 0, I1, 0, I37 }, {"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO, 0, I1, 0, I37 }, {"rdhwr", "t,K", 0x7c00003b, 0xffe007ff, WR_1, 0, I33, 0, 0 }, +{"rdhwr", "t,K,+O", 0x7c00003b, 0xffe0063f, WR_1, 0, I37, 0, 0 }, {"rdpgpr", "d,w", 0x41400000, 0xffe007ff, WR_1, 0, I33, 0, 0 }, /* rfe is moved below as it now conflicts with tlbgp */ {"rnas.qh", "X,Q", 0x78200025, 0xfc20f83f, WR_1|RD_2|FP_D, RD_MACC, 0, MX, 0 }, |