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| author | Andre Vieira <andre.simoesdiasvieira@arm.com> | 2019-04-15 11:58:47 +0100 |
|---|---|---|
| committer | Andre Vieira <andre.simoesdiasvieira@arm.com> | 2019-04-15 12:31:45 +0100 |
| commit | 60f993ce170b91876ad41e8f7339c24afd63fac2 (patch) | |
| tree | 2326ba080630de9a1378466903b492084a476616 /opcodes | |
| parent | f6b2b12db82f7b76c30ec389a67fbce5d2805323 (diff) | |
| download | gdb-60f993ce170b91876ad41e8f7339c24afd63fac2.zip gdb-60f993ce170b91876ad41e8f7339c24afd63fac2.tar.gz gdb-60f993ce170b91876ad41e8f7339c24afd63fac2.tar.bz2 | |
[binutils, ARM, 12/16] Scalar Low Overhead loop instructions for Armv8.1-M Mainline
s patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils.
This patch adds support to the Scalar low overhead loop instructions:
LE
WLS
DLS
We also add a new assembler resolvable relocation bfd_reloc_code_real enum for the 12-bit branch offset used in these instructions.
ChangeLog entries are as follows:
*** bfd/ChnageLog ***
2019-04-12 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_ARM_THUMB_LOOP12): New.
* bfd-in2.h: Regenerated.
* libbfd.h: Regenerated.
*** gas/ChangeLog ***
2019-04-12 Sudakshina Das <sudi.das@arm.com>
Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (operand_parse_code): Add OP_LR and OP_oLR
for the LR operand and optional LR operand.
(parse_operands): Add switch cases for OP_LR and OP_oLR for
both type checking and value checking.
(encode_thumb32_addr_mode): New entries for DLS, WLS and LE.
(v8_1_loop_reloc): New helper function for handling labels
for the low overhead loop instructions.
(do_t_loloop): New function to encode DLS, WLS and LE.
(insns): New entries for WLS, DLS and LE.
(md_pcrel_from_section): New switch case
for BFD_RELOC_ARM_THUMB_LOOP12.
(md_appdy_fix): Likewise.
(tc_gen_reloc): Likewise.
* testsuite/gas/arm/armv8_1-m-tloop.s: New.
* testsuite/gas/arm/armv8_1-m-tloop.d: New.
* testsuite/gas/arm/armv8_1-m-tloop-bad.s: New.
* testsuite/gas/arm/armv8_1-m-tloop-bad.d: New.
* testsuite/gas/arm/armv8_1-m-tloop-bad.l: New.
*** opcodes/ChangeLog ***
2019-04-12 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Updated to accept new %P
and %Q patterns.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/arm-dis.c | 37 |
2 files changed, 42 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 594e7ae..7f86025 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,10 @@ 2019-04-15 Sudakshina Das <sudi.das@arm.com> + * arm-dis.c (print_insn_thumb32): Updated to accept new %P + and %Q patterns. + +2019-04-15 Sudakshina Das <sudi.das@arm.com> + * arm-dis.c (thumb32_opcodes): New instruction bfcsel. (print_insn_thumb32): Edit the switch case for %Z. diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index 9886996..4a0f76a 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -2717,6 +2717,8 @@ static const struct opcode16 thumb_opcodes[] = %W print an offset for BF instruction %Y print an offset for BFL instruction %Z print an offset for BFCSEL instruction + %Q print an offset for Low Overhead Loop instructions + %P print an offset for Low Overhead Loop end instructions %b print a conditional branch offset %B print an unconditional branch offset %s print the shift field of an SSAT instruction @@ -2751,6 +2753,15 @@ static const struct opcode32 thumb32_opcodes[] = { /* Armv8.1-M Mainline instructions. */ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), + 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), + 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), + 0xf02fc001, 0xfffff001, "le\t%P"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), + 0xf00fc001, 0xfffff001, "le\tlr, %P"}, + + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 0xf040e001, 0xf860f001, "bf%c\t%G, %W"}, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"}, @@ -5944,6 +5955,32 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) } break; + case 'Q': + { + unsigned int immh = (given & 0x000007feu) >> 1; + unsigned int imml = (given & 0x00000800u) >> 11; + bfd_vma imm32 = 0; + + imm32 |= immh << 2; + imm32 |= imml << 1; + + info->print_address_func (pc + 4 + imm32, info); + } + break; + + case 'P': + { + unsigned int immh = (given & 0x000007feu) >> 1; + unsigned int imml = (given & 0x00000800u) >> 11; + bfd_vma imm32 = 0; + + imm32 |= immh << 2; + imm32 |= imml << 1; + + info->print_address_func (pc + 4 - imm32, info); + } + break; + case 'b': { unsigned int S = (given & 0x04000000u) >> 26; |