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| author | Matthew Malcomson <matthew.malcomson@arm.com> | 2019-05-09 10:29:16 +0100 |
|---|---|---|
| committer | Matthew Malcomson <matthew.malcomson@arm.com> | 2019-05-09 10:29:16 +0100 |
| commit | 3bd82c86f0f432bd7653101069bf056fda14b7cd (patch) | |
| tree | b26d522e496dcd5b402020c7843059de9a101e63 /opcodes | |
| parent | adccc50753467ac66573471f180a60d8d96ce223 (diff) | |
| download | gdb-3bd82c86f0f432bd7653101069bf056fda14b7cd.zip gdb-3bd82c86f0f432bd7653101069bf056fda14b7cd.tar.gz gdb-3bd82c86f0f432bd7653101069bf056fda14b7cd.tar.bz2 | |
[binutils][aarch64] New iclass sve_size_hsd2.
Add "sve_size_hsd2" iclass decode that uses the new FLD_SVE_size field
value to determine the variant of an instruction.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_hsd2 iclass.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
sve_size_hsd2 iclass encode.
* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
sve_size_hsd2 iclass decode.
* aarch64-opc.c (fields): Handle SVE_size field.
* aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 9 | ||||
| -rw-r--r-- | opcodes/aarch64-asm.c | 5 | ||||
| -rw-r--r-- | opcodes/aarch64-dis.c | 7 | ||||
| -rw-r--r-- | opcodes/aarch64-opc.c | 1 | ||||
| -rw-r--r-- | opcodes/aarch64-opc.h | 1 |
5 files changed, 23 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index a1a842d..8e8b185 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,14 @@ 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> + * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle + sve_size_hsd2 iclass encode. + * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle + sve_size_hsd2 iclass decode. + * aarch64-opc.c (fields): Handle SVE_size field. + * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field. + +2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> + * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index 2424b66..d4f498f 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -1659,6 +1659,11 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst) insert_field (FLD_SVE_sz, &inst->value, aarch64_get_variant (inst), 0); break; + case sve_size_hsd2: + insert_field (FLD_SVE_size, &inst->value, + aarch64_get_variant (inst) + 1, 0); + break; + default: break; } diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index eea649f..844c6ab 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -2810,6 +2810,13 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst) variant = extract_field (FLD_SVE_sz, inst->value, 0); break; + case sve_size_hsd2: + i = extract_field (FLD_SVE_size, inst->value, 0); + if (i < 1) + return FALSE; + variant = i - 1; + break; + default: /* No mapping between instruction class and qualifiers. */ return TRUE; diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index eb3a1e4..97cbfc8 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -311,6 +311,7 @@ const aarch64_field fields[] = { 10, 2 }, /* SVE_rot2: 2-bit rotation amount. */ { 10, 1 }, /* SVE_rot3: 1-bit rotation amount at bit 10. */ { 22, 1 }, /* SVE_sz: 1-bit element size select. */ + { 17, 2 }, /* SVE_size: 2-bit element size, bits [18,17]. */ { 16, 4 }, /* SVE_tsz: triangular size select. */ { 22, 2 }, /* SVE_tszh: triangular size select high, bits [23,22]. */ { 8, 2 }, /* SVE_tszl_8: triangular size select low, bits [9,8]. */ diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h index b1060d4..942fa58 100644 --- a/opcodes/aarch64-opc.h +++ b/opcodes/aarch64-opc.h @@ -138,6 +138,7 @@ enum aarch64_field_kind FLD_SVE_rot2, FLD_SVE_rot3, FLD_SVE_sz, + FLD_SVE_size, FLD_SVE_tsz, FLD_SVE_tszh, FLD_SVE_tszl_8, |