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| author | Andre Vieira <andre.simoesdiasvieira@arm.com> | 2019-04-15 11:37:51 +0100 |
|---|---|---|
| committer | Andre Vieira <andre.simoesdiasvieira@arm.com> | 2019-04-15 12:30:33 +0100 |
| commit | 1caf72a5849abf9a717ed3e0232abf591ff933e7 (patch) | |
| tree | 195d651a5012a54933d6cb2d1793ebc659db4fc8 /opcodes | |
| parent | f1c7f42126274d48f6b0a929e4e15a32193997c6 (diff) | |
| download | gdb-1caf72a5849abf9a717ed3e0232abf591ff933e7.zip gdb-1caf72a5849abf9a717ed3e0232abf591ff933e7.tar.gz gdb-1caf72a5849abf9a717ed3e0232abf591ff933e7.tar.bz2 | |
[binutils, ARM, 8/16] BFL infrastructure with new global reloc R_ARM_THM_BF18
This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils.
This adds infrastructure for the BFL instructions which is one of the first instructions in Arm that have more than one relocations in them.
This adds a new relocation R_ARM_THM_BF18.
The inconsistency between external R_ARM_THM_BF18 and internal
BFD_RELOC_ARM_THUMB_BF19 is because internally we count the static bit-0 of the immediate and we don't externally.
ChangeLog entries are as follows :
*** bfd/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_ARM_THUMB_BF19): New
* libbfd.h: Regenerated.
* bfd-in2.h: Regenerated.
* bfd-elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF18.
(elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF19
and R_ARM_THM_BF18 together.
(elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF19.
*** elfcpp/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm.h (R_ARM_THM_BF18): New relocation code.
*** gas/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (md_pcrel_from_section): New switch case for
BFD_RELOC_ARM_THUMB_BF19.
(md_appdy_fix): Likewise.
(tc_gen_reloc): Likewise.
*** include/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF18.
*** opcodes/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 4 | ||||
| -rw-r--r-- | opcodes/arm-dis.c | 18 |
2 files changed, 22 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index e4de1d7..edd03f8 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,9 @@ 2019-04-15 Sudakshina Das <sudi.das@arm.com> + * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern. + +2019-04-15 Sudakshina Das <sudi.das@arm.com> + * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an Arm register with r13 and r15 unpredictable. (thumb32_opcodes): New instructions for bfx and bflx. diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index 08af171..b32ff32 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -2715,6 +2715,7 @@ static const struct opcode16 thumb_opcodes[] = %F print the lsb and width fields of a sbfx/ubfx instruction %G print a fallback offset for Branch Future instructions %W print an offset for BF instruction + %Y print an offset for BFL instruction %b print a conditional branch offset %B print an unconditional branch offset %s print the shift field of an SSAT instruction @@ -5898,6 +5899,23 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) } break; + case 'Y': + { + unsigned int immA = (given & 0x007f0000u) >> 16; + unsigned int immB = (given & 0x000007feu) >> 1; + unsigned int immC = (given & 0x00000800u) >> 11; + bfd_vma offset = 0; + + offset |= immA << 12; + offset |= immB << 2; + offset |= immC << 1; + /* Sign extend. */ + offset = (offset & 0x40000) ? offset - (1 << 19) : offset; + + info->print_address_func (pc + 4 + offset, info); + } + break; + case 'b': { unsigned int S = (given & 0x04000000u) >> 26; |