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authorAndre Vieira <andre.simoesdiasvieira@arm.com>2019-04-15 11:46:54 +0100
committerAndre Vieira <andre.simoesdiasvieira@arm.com>2019-04-15 12:31:34 +0100
commit1889da7048b310151d142b100678b6bd6053b548 (patch)
treee0e8d1d48cd6814f4c10ea01da58235a3c81728b /opcodes
parent65d1bc05e89e45b102783422c3984ed718547d5c (diff)
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[binutils, ARM, 10/16] BFCSEL infrastructure with new global reloc R_ARM_THM_BF12
This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This adds infrastructure for the BFCSEL instructions which is one of the first instructions in Arm that have more than one relocations in them. This adds a new relocation R_ARM_THM_BF12. The inconsistency between external R_ARM_THM_BF12 and internal BFD_RELOC_ARM_THUMB_BF13 is because internally we count the static bit-0 of the immediate and we don't externally. ChangeLog entries are as follows : ChangeLog entries are as follows : *** bfd/ChnageLog *** 2019-04-04 Sudakshina Das <sudi.das@arm.com> * reloc.c (BFD_RELOC_ARM_THUMB_BF13): New. * bfd-in2.h: Regenerated. * libbfd.h: Regenerated. * elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF13. (elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF13 and R_ARM_THM_BF12 together. (elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF13. *** elfcpp/ChangeLog *** 2019-04-04 Sudakshina Das <sudi.das@arm.com> * arm.h (R_ARM_THM_BF12): New relocation code. *** gas/ChangeLog *** 2019-04-04 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (md_pcrel_from_section): New switch case for BFD_RELOC_ARM_THUMB_BF13. (md_appdy_fix): Likewise. (tc_gen_reloc): Likewise. *** include/ChangeLog *** 2019-04-04 Sudakshina Das <sudi.das@arm.com> * elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF12. *** opcodes/ChangeLog *** 2019-04-04 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
Diffstat (limited to 'opcodes')
-rw-r--r--opcodes/ChangeLog4
-rw-r--r--opcodes/arm-dis.c18
2 files changed, 22 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 94860b8..69a191a 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,9 @@
2019-04-15 Sudakshina Das <sudi.das@arm.com>
+ * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
+
+2019-04-15 Sudakshina Das <sudi.das@arm.com>
+
* arm-dis.c (thumb32_opcodes): New instruction bfl.
2019-04-15 Sudakshina Das <sudi.das@arm.com>
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index c7b5959..93e1efe 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -2716,6 +2716,7 @@ static const struct opcode16 thumb_opcodes[] =
%G print a fallback offset for Branch Future instructions
%W print an offset for BF instruction
%Y print an offset for BFL instruction
+ %Z print an offset for BFCSEL instruction
%b print a conditional branch offset
%B print an unconditional branch offset
%s print the shift field of an SSAT instruction
@@ -5918,6 +5919,23 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
}
break;
+ case 'Z':
+ {
+ unsigned int immA = (given & 0x00010000u) >> 16;
+ unsigned int immB = (given & 0x000007feu) >> 1;
+ unsigned int immC = (given & 0x00000800u) >> 11;
+ bfd_vma offset = 0;
+
+ offset |= immA << 12;
+ offset |= immB << 2;
+ offset |= immC << 1;
+ /* Sign extend. */
+ offset = (offset & 0x1000) ? offset - (1 << 13) : offset;
+
+ info->print_address_func (pc + 4 + offset, info);
+ }
+ break;
+
case 'b':
{
unsigned int S = (given & 0x04000000u) >> 26;