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| author | Adam Nemet <anemet@caviumnetworks.com> | 2008-04-29 23:27:01 +0000 |
|---|---|---|
| committer | Adam Nemet <anemet@caviumnetworks.com> | 2008-04-29 23:27:01 +0000 |
| commit | 89aa3097c23c68a459a9795d8875290f8e48d8d8 (patch) | |
| tree | 8edce94a088b27a54bd3e88732e7a8682e449a8b /opcodes | |
| parent | 1de34ab72d7fe2c5a98a72f0e2b02d05828687a5 (diff) | |
| download | gdb-89aa3097c23c68a459a9795d8875290f8e48d8d8.zip gdb-89aa3097c23c68a459a9795d8875290f8e48d8d8.tar.gz gdb-89aa3097c23c68a459a9795d8875290f8e48d8d8.tar.bz2 | |
* mips-opc.c (mips_builtin_opcodes): Set field `match' to 0 for
the two drem and the two dremu macros.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/mips-opc.c | 8 |
2 files changed, 9 insertions, 4 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 6f55be2..26356c4 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2008-04-29 Adam Nemet <anemet@caviumnetworks.com> + + * mips-opc.c (mips_builtin_opcodes): Set field `match' to 0 for + the two drem and the two dremu macros. + 2008-04-28 Adam Nemet <anemet@caviumnetworks.com> * mips-opc.c (mips_builtin_opcodes): Mark prefx and c1 diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index 63bec4f..1787c9e 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -630,11 +630,11 @@ const struct mips_opcode mips_builtin_opcodes[] = {"dneg", "d,w", 0x0000002e, 0xffe007ff, WR_d|RD_t, 0, I3 }, /* dsub 0 */ {"dnegu", "d,w", 0x0000002f, 0xffe007ff, WR_d|RD_t, 0, I3 }, /* dsubu 0*/ {"drem", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, -{"drem", "d,v,t", 3, (int) M_DREM_3, INSN_MACRO, 0, I3 }, -{"drem", "d,v,I", 3, (int) M_DREM_3I, INSN_MACRO, 0, I3 }, +{"drem", "d,v,t", 0, (int) M_DREM_3, INSN_MACRO, 0, I3 }, +{"drem", "d,v,I", 0, (int) M_DREM_3I, INSN_MACRO, 0, I3 }, {"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, -{"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO, 0, I3 }, -{"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO, 0, I3 }, +{"dremu", "d,v,t", 0, (int) M_DREMU_3, INSN_MACRO, 0, I3 }, +{"dremu", "d,v,I", 0, (int) M_DREMU_3I, INSN_MACRO, 0, I3 }, {"dret", "", 0x7000003e, 0xffffffff, 0, 0, N5 }, {"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I3 }, {"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I3 }, |