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| author | Sergey Belyashov <sergey.belyashov@gmail.com> | 2020-03-03 16:31:42 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2020-03-03 16:32:52 +0000 |
| commit | b8ba13856360d1cae00269a0ffe291cf573bb575 (patch) | |
| tree | 8ea4c0ca398549d57965783aff7cb2aab9ffbbd3 /opcodes | |
| parent | 7b973adce2b486518d3150db257b179e1b9a5d33 (diff) | |
| download | gdb-b8ba13856360d1cae00269a0ffe291cf573bb575.zip gdb-b8ba13856360d1cae00269a0ffe291cf573bb575.tar.gz gdb-b8ba13856360d1cae00269a0ffe291cf573bb575.tar.bz2 | |
The patch fixed invalid compilation of instruction LD IY,(HL) and disassemble of this and LD (HL),IX instruction. Also it update testsuit.
PR 25627
opcodes * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
instructions.
gas * config/tc-z80.c (emit_ld_rr_m): Fix invalid compilation of
instruction LD IY,(HL).
* testsuite/gas/z80/ez80_adl_all.d: Update expected disassembly.
* testsuite/gas/z80/ez80_adl_all.s: Add tests of the instruction.
* testsuite/gas/z80/ez80_z80_all.d: Update expected disassembly.
* testsuite/gas/z80/ez80_z80_all.s: Add tests of the instruction.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 6 | ||||
| -rw-r--r-- | opcodes/z80-dis.c | 4 |
2 files changed, 8 insertions, 2 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 03146c2..f471cd0 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,9 @@ +2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com> + + PR 25627 + * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX + instructions. + 2020-03-03 H.J. Lu <hongjiu.lu@intel.com> PR gas/25622 diff --git a/opcodes/z80-dis.c b/opcodes/z80-dis.c index 4762a62..d66bd75 100644 --- a/opcodes/z80-dis.c +++ b/opcodes/z80-dis.c @@ -436,6 +436,7 @@ struct tab_elt opc_ed[] = { { 0x30, 0xFF, prt, "mul d,e", INSS_Z80N }, { 0x31, 0xFF, prt, "add hl,a", INSS_Z80N }, + { 0x31, 0xFF, prt, "ld iy,(hl)", INSS_EZ80 }, { 0x30, 0xFE, dump, "xx", INSS_ALL }, /* do not move this line */ { 0x00, 0xC7, prt_r_n, "in0 %s,(0x%%02x)", INSS_Z180|INSS_EZ80 }, { 0x01, 0xC7, prt_r_n, "out0 (0x%%02x),%s", INSS_Z180|INSS_EZ80 }, @@ -446,6 +447,7 @@ struct tab_elt opc_ed[] = { 0x04, 0xC7, prt_r, "tst %s", INSS_Z180}, { 0x04, 0xC7, prt_r, "tst a,%s", INSS_EZ80 }, { 0x07, 0xFF, prt, "ld bc,(hl)", INSS_EZ80 }, + { 0x3F, 0xFF, prt, "ld (hl),ix", INSS_EZ80 }, { 0x0F, 0xCF, prt_rr, "ld (hl),", INSS_EZ80 }, { 0x17, 0xFF, prt, "ld de,(hl)", INSS_EZ80 }, { 0x23, 0xFF, prt, "swapnib", INSS_Z80N }, @@ -462,10 +464,8 @@ struct tab_elt opc_ed[] = { 0x34, 0xFF, prt_nn, "add hl,0x%04x", INSS_Z80N }, { 0x35, 0xFF, prt_nn, "add de,0x%04x", INSS_Z80N }, { 0x36, 0xFF, prt_nn, "add bc,0x%04x", INSS_Z80N }, - { 0x36, 0xFF, prt, "ld iy,(hl)", INSS_EZ80 }, { 0x37, 0xFF, prt, "ld ix,(hl)", INSS_EZ80 }, { 0x3E, 0xFF, prt, "ld (hl),iy", INSS_EZ80 }, - { 0x3F, 0xFF, prt, "ld (hl),ix", INSS_EZ80 }, { 0x70, 0xFF, prt, "in f,(c)", INSS_Z80 | INSS_R800 | INSS_Z80N }, { 0x70, 0xFF, dump, "xx", INSS_ALL }, { 0x40, 0xC7, prt_r, "in %s,(bc)", INSS_EZ80 }, |