gas/testsuite/

	* gas/m68k/mcf-coproc.d: New.
	* gas/m68k/mcf-coproc.s: New.
	* gas/m68k/all.exp: Add it.

	gas/
	* config/tc-m68k.c (m68k_ip): Add j & K operand types.
	(install_operand): Add E encoding.
	(md_begin): Check and skip initial '.' arg character.
	(get_num): Add 0..511 case.

	include/
	* opcode/m68k.h: Document j K & E.

	opcodes/
	* m68k-dis.c (fetch_arg): Add E.  Replace length switch with
	direct masking.
	(print_ins_arg): Add j & K operand types.
	(match_insn_m68k): Check and skip initial '.' arg character.
	(m68k_scan_mask): Likewise.
	* m68k-opc.c (m68k_opcodes): Add coprocessor instructions.

3 files changed, 72 insertions, 35 deletions

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 42ebf40..f6c6418 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,12 @@
+2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* m68k-dis.c (fetch_arg): Add E.  Replace length switch with
+	direct masking.
+	(print_ins_arg): Add j & K operand types.
+	(match_insn_m68k): Check and skip initial '.' arg character.
+	(m68k_scan_mask): Likewise.
+	* m68k-opc.c (m68k_opcodes): Add coprocessor instructions.
+
 2007-07-02  Alan Modra  <amodra@bigpond.net.au>
 
 	* Makefile.am: Run "make dep-am".
diff --git a/opcodes/m68k-dis.c b/opcodes/m68k-dis.c
index d964ef4..99d4533 100644
--- a/opcodes/m68k-dis.c
+++ b/opcodes/m68k-dis.c
@@ -280,6 +280,11 @@ fetch_arg (unsigned char *buffer,
       val = (buffer[1] >> 6);
       break;
 
+    case 'E':
+      FETCH_DATA (info, buffer + 3);
+      val = (buffer[2] >> 1);
+      break;
+
     case 'm':
       val = (buffer[1] & 0x40 ? 0x8 : 0)
 	| ((buffer[0] >> 1) & 0x7)
@@ -310,29 +315,8 @@ fetch_arg (unsigned char *buffer,
       abort ();
     }
 
-  switch (bits)
-    {
-    case 1:
-      return val & 1;
-    case 2:
-      return val & 3;
-    case 3:
-      return val & 7;
-    case 4:
-      return val & 017;
-    case 5:
-      return val & 037;
-    case 6:
-      return val & 077;
-    case 7:
-      return val & 0177;
-    case 8:
-      return val & 0377;
-    case 12:
-      return val & 07777;
-    default:
-      abort ();
-    }
+  /* bits is never too big.  */
+  return val & ((1 << bits) - 1);
 }
 
 /* Check if an EA is valid for a particular code.  This is required
@@ -685,6 +669,16 @@ print_insn_arg (const char *d,
       (*info->fprintf_func) (info->stream, "#%d", val);
       break;
 
+    case 'j':
+      val = fetch_arg (buffer, place, 3, info);
+      (*info->fprintf_func) (info->stream, "#%d", val+1);
+      break;
+
+    case 'K':
+      val = fetch_arg (buffer, place, 9, info);
+      (*info->fprintf_func) (info->stream, "#%d", val);
+      break;
+
     case 'M':
       if (place == 'h')
 	{
@@ -1214,6 +1208,7 @@ match_insn_m68k (bfd_vma memaddr,
   unsigned char *save_p;
   unsigned char *p;
   const char *d;
+  const char *args = best->args;
 
   struct private *priv = (struct private *) info->private_data;
   bfd_byte *buffer = priv->the_buffer;
@@ -1221,6 +1216,9 @@ match_insn_m68k (bfd_vma memaddr,
   void (* save_print_address) (bfd_vma, struct disassemble_info *)
     = info->print_address_func;
 
+  if (*args == '.')
+    args++;
+  
   /* Point at first word of argument data,
      and at descriptor for first argument.  */
   p = buffer + 2;
@@ -1229,7 +1227,7 @@ match_insn_m68k (bfd_vma memaddr,
      The only place this is stored in the opcode table is
      in the arguments--look for arguments which specify fields in the 2nd
      or 3rd words of the instruction.  */
-  for (d = best->args; *d; d += 2)
+  for (d = args; *d; d += 2)
     {
       /* I don't think it is necessary to be checking d[0] here;
 	 I suspect all this could be moved to the case statement below.  */
@@ -1276,8 +1274,8 @@ match_insn_m68k (bfd_vma memaddr,
      three words long.  */
   if (p - buffer < 6
       && (best->match & 0xffff) == 0xffff
-      && best->args[0] == '#'
-      && best->args[1] == 'w')
+      && args[0] == '#'
+      && args[1] == 'w')
     {
       /* Copy the one word argument into the usual location for a one
 	 word argument, to simplify printing it.  We can get away with
@@ -1291,15 +1289,13 @@ match_insn_m68k (bfd_vma memaddr,
 
   FETCH_DATA (info, p);
 
-  d = best->args;
-
   save_p = p;
   info->print_address_func = dummy_print_address;
   info->fprintf_func = (fprintf_ftype) dummy_printer;
 
   /* We scan the operands twice.  The first time we don't print anything,
      but look for errors.  */
-  for (; *d; d += 2)
+  for (d = args; *d; d += 2)
     {
       int eaten = print_insn_arg (d, buffer, p, memaddr + (p - buffer), info);
 
@@ -1329,7 +1325,7 @@ match_insn_m68k (bfd_vma memaddr,
   info->fprintf_func = save_printer;
   info->print_address_func = save_print_address;
 
-  d = best->args;
+  d = args;
 
   info->fprintf_func (info->stream, "%s", best->name);
 
@@ -1401,6 +1397,10 @@ m68k_scan_mask (bfd_vma memaddr, disassemble_info *info,
       const struct m68k_opcode *opc = opcodes[major_opcode][i];
       unsigned long opcode = opc->opcode;
       unsigned long match = opc->match;
+      const char *args = opc->args;
+
+      if (*args == '.')
+	args++;
 
       if (((0xff & buffer[0] & (match >> 24)) == (0xff & (opcode >> 24)))
 	  && ((0xff & buffer[1] & (match >> 16)) == (0xff & (opcode >> 16)))
@@ -1416,7 +1416,7 @@ m68k_scan_mask (bfd_vma memaddr, disassemble_info *info,
 	  /* Don't use for printout the variants of divul and divsl
 	     that have the same register number in two places.
 	     The more general variants will match instead.  */
-	  for (d = opc->args; *d; d += 2)
+	  for (d = args; *d; d += 2)
 	    if (d[1] == 'D')
 	      break;
 
@@ -1424,7 +1424,7 @@ m68k_scan_mask (bfd_vma memaddr, disassemble_info *info,
 	     point coprocessor instructions which use the same
 	     register number in two places, as above.  */
 	  if (*d == '\0')
-	    for (d = opc->args; *d; d += 2)
+	    for (d = args; *d; d += 2)
 	      if (d[1] == 't')
 		break;
 
@@ -1432,7 +1432,7 @@ m68k_scan_mask (bfd_vma memaddr, disassemble_info *info,
 	     wait for fmoveml.  */
 	  if (*d == '\0')
 	    {
-	      for (d = opc->args; *d; d += 2)
+	      for (d = args; *d; d += 2)
 		{
 		  if (d[0] == 's' && d[1] == '8')
 		    {
@@ -1446,7 +1446,7 @@ m68k_scan_mask (bfd_vma memaddr, disassemble_info *info,
 	  /* Don't match FPU insns with non-default coprocessor ID.  */
 	  if (*d == '\0')
 	    {
-	      for (d = opc->args; *d; d += 2)
+	      for (d = args; *d; d += 2)
 		{
 		  if (d[0] == 'I')
 		    {
diff --git a/opcodes/m68k-opc.c b/opcodes/m68k-opc.c
index 12cd14a..7f3b0d8 100644
--- a/opcodes/m68k-opc.c
+++ b/opcodes/m68k-opc.c
@@ -30,6 +30,10 @@
    be consecutive.  If they aren't, the assembler will bomb at
    runtime.  */
 
+/* Format strings consist of pairs of characters.  The first describes
+   the type of the operand and the second describes the encoding.
+   include/opcodes/m68k.h describes them in detail.  */
+
 const struct m68k_opcode m68k_opcodes[] =
 {
 {"abcd", 2,	one(0140400),	one(0170770), "DsDd", m68000up },
@@ -290,7 +294,31 @@ const struct m68k_opcode m68k_opcodes[] =
 {"cmpl", 6,	one(0006200),	one(0177700), "#lDs", mcfisa_a },
 {"cmpl", 2,	one(0130610),	one(0170770), "+s+d", m68000up },
 {"cmpl", 2,	one(0130200),	one(0170700), "*lDd", m68000up | mcfisa_a },
-
+  
+{"cp0bcbusy",2, one (0176300), one (01777770), "BW", mcfisa_a},
+{"cp1bcbusy",2, one (0177300), one (01777770), "BW", mcfisa_a},
+{"cp0nop",   4, two (0176000,0), two (01777477,0170777), "jE", mcfisa_a},
+{"cp1nop",   4, two (0177000,0), two (01777477,0170777), "jE", mcfisa_a},
+/* These all have 2 opcode words, but no fixed bits in the second
+   word.  We use a leading ' ' in the args string to indicate the
+   extra opcode word.  */
+{"cp0ldb",   6, one (0176000), one (01777700), ".pwR1jEK3", mcfisa_a},
+{"cp1ldb",   6, one (0177000), one (01777700), ".pwR1jEK3", mcfisa_a},
+{"cp0ldw",   6, one (0176100), one (01777700), ".pwR1jEK3", mcfisa_a},
+{"cp1ldw",   6, one (0177100), one (01777700), ".pwR1jEK3", mcfisa_a},
+{"cp0ldl",   6, one (0176200), one (01777700), ".pwR1jEK3", mcfisa_a},
+{"cp1ldl",   6, one (0177200), one (01777700), ".pwR1jEK3", mcfisa_a},
+{"cp0ld",    6, one (0176200), one (01777700), ".pwR1jEK3", mcfisa_a},
+{"cp1ld",    6, one (0177200), one (01777700), ".pwR1jEK3", mcfisa_a},
+{"cp0stb",   6, one (0176400), one (01777700), ".R1pwjEK3", mcfisa_a},
+{"cp1stb",   6, one (0177400), one (01777700), ".R1pwjEK3", mcfisa_a},
+{"cp0stw",   6, one (0176500), one (01777700), ".R1pwjEK3", mcfisa_a},
+{"cp1stw",   6, one (0177500), one (01777700), ".R1pwjEK3", mcfisa_a},
+{"cp0stl",   6, one (0176600), one (01777700), ".R1pwjEK3", mcfisa_a},
+{"cp1stl",   6, one (0177600), one (01777700), ".R1pwjEK3", mcfisa_a},
+{"cp0st",    6, one (0176600), one (01777700), ".R1pwjEK3", mcfisa_a},
+{"cp1st",    6, one (0177600), one (01777700), ".R1pwjEK3", mcfisa_a},
+  
 {"dbcc", 2,	one(0052310),	one(0177770), "DsBw", m68000up },
 {"dbcs", 2,	one(0052710),	one(0177770), "DsBw", m68000up },
 {"dbeq", 2,	one(0053710),	one(0177770), "DsBw", m68000up },