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author | Fernando Nasser <fnasser@redhat.com> | 2000-02-14 19:02:47 +0000 |
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committer | Fernando Nasser <fnasser@redhat.com> | 2000-02-14 19:02:47 +0000 |
commit | a7f8487eecca8e23ac7be6b152e1a139e620c2ab (patch) | |
tree | 9891b37781f5ae021e252f3c9a9da0d5f905d8f4 /opcodes | |
parent | 031d1bf1b8773982a7fa8ffb4b7a8cedf809991b (diff) | |
download | gdb-a7f8487eecca8e23ac7be6b152e1a139e620c2ab.zip gdb-a7f8487eecca8e23ac7be6b152e1a139e620c2ab.tar.gz gdb-a7f8487eecca8e23ac7be6b152e1a139e620c2ab.tar.bz2 |
2000-02-14 Fernando Nasser <fnasser@totem.to.cygnus.com>
* arm-dis.c: Change flavor name from atpcs-special to
special-atpcs to prevent name conflict in gdb.
(get_arm_regname_num_options, set_arm_regname_option,
get_arm_regnames): New functions. API to access the several
flavor of register names. Note: Used by gdb.
(print_insn_thumb): Use the register name entry from the currently
selected flavor for LR and PC.
Diffstat (limited to 'opcodes')
-rw-r--r-- | opcodes/ChangeLog | 10 | ||||
-rw-r--r-- | opcodes/arm-dis.c | 36 |
2 files changed, 43 insertions, 3 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 2325da3..33dea54 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,13 @@ +2000-02-14 Fernando Nasser <fnasser@totem.to.cygnus.com> + + * arm-dis.c: Change flavor name from atpcs-special to + special-atpcs to prevent name conflict in gdb. + (get_arm_regname_num_options, set_arm_regname_option, + get_arm_regnames): New functions. API to access the several + flavor of register names. Note: Used by gdb. + (print_insn_thumb): Use the register name entry from the currently + selected flavor for LR and PC. + 2000-02-10 Nick Clifton <nickc@cygnus.com> * mcore-opc.h (enum mcore_opclass): Add MULSH and OPSR diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index a3f44db..f131ada 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -66,7 +66,7 @@ static arm_regname regnames[] = { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }}, { "atpcs", "Select register names used in the ATPCS", { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }}, - { "atpcs-special", "Select special register names used in the ATPCS", + { "special-atpcs", "Select special register names used in the ATPCS", { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }} }; @@ -90,8 +90,38 @@ static int print_insn_arm PARAMS ((bfd_vma, struct disassemble_info *, long)) static int print_insn_thumb PARAMS ((bfd_vma, struct disassemble_info *, long)); static void parse_disassembler_options PARAMS ((char *)); static int print_insn PARAMS ((bfd_vma, struct disassemble_info *, boolean)); +int get_arm_regname_num_options (void); +int set_arm_regname_option (int option); +int get_arm_regnames (int option, const char **setname, + const char **setdescription, + const char ***register_names); /* Functions. */ +int +get_arm_regname_num_options (void) +{ + return NUM_ARM_REGNAMES; +} + +int +set_arm_regname_option (int option) +{ + int old = regname_selected; + regname_selected = option; + return old; +} + +int +get_arm_regnames (int option, const char **setname, + const char **setdescription, + const char ***register_names) +{ + *setname = regnames[option].name; + *setdescription = regnames[option].description; + *register_names = regnames[option].reg_names; + return 16; +} + static void arm_decode_shift (given, func, stream) long given; @@ -707,14 +737,14 @@ print_insn_thumb (pc, info, given) if (started) func (stream, ", "); started = 1; - func (stream, "lr"); + func (stream, arm_regnames[14] /* "lr" */); } if (domaskpc) { if (started) func (stream, ", "); - func (stream, "pc"); + func (stream, arm_regnames[15] /* "pc" */); } func (stream, "}"); |