Don't compare boolean values against TRUE or FALSE

bfd/
	* arc-got.h: Don't compare boolean values against TRUE or FALSE.
	* elf-m10300.c: Likewise.
	* elf.c: Likewise.
	* elf32-arc.c: Likewise.
	* elf32-bfin.c: Likewise.
	* elf32-m68k.c: Likewise.
	* elf32-nds32.c: Likewise.
	* elf32-tilepro.c: Likewise.
	* elflink.c: Likewise.
	* elfnn-aarch64.c: Likewise.
	* elfnn-riscv.c: Likewise.
	* elfxx-tilegx.c: Likewise.
	* mach-o.c: Likewise.
	* peXXigen.c: Likewise.
	* vms-alpha.c: Likewise.
	* vms-lib.c: Likewise.
opcodes/
	* aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
	* aarch64-dis.c: Likewise.
	* aarch64-gen.c: Likewise.
	* aarch64-opc.c: Likewise.
binutils/
	* strings.c: Don't compare boolean values against TRUE or FALSE.
gas/
	* config/tc-aarch64.c: Don't compare booleans against TRUE or FALSE.
	* config/tc-hppa.c: Likewise.
	* config/tc-mips.c: Likewise.
	* config/tc-score7.c: Likewise.
ld/
	* emultempl/elf32.em: Don't compare boolean values against TRUE or FALSE.
	* emultempl/pe.em: Likewise.
	* emultempl/pep.em: Likewise.
	* emultempl/xtensaelf.em: Likewise.

5 files changed, 20 insertions, 14 deletions

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 7c819d3..fba29e0 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,10 @@
+2017-05-18  Alan Modra  <amodra@gmail.com>
+
+	* aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
+	* aarch64-dis.c: Likewise.
+	* aarch64-gen.c: Likewise.
+	* aarch64-opc.c: Likewise.
+
 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
 	    Matthew Fortune  <matthew.fortune@imgtec.com>
 
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index 516bdab..6d2c75a 100644
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -498,9 +498,8 @@ aarch64_ins_limm_1 (const aarch64_operand *self,
 
   if (invert_p)
     imm = ~imm;
-  if (aarch64_logical_immediate_p (imm, esize, &value) == FALSE)
-    /* The constraint check should have guaranteed this wouldn't happen.  */
-    assert (0);
+  /* The constraint check should have guaranteed this wouldn't happen.  */
+  assert (aarch64_logical_immediate_p (imm, esize, &value));
 
   insert_fields (code, value, 0, 3, self->fields[2], self->fields[1],
 		 self->fields[0]);
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index b528af6..e5fe61f 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -2339,7 +2339,7 @@ convert_movewide_to_mov (aarch64_inst *inst)
       int is32 = inst->operands[0].qualifier == AARCH64_OPND_QLF_W;
       value = ~value;
       /* A MOVN has an immediate that could be encoded by MOVZ.  */
-      if (aarch64_wide_constant_p (value, is32, NULL) == TRUE)
+      if (aarch64_wide_constant_p (value, is32, NULL))
 	return 0;
     }
   inst->operands[1].imm.value = value;
@@ -2372,8 +2372,8 @@ convert_movebitmask_to_mov (aarch64_inst *inst)
   /* ORR has an immediate that could be generated by a MOVZ or MOVN
      instruction.  */
   if (inst->operands[0].reg.regno != 0x1f
-      && (aarch64_wide_constant_p (value, is32, NULL) == TRUE
-	  || aarch64_wide_constant_p (~value, is32, NULL) == TRUE))
+      && (aarch64_wide_constant_p (value, is32, NULL)
+	  || aarch64_wide_constant_p (~value, is32, NULL)))
     return 0;
 
   inst->operands[2].type = AARCH64_OPND_NIL;
@@ -2494,7 +2494,7 @@ determine_disassembling_preference (struct aarch64_inst *inst)
   opcode = inst->opcode;
 
   /* This opcode does not have an alias, so use itself.  */
-  if (opcode_has_alias (opcode) == FALSE)
+  if (!opcode_has_alias (opcode))
     return;
 
   alias = aarch64_find_alias_opcode (opcode);
diff --git a/opcodes/aarch64-gen.c b/opcodes/aarch64-gen.c
index 0ba2242..d2685dc 100644
--- a/opcodes/aarch64-gen.c
+++ b/opcodes/aarch64-gen.c
@@ -143,9 +143,9 @@ read_table (const struct aarch64_opcode* table)
       /* F_PSEUDO needs to be used together with F_ALIAS to indicate an alias
 	 opcode is a programmer friendly pseudo instruction available only in
 	 the assembly code (thus will not show up in the disassembly).  */
-      assert (pseudo_opcode_p (ent) == FALSE || alias_opcode_p (ent) == TRUE);
+      assert (!pseudo_opcode_p (ent) || alias_opcode_p (ent));
       /* Skip alias (inc. pseudo) opcode.  */
-      if (alias_opcode_p (ent) == TRUE)
+      if (alias_opcode_p (ent))
 	{
 	  index++;
 	  continue;
@@ -704,7 +704,7 @@ find_alias_opcode (const aarch64_opcode *opcode)
       /* The mask of an alias opcode must be equal to or a super-set (i.e.
 	 more constrained) of that of the aliased opcode; so is the base
 	 opcode value.  */
-      if (alias_opcode_p (ent) == TRUE
+      if (alias_opcode_p (ent)
 	  && (ent->mask & opcode->mask) == opcode->mask
 	  && (opcode->mask & ent->opcode) == (opcode->mask & opcode->opcode))
 	{
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index a52ea70..a47a754 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -1207,7 +1207,7 @@ aarch64_logical_immediate_p (uint64_t value, int esize, aarch64_insn *encoding)
   DEBUG_TRACE ("enter with 0x%" PRIx64 "(%" PRIi64 "), esize: %d", value,
 	       value, esize);
 
-  if (initialized == FALSE)
+  if (!initialized)
     {
       build_immediate_table ();
       initialized = TRUE;
@@ -2113,7 +2113,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
 	    uint64_t uimm = opnd->imm.value;
 	    if (opcode->op == OP_BIC)
 	      uimm = ~uimm;
-	    if (aarch64_logical_immediate_p (uimm, esize, NULL) == FALSE)
+	    if (!aarch64_logical_immediate_p (uimm, esize, NULL))
 	      {
 		set_other_error (mismatch_detail, idx,
 				 _("immediate out of range"));
@@ -2521,7 +2521,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
       switch (type)
 	{
 	case AARCH64_OPND_Rm_EXT:
-	  if (aarch64_extend_operator_p (opnd->shifter.kind) == FALSE
+	  if (!aarch64_extend_operator_p (opnd->shifter.kind)
 	      && opnd->shifter.kind != AARCH64_MOD_LSL)
 	    {
 	      set_other_error (mismatch_detail, idx,
@@ -2573,7 +2573,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
 	case AARCH64_OPND_Rm_SFT:
 	  /* ROR is not available to the shifted register operand in
 	     arithmetic instructions.  */
-	  if (aarch64_shift_operator_p (opnd->shifter.kind) == FALSE)
+	  if (!aarch64_shift_operator_p (opnd->shifter.kind))
 	    {
 	      set_other_error (mismatch_detail, idx,
 			       _("shift operator expected"));