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| author | H.J. Lu <hjl.tools@gmail.com> | 2020-01-17 07:07:55 -0800 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2020-01-17 07:07:55 -0800 |
| commit | 42e04b360158941f4d490a38cad14b11593854fa (patch) | |
| tree | 9bf46016eb0fbf13ee7dde413deed9aa4e6ef5f5 /opcodes | |
| parent | 26f42329caf1dcd4a410de61045208024156169f (diff) | |
| download | gdb-42e04b360158941f4d490a38cad14b11593854fa.zip gdb-42e04b360158941f4d490a38cad14b11593854fa.tar.gz gdb-42e04b360158941f4d490a38cad14b11593854fa.tar.bz2 | |
x86: Add {vex} pseudo prefix
There are 2-byte VEX prefix and 3-byte VEX prefix. 2-byte VEX prefix
can't encode all operands. By default, assembler tries 2-byte VEX prefix
first. {vex3} can be used to force 3-byte VEX prefix. This patch adds
{vex} pseudo prefix and keeps {vex2} for backward compatibility.
gas/
* config/tc-i386.c (_i386_insn): Replace vex_encoding_vex2
with vex_encoding_vex.
(parse_insn): Likewise.
* doc/c-i386.texi: Replace {vex2} with {vex}. Update {vex}
and {vex3} documentation.
* testsuite/gas/i386/pseudos.s: Replace 3 {vex2} tests with
{vex}.
* testsuite/gas/i386/x86-64-pseudos.s: Likewise.
opcodes/
* i386-opc.tbl: Add {vex} pseudo prefix.
* i386-tbl.h: Regenerated.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/i386-opc.tbl | 1 | ||||
| -rw-r--r-- | opcodes/i386-tbl.h | 12 |
3 files changed, 18 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 2d3b6d1..e48e566 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2020-01-17 H.J. Lu <hongjiu.lu@intel.com> + + * i386-opc.tbl: Add {vex} pseudo prefix. + * i386-tbl.h: Regenerated. + 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com> PR 25376 diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 73cd6c6..d8af259 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -879,6 +879,7 @@ rex.wrxb, 0, 0x4f, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ld {disp32}, 0, 0x1, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } {load}, 0, 0x2, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } {store}, 0, 0x3, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +{vex}, 0, 0x4, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } {vex2}, 0, 0x4, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } {vex3}, 0, 0x5, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } {evex}, 0, 0x6, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h index e9381bf..758d92b 100644 --- a/opcodes/i386-tbl.h +++ b/opcodes/i386-tbl.h @@ -7600,6 +7600,18 @@ const insn_template i386_optab[] = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, + { "{vex}", 0x4, None, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } } } }, { "{vex2}", 0x4, None, 0, 0, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |