CSKY: Add new arch CK860.

bfd/
        * bfd-in2.h (bfd_mach_ck860): New.
        * cpu-csky.c (arch_info_struct): Add item for CK860.

gas/
        * config/tc-csky.c (csky_archs): Add item for CK860,
        change ck810 and ck807's arch_flag.
        (csky_cpus): Add item for CK860.
        (md_begin): Enable DSP for CK810 and CK807 by default.
        (md_apply_fix): Fix CKCORE_TLS_IE32 relocation failure.
        * gas/testsuite/gas/csky/cskyv2_all.d: Change 'sync 0'
        to 'sync'.
        * gas/testsuite/gas/csky/cskyv2_all.s: Likewise.
        * gas/testsuite/gas/csky/cskyv2_ck860.d: New.
        * gas/testsuite/gas/csky/cskyv2_ck860.s: New.
        * gas/testsuite/gas/csky/enhance_dsp.d: Change plsli.u16
        to plsli.16.
        * gas/testsuite/gas/csky/enhance_dsp.s: Likewise.

include/
        * opcode/csky.h (CSKYV2_ISA_10E60): New.
        (CSKY_ARCH_860): New.

opcode/
        * csky-dis.c (csky_find_inst_info): Skip CK860's instructions
        in other CPUs to speed up disassembling.
        * csky-opc.h (csky_v2_opcodes): Add CK860's instructions,
        Change plsli.u16 to plsli.16, change sync's operand format.

Change-Id: I80ec1a9c0cc600d668082a9b91ae6d45b33ec0fc

3 files changed, 128 insertions, 6 deletions

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index effcd63..f2dbc22 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,10 @@
+2020-08-24  Cooper Qu  <cooper.qu@linux.alibaba.com>
+
+	* csky-dis.c (csky_find_inst_info): Skip CK860's instructions
+	in other CPUs to speed up disassembling.
+	* csky-opc.h (csky_v2_opcodes): Add CK860's instructions,
+	Change plsli.u16 to plsli.16, change sync's operand format.
+
 2020-08-21  Cooper Qu  <cooper.qu@linux.alibaba.com>
 
 	* csky-opc.h (csky_v2_opcodes): Add instruction bnezad.
diff --git a/opcodes/csky-dis.c b/opcodes/csky-dis.c
index bc6820a..537725b 100644
--- a/opcodes/csky-dis.c
+++ b/opcodes/csky-dis.c
@@ -159,6 +159,15 @@ csky_find_inst_info (struct csky_opcode_info const **pinfo,
   p = g_opcodeP;
   while (p->mnemonic)
     {
+      /* FIXME: Skip 860's instruction in other CPUs. It is not suitable.
+	 These codes need to be optimized.  */
+      if (((CSKY_ARCH_MASK & mach_flag) != CSKY_ARCH_860)
+	  && (p->isa_flag32 & CSKYV2_ISA_10E60))
+	{
+	  p++;
+	  continue;
+	}
+
       /* Get the opcode mask.  */
       for (i = 0; i < OP_TABLE_NUM; i++)
 	if (length == 2)
diff --git a/opcodes/csky-opc.h b/opcodes/csky-opc.h
index 3089403..796d375 100644
--- a/opcodes/csky-opc.h
+++ b/opcodes/csky-opc.h
@@ -3401,11 +3401,6 @@ const struct csky_opcode csky_v2_opcodes[] =
 			(0_3or21_24, FREGLIST_DASH, OPRND_SHIFT_0_BIT),
 			(16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)),
 	  CSKY_ISA_FLOAT_1E2),
-    DOP32 ("sync",
-	   OPCODE_INFO1 (0xc0000420,
-			 (21_25, IMM5b, OPRND_SHIFT_0_BIT)),
-	   OPCODE_INFO0 (0xc0000420),
-	   CSKYV2_ISA_E1),
     DOP32 ("idly",
 	   OPCODE_INFO1 (0xc0001c20,
 			 (21_25, OIMM5b_IDLY, OPRND_SHIFT_0_BIT)),
@@ -4681,6 +4676,117 @@ const struct csky_opcode csky_v2_opcodes[] =
 #undef _RELAX
 #define _RELAX      0
 
+  /* CK860 instructions.  */
+  OP32("sync.is",
+       OPCODE_INFO0(0xc2200420),
+       CSKYV2_ISA_10E60),
+  OP32("sync.i",
+       OPCODE_INFO0(0xc0200420),
+       CSKYV2_ISA_10E60),
+  OP32("sync.s",
+       OPCODE_INFO0(0xc2000420),
+       CSKYV2_ISA_10E60),
+  OP32("bar.brwarw",
+       OPCODE_INFO0(0xc000842f),
+       CSKYV2_ISA_10E60),
+  OP32("bar.brwarws",
+       OPCODE_INFO0(0xc200842f),
+       CSKYV2_ISA_10E60),
+  OP32("bar.brar",
+       OPCODE_INFO0(0xc0008425),
+       CSKYV2_ISA_10E60),
+  OP32("bar.brars",
+       OPCODE_INFO0(0xc2008425),
+       CSKYV2_ISA_10E60),
+  OP32("bar.bwaw",
+       OPCODE_INFO0(0xc000842a),
+       CSKYV2_ISA_10E60),
+  OP32("bar.bwaws",
+       OPCODE_INFO0(0xc200842a),
+       CSKYV2_ISA_10E60),
+  OP32("icache.iall",
+       OPCODE_INFO0(0xc1009020),
+       CSKYV2_ISA_10E60),
+  OP32("icache.ialls",
+       OPCODE_INFO0(0xc3009020),
+       CSKYV2_ISA_10E60),
+  OP32("icache.iva",
+       OPCODE_INFO1(0xc0a09020,
+		    (16_20, AREG, OPRND_SHIFT_0_BIT)),
+       CSKYV2_ISA_10E60),
+  OP32("dcache.iall",
+       OPCODE_INFO0(0xc1009420),
+       CSKYV2_ISA_10E60),
+  OP32("dcache.iva",
+       OPCODE_INFO1(0xc1609420,
+		    (16_20, AREG, OPRND_SHIFT_0_BIT)),
+       CSKYV2_ISA_10E60),
+  OP32("dcache.isw",
+       OPCODE_INFO1(0xc1409420,
+		    (16_20, AREG, OPRND_SHIFT_0_BIT)),
+       CSKYV2_ISA_10E60),
+  OP32("dcache.call",
+       OPCODE_INFO0(0xc0809420),
+       CSKYV2_ISA_10E60),
+  OP32("dcache.cva",
+       OPCODE_INFO1(0xc0e09420,
+		    (16_20, AREG, OPRND_SHIFT_0_BIT)),
+       CSKYV2_ISA_10E60),
+  OP32("dcache.cval1",
+       OPCODE_INFO1(0xc2e09420,
+		    (16_20, AREG, OPRND_SHIFT_0_BIT)),
+       CSKYV2_ISA_10E60),
+  OP32("dcache.csw",
+       OPCODE_INFO1(0xc0c09420,
+		    (16_20, AREG, OPRND_SHIFT_0_BIT)),
+       CSKYV2_ISA_10E60),
+  OP32("dcache.ciall",
+       OPCODE_INFO0(0xc1809420),
+       CSKYV2_ISA_10E60),
+  OP32("dcache.civa",
+       OPCODE_INFO1(0xc1e09420,
+		    (16_20, AREG, OPRND_SHIFT_0_BIT)),
+       CSKYV2_ISA_10E60),
+  OP32("dcache.cisw",
+       OPCODE_INFO1(0xc1c09420,
+		    (16_20, AREG, OPRND_SHIFT_0_BIT)),
+       CSKYV2_ISA_10E60),
+  OP32("tlbi.vaa",
+       OPCODE_INFO1(0xc0408820,
+		    (16_20, AREG, OPRND_SHIFT_0_BIT)),
+       CSKYV2_ISA_10E60),
+  OP32("tlbi.vaas",
+       OPCODE_INFO1(0xc2408820,
+		    (16_20, AREG, OPRND_SHIFT_0_BIT)),
+       CSKYV2_ISA_10E60),
+  OP32("tlbi.asid",
+       OPCODE_INFO1(0xc0208820,
+		    (16_20, AREG, OPRND_SHIFT_0_BIT)),
+       CSKYV2_ISA_10E60),
+  OP32("tlbi.asids",
+       OPCODE_INFO1(0xc2208820,
+		    (16_20, AREG, OPRND_SHIFT_0_BIT)),
+       CSKYV2_ISA_10E60),
+  OP32("tlbi.va",
+       OPCODE_INFO1(0xc0608820,
+		    (16_20, AREG, OPRND_SHIFT_0_BIT)),
+       CSKYV2_ISA_10E60),
+  OP32("tlbi.vas",
+       OPCODE_INFO1(0xc2608820,
+		    (16_20, AREG, OPRND_SHIFT_0_BIT)),
+       CSKYV2_ISA_10E60),
+  OP32("tlbi.all",
+       OPCODE_INFO0(0xc0008820),
+       CSKYV2_ISA_10E60),
+  OP32("tlbi.alls",
+       OPCODE_INFO0(0xc2008820),
+       CSKYV2_ISA_10E60),
+  DOP32("sync",
+       OPCODE_INFO0(0xc0000420),
+       OPCODE_INFO1(0xc0000420,
+		    (21_25, IMM5b, OPRND_SHIFT_0_BIT)),
+       CSKYV2_ISA_E1),
+
     /* The followings are enhance DSP instructions.  */
     DOP32_WITH_WORK ("bloop",
 		     OPCODE_INFO3 (0xe9c00000,
@@ -5325,7 +5431,7 @@ const struct csky_opcode csky_v2_opcodes[] =
 			(16_20, AREG, OPRND_SHIFT_0_BIT),
 			(21_25, AREG, OPRND_SHIFT_0_BIT)),
 	  CSKY_ISA_DSP_ENHANCE),
-    OP32 ("plsli.u16",
+    OP32 ("plsli.16",
 	  OPCODE_INFO3 (0xf800d400,
 			(0_4, AREG, OPRND_SHIFT_0_BIT),
 			(16_20, AREG, OPRND_SHIFT_0_BIT),