x86/Intel: correct AVX512 S/G disassembly

Commit 6ff00b5e12e7 ("x86/Intel: correct permitted operand sizes for
AVX512 scatter/gather") brought the assembler side of AVX512 S/G insn
handling in line with AVX2's, but the disassembler side was forgotten.
This has the benefit of
- allowing to fold a number of table entries,
- rendering a few #define-s and enumerators unused.

6 files changed, 42 insertions, 114 deletions

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index aa691ee..4f76456 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,26 @@
 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 
+	* opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
+	vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
+	REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
+	EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
+	EVEX_W_0F38C7_M_0_L_2): Delete.
+	(REG_EVEX_0F38C7_M_0_L_2): New.
+	(intel_operand_size): Handle VEX and EVEX the same for
+	vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
+	vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
+	(OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
+	vex_vsib_q_w_d_mode uses.
+	* i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
+	0F38A1, and 0F38A3 entries.
+	* i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
+	entry.
+	* i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
+	* i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
+	0F38A3 entries.
+
+2021-03-10  Jan Beulich  <jbeulich@suse.com>
+
 	* opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 	REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 	MOD_VEX_0FXOP_09_12): Rename to ...
diff --git a/opcodes/i386-dis-evex-len.h b/opcodes/i386-dis-evex-len.h
index 46f6eeb..60dec67 100644
--- a/opcodes/i386-dis-evex-len.h
+++ b/opcodes/i386-dis-evex-len.h
@@ -59,7 +59,7 @@ static const struct dis386 evex_len_table[][3] = {
   {
     { Bad_Opcode },
     { Bad_Opcode },
-    { VEX_W_TABLE (EVEX_W_0F38C7_M_0_L_2) },
+    { REG_TABLE (REG_EVEX_0F38C7_M_0_L_2) },
   },
 
   /* EVEX_LEN_0F3A00 */
diff --git a/opcodes/i386-dis-evex-reg.h b/opcodes/i386-dis-evex-reg.h
index 0ba1b0f..5ae6c00 100644
--- a/opcodes/i386-dis-evex-reg.h
+++ b/opcodes/i386-dis-evex-reg.h
@@ -42,20 +42,10 @@
   /* REG_EVEX_0F38C7_M_0_L_2_W_0 */
   {
     { Bad_Opcode },
-    { "vgatherpf0qps",  { MVexVSIBDQWpX }, PREFIX_DATA },
-    { "vgatherpf1qps",  { MVexVSIBDQWpX }, PREFIX_DATA },
+    { "vgatherpf0qp%XW",  { MVexVSIBQWpX }, PREFIX_DATA },
+    { "vgatherpf1qp%XW",  { MVexVSIBQWpX }, PREFIX_DATA },
     { Bad_Opcode },
     { Bad_Opcode },
-    { "vscatterpf0qps",  { MVexVSIBDQWpX }, PREFIX_DATA },
-    { "vscatterpf1qps",  { MVexVSIBDQWpX }, PREFIX_DATA },
-  },
-  /* REG_EVEX_0F38C7_M_0_L_2_W_1 */
-  {
-    { Bad_Opcode },
-    { "vgatherpf0qpd",  { MVexVSIBQWpX }, PREFIX_DATA },
-    { "vgatherpf1qpd",  { MVexVSIBQWpX }, PREFIX_DATA },
-    { Bad_Opcode },
-    { Bad_Opcode },
-    { "vscatterpf0qpd",  { MVexVSIBQWpX }, PREFIX_DATA },
-    { "vscatterpf1qpd",  { MVexVSIBQWpX }, PREFIX_DATA },
+    { "vscatterpf0qp%XW",  { MVexVSIBQWpX }, PREFIX_DATA },
+    { "vscatterpf1qp%XW",  { MVexVSIBQWpX }, PREFIX_DATA },
   },
diff --git a/opcodes/i386-dis-evex-w.h b/opcodes/i386-dis-evex-w.h
index ff89007..637ab84 100644
--- a/opcodes/i386-dis-evex-w.h
+++ b/opcodes/i386-dis-evex-w.h
@@ -555,31 +555,6 @@
     { Bad_Opcode },
     { "vpmultishiftqb",	{ XM, Vex, EXx }, PREFIX_DATA },
   },
-  /* EVEX_W_0F3891 */
-  {
-    { "vpgatherqd",	{ XMxmmq, MVexVSIBQDWpX }, PREFIX_DATA },
-    { "vpgatherqq",	{ XM, MVexVSIBQWpX }, 0 },
-  },
-  /* EVEX_W_0F3893 */
-  {
-    { "vgatherqps",	{ XMxmmq, MVexVSIBQDWpX }, PREFIX_DATA },
-    { "vgatherqpd",	{ XM, MVexVSIBQWpX }, 0 },
-  },
-  /* EVEX_W_0F38A1 */
-  {
-    { "vpscatterqd",	{ MVexVSIBQDWpX, XMxmmq }, PREFIX_DATA },
-    { "vpscatterqq",	{ MVexVSIBQWpX, XM }, 0 },
-  },
-  /* EVEX_W_0F38A3 */
-  {
-    { "vscatterqps",	{ MVexVSIBQDWpX, XMxmmq }, PREFIX_DATA },
-    { "vscatterqpd",	{ MVexVSIBQWpX, XM }, 0 },
-  },
-  /* EVEX_W_0F38C7_M_0_L_2 */
-  {
-    { REG_TABLE (REG_EVEX_0F38C7_M_0_L_2_W_0) },
-    { REG_TABLE (REG_EVEX_0F38C7_M_0_L_2_W_1) },
-  },
   /* EVEX_W_0F3A05 */
   {
     { Bad_Opcode },
diff --git a/opcodes/i386-dis-evex.h b/opcodes/i386-dis-evex.h
index eb88e5f..ec50104 100644
--- a/opcodes/i386-dis-evex.h
+++ b/opcodes/i386-dis-evex.h
@@ -456,9 +456,9 @@ static const struct dis386 evex_table[][256] = {
     { "vpshufbitqmb",  { XMask, Vex, EXx }, PREFIX_DATA },
     /* 90 */
     { "vpgatherd%DQ",	{ XM, MVexVSIBDWpX }, PREFIX_DATA },
-    { VEX_W_TABLE (EVEX_W_0F3891) },
+    { "vpgatherq%DQ",	{ XMGatherQ, MVexVSIBQWpX }, PREFIX_DATA },
     { "vgatherdp%XW",	{ XM, MVexVSIBDWpX}, PREFIX_DATA },
-    { VEX_W_TABLE (EVEX_W_0F3893) },
+    { "vgatherqp%XW",	{ XMGatherQ, MVexVSIBQWpX }, PREFIX_DATA },
     { Bad_Opcode },
     { Bad_Opcode },
     { "vfmaddsub132p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
@@ -474,9 +474,9 @@ static const struct dis386 evex_table[][256] = {
     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, PREFIX_DATA },
     /* A0 */
     { "vpscatterd%DQ",	{ MVexVSIBDWpX, XM }, PREFIX_DATA },
-    { VEX_W_TABLE (EVEX_W_0F38A1) },
+    { "vpscatterq%DQ",	{ MVexVSIBQWpX, XMGatherQ }, PREFIX_DATA },
     { "vscatterdp%XW",	{ MVexVSIBDWpX, XM }, PREFIX_DATA },
-    { VEX_W_TABLE (EVEX_W_0F38A3) },
+    { "vscatterqp%XW",	{ MVexVSIBQWpX, XMGatherQ }, PREFIX_DATA },
     { Bad_Opcode },
     { Bad_Opcode },
     { "vfmaddsub213p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 98d340c..6300ab9 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -411,9 +411,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
 #define MaskVex { OP_VEX, mask_mode }
 
 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
-#define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
-#define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 
 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
 
@@ -555,12 +553,8 @@ enum
 
   /* Operand size depends on the VEX.W bit, with VSIB dword indices.  */
   vex_vsib_d_w_dq_mode,
-  /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
-  vex_vsib_d_w_d_mode,
   /* Operand size depends on the VEX.W bit, with VSIB qword indices.  */
   vex_vsib_q_w_dq_mode,
-  /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
-  vex_vsib_q_w_d_mode,
   /* mandatory non-vector SIB.  */
   vex_sibmem_mode,
 
@@ -717,8 +711,7 @@ enum
   REG_EVEX_0F72,
   REG_EVEX_0F73,
   REG_EVEX_0F38C6_M_0_L_2,
-  REG_EVEX_0F38C7_M_0_L_2_W_0,
-  REG_EVEX_0F38C7_M_0_L_2_W_1
+  REG_EVEX_0F38C7_M_0_L_2
 };
 
 enum
@@ -1598,11 +1591,6 @@ enum
   EVEX_W_0F387A,
   EVEX_W_0F387B,
   EVEX_W_0F3883,
-  EVEX_W_0F3891,
-  EVEX_W_0F3893,
-  EVEX_W_0F38A1,
-  EVEX_W_0F38A3,
-  EVEX_W_0F38C7_M_0_L_2,
 
   EVEX_W_0F3A05,
   EVEX_W_0F3A08,
@@ -11263,51 +11251,10 @@ intel_operand_size (int bytemode, int sizeflag)
       if (!need_vex)
 	abort ();
 
-      if (!vex.evex)
-	{
-	  if (vex.w)
-	    oappend ("QWORD PTR ");
-	  else
-	    oappend ("DWORD PTR ");
-	}
+      if (vex.w)
+	oappend ("QWORD PTR ");
       else
-	{
-	  switch (vex.length)
-	    {
-	    case 128:
-	      oappend ("XMMWORD PTR ");
-	      break;
-	    case 256:
-	      oappend ("YMMWORD PTR ");
-	      break;
-	    case 512:
-	      oappend ("ZMMWORD PTR ");
-	      break;
-	    default:
-	      abort ();
-	    }
-	}
-      break;
-    case vex_vsib_q_w_d_mode:
-    case vex_vsib_d_w_d_mode:
-      if (!need_vex || !vex.evex)
-	abort ();
-
-      switch (vex.length)
-	{
-	case 128:
-	  oappend ("QWORD PTR ");
-	  break;
-	case 256:
-	  oappend ("XMMWORD PTR ");
-	  break;
-	case 512:
-	  oappend ("YMMWORD PTR ");
-	  break;
-	default:
-	  abort ();
-	}
-
+	oappend ("DWORD PTR ");
       break;
     case mask_bd_mode:
       if (!need_vex || vex.length != 128)
@@ -11502,9 +11449,7 @@ OP_E_memory (int bytemode, int sizeflag)
 	    /* fall through */
 	case vex_scalar_w_dq_mode:
 	case vex_vsib_d_w_dq_mode:
-	case vex_vsib_d_w_d_mode:
 	case vex_vsib_q_w_dq_mode:
-	case vex_vsib_q_w_d_mode:
 	case evex_x_gscat_mode:
 	  shift = vex.w ? 3 : 2;
 	  break;
@@ -11607,9 +11552,7 @@ OP_E_memory (int bytemode, int sizeflag)
 	  switch (bytemode)
 	    {
 	    case vex_vsib_d_w_dq_mode:
-	    case vex_vsib_d_w_d_mode:
 	    case vex_vsib_q_w_dq_mode:
-	    case vex_vsib_q_w_d_mode:
 	      if (!need_vex)
 		abort ();
 	      if (vex.evex)
@@ -11626,16 +11569,14 @@ OP_E_memory (int bytemode, int sizeflag)
 		  break;
 		case 256:
 		  if (!vex.w
-		      || bytemode == vex_vsib_q_w_dq_mode
-		      || bytemode == vex_vsib_q_w_d_mode)
+		      || bytemode == vex_vsib_q_w_dq_mode)
 		    indexes64 = indexes32 = names_ymm;
 		  else
 		    indexes64 = indexes32 = names_xmm;
 		  break;
 		case 512:
 		  if (!vex.w
-		      || bytemode == vex_vsib_q_w_dq_mode
-		      || bytemode == vex_vsib_q_w_d_mode)
+		      || bytemode == vex_vsib_q_w_dq_mode)
 		    indexes64 = indexes32 = names_zmm;
 		  else
 		    indexes64 = indexes32 = names_ymm;
@@ -12676,14 +12617,17 @@ OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
 	  break;
 	case 256:
 	  if (vex.w
-	      || (bytemode != vex_vsib_q_w_dq_mode
-		  && bytemode != vex_vsib_q_w_d_mode))
+	      || bytemode != vex_vsib_q_w_dq_mode)
 	    names = names_ymm;
 	  else
 	    names = names_xmm;
 	  break;
 	case 512:
-	  names = names_zmm;
+	  if (vex.w
+	      || bytemode != vex_vsib_q_w_dq_mode)
+	    names = names_zmm;
+	  else
+	    names = names_ymm;
 	  break;
 	default:
 	  abort ();
@@ -13419,7 +13363,6 @@ OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
 	{
 	case vex_mode:
 	case vex_vsib_q_w_dq_mode:
-	case vex_vsib_q_w_d_mode:
 	  names = names_xmm;
 	  break;
 	case dq_mode:
@@ -13449,7 +13392,6 @@ OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
 	  names = names_ymm;
 	  break;
 	case vex_vsib_q_w_dq_mode:
-	case vex_vsib_q_w_d_mode:
 	  names = vex.w ? names_ymm : names_xmm;
 	  break;
 	case mask_bd_mode: