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| author | Sudakshina Das <sudi.das@arm.com> | 2018-11-12 12:45:30 +0000 |
|---|---|---|
| committer | Sudakshina Das <sudi.das@arm.com> | 2018-11-12 12:45:30 +0000 |
| commit | 73b605ec3f546ff5a1c343ae02e6322aaa451bcf (patch) | |
| tree | bfb2b84b65a1814f00388c9654627aba9587b1ff /opcodes | |
| parent | d1b603a74e3a06da231727eb88947666e1885196 (diff) | |
| download | gdb-73b605ec3f546ff5a1c343ae02e6322aaa451bcf.zip gdb-73b605ec3f546ff5a1c343ae02e6322aaa451bcf.tar.gz gdb-73b605ec3f546ff5a1c343ae02e6322aaa451bcf.tar.bz2 | |
[BINUTILS, AARCH64, 1/8] Add support for Memory Tagging Extension for ARMv8.5-A
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions. Memory Tagging Extension is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.
This patch adds the new command line option and the new feature macros.
*** include/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_MEMTAG): New.
*** opcodes/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* aarch64-tbl.h (aarch64_feature_memtag): New.
(MEMTAG, MEMTAG_INSN): New.
*** gas/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (aarch64_features): Add "memtag"
as a new option.
* doc/c-aarch64.texi: Document the same.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/aarch64-tbl.h | 5 |
2 files changed, 10 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index bac6294..4fc11f7 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2018-11-12 Sudakshina Das <sudi.das@arm.com> + + * aarch64-tbl.h (aarch64_feature_memtag): New. + (MEMTAG, MEMTAG_INSN): New. + 2018-11-06 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (select_arm_features): Update bfd_mach_arm_8 diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index b73007d..5a4eaea 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -2171,6 +2171,8 @@ static const aarch64_feature_set aarch64_feature_predres = AARCH64_FEATURE (AARCH64_FEATURE_PREDRES, 0); static const aarch64_feature_set aarch64_feature_bti = AARCH64_FEATURE (AARCH64_FEATURE_BTI, 0); +static const aarch64_feature_set aarch64_feature_memtag = + AARCH64_FEATURE (AARCH64_FEATURE_V8_5 | AARCH64_FEATURE_MEMTAG, 0); #define CORE &aarch64_feature_v8 @@ -2205,6 +2207,7 @@ static const aarch64_feature_set aarch64_feature_bti = #define SB &aarch64_feature_sb #define PREDRES &aarch64_feature_predres #define BTI &aarch64_feature_bti +#define MEMTAG &aarch64_feature_memtag #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL } @@ -2268,6 +2271,8 @@ static const aarch64_feature_set aarch64_feature_bti = { NAME, OPCODE, MASK, CLASS, 0, PREDRES, OPS, QUALS, FLAGS, 0, 0, NULL } #define BTI_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, BTI, OPS, QUALS, FLAGS, 0, 0, NULL } +#define MEMTAG_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ + { NAME, OPCODE, MASK, CLASS, 0, MEMTAG, OPS, QUALS, FLAGS, 0, 0, NULL } struct aarch64_opcode aarch64_opcode_table[] = { |