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| author | Christoph Müllner <christoph.muellner@vrull.eu> | 2022-06-28 17:44:46 +0200 |
|---|---|---|
| committer | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2022-09-22 18:06:09 +0200 |
| commit | 4041e11db3ec3611921d10150572a92689aa3154 (patch) | |
| tree | bba8aafa39329d95a4cc101c5672a52689033b44 /opcodes | |
| parent | 73442230966a22b3238b2074691a71d7b4ed914a (diff) | |
| download | gdb-4041e11db3ec3611921d10150572a92689aa3154.zip gdb-4041e11db3ec3611921d10150572a92689aa3154.tar.gz gdb-4041e11db3ec3611921d10150572a92689aa3154.tar.bz2 | |
RISC-V: Add T-Head MAC vendor extension
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds the XTheadMac extension, a collection of
T-Head-specific multiply-accumulate instructions.
The 'th' prefix and the "XTheadMac" extension are documented
in a PR for the RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/riscv-opc.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 1113086..5d52989 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -1871,6 +1871,14 @@ const struct riscv_opcode riscv_opcodes[] = {"th.mveqz", 0, INSN_CLASS_XTHEADCONDMOV, "d,s,t", MATCH_TH_MVEQZ, MASK_TH_MVEQZ, match_opcode, 0}, {"th.mvnez", 0, INSN_CLASS_XTHEADCONDMOV, "d,s,t", MATCH_TH_MVNEZ, MASK_TH_MVNEZ, match_opcode, 0}, +/* Vendor-specific (T-Head) XTheadMac instructions. */ +{"th.mula", 0, INSN_CLASS_XTHEADMAC, "d,s,t", MATCH_TH_MULA, MASK_TH_MULA, match_opcode, 0}, +{"th.mulah", 0, INSN_CLASS_XTHEADMAC, "d,s,t", MATCH_TH_MULAH, MASK_TH_MULAH, match_opcode, 0}, +{"th.mulaw", 64, INSN_CLASS_XTHEADMAC, "d,s,t", MATCH_TH_MULAW, MASK_TH_MULAW, match_opcode, 0}, +{"th.muls", 0, INSN_CLASS_XTHEADMAC, "d,s,t", MATCH_TH_MULS, MASK_TH_MULS, match_opcode, 0}, +{"th.mulsh", 0, INSN_CLASS_XTHEADMAC, "d,s,t", MATCH_TH_MULSH, MASK_TH_MULSH, match_opcode, 0}, +{"th.mulsw", 64, INSN_CLASS_XTHEADMAC, "d,s,t", MATCH_TH_MULSW, MASK_TH_MULSW, match_opcode, 0}, + /* Vendor-specific (T-Head) XTheadSync instructions. */ {"th.sfence.vmas", 0, INSN_CLASS_XTHEADSYNC, "s,t",MATCH_TH_SFENCE_VMAS, MASK_TH_SFENCE_VMAS, match_opcode, 0}, {"th.sync", 0, INSN_CLASS_XTHEADSYNC, "", MATCH_TH_SYNC, MASK_TH_SYNC, match_opcode, 0}, |