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| author | Jim Wilson <jimw@sifive.com> | 2017-12-13 14:59:42 -0800 |
|---|---|---|
| committer | Jim Wilson <jimw@sifive.com> | 2017-12-13 14:59:42 -0800 |
| commit | 25982ee0222196381863a17dc135fc1d2763b385 (patch) | |
| tree | f3cbe90c0fbeffe0f4f10afb6b896ae92fdda8a3 /opcodes | |
| parent | b89641bab55496e52094282fabe146289c57b6d1 (diff) | |
| download | gdb-25982ee0222196381863a17dc135fc1d2763b385.zip gdb-25982ee0222196381863a17dc135fc1d2763b385.tar.gz gdb-25982ee0222196381863a17dc135fc1d2763b385.tar.bz2 | |
Add missing RISC-V fsrmi and fsflagsi instructions.
PR 22599
gas/
* testsuite/gas/riscv/fsxxi.d, testsuite/gas/riscv/fsxxi.s: New.
opcodes/
* riscv-opc.c (riscv_opcodes) <fsrmi, fsflagsi>: New.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/riscv-opc.c | 4 |
2 files changed, 9 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 5e8ad9f..dbc29fa 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2017-12-13 Jim Wilson <jimw@sifive.com> + + PR 22599 + * riscv-opc.c (riscv_opcodes) <fsrmi, fsflagsi>: New. + 2017-12-13 Dimitar Dimitrov <dimitar@dinux.eu> * disassemble.c: Enable disassembler_needs_relocs for PRU. diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 84cdea8..10448da 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -440,9 +440,13 @@ const struct riscv_opcode riscv_opcodes[] = {"frrm", "F", "d", MATCH_FRRM, MASK_FRRM, match_opcode, 0 }, {"fsrm", "F", "s", MATCH_FSRM, MASK_FSRM | MASK_RD, match_opcode, 0 }, {"fsrm", "F", "d,s", MATCH_FSRM, MASK_FSRM, match_opcode, 0 }, +{"fsrmi", "F", "d,Z", MATCH_FSRMI, MASK_FSRMI, match_opcode, 0 }, +{"fsrmi", "F", "Z", MATCH_FSRMI, MASK_FSRMI | MASK_RD, match_opcode, 0 }, {"frflags", "F", "d", MATCH_FRFLAGS, MASK_FRFLAGS, match_opcode, 0 }, {"fsflags", "F", "s", MATCH_FSFLAGS, MASK_FSFLAGS | MASK_RD, match_opcode, 0 }, {"fsflags", "F", "d,s", MATCH_FSFLAGS, MASK_FSFLAGS, match_opcode, 0 }, +{"fsflagsi", "F", "d,Z", MATCH_FSFLAGSI, MASK_FSFLAGSI, match_opcode, 0 }, +{"fsflagsi", "F", "Z", MATCH_FSFLAGSI, MASK_FSFLAGSI | MASK_RD, match_opcode, 0 }, {"flw", "32C", "D,Cm(Cc)", MATCH_C_FLWSP, MASK_C_FLWSP, match_opcode, INSN_ALIAS }, {"flw", "32C", "CD,Ck(Cs)", MATCH_C_FLW, MASK_C_FLW, match_opcode, INSN_ALIAS }, {"flw", "F", "D,o(s)", MATCH_FLW, MASK_FLW, match_opcode, 0 }, |