RISC-V: Support XVentanaCondOps extension

    Ventana Micro has published the specification for their
    XVentanaCondOps ("conditional ops") extension at
      https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf
    which contains two new instructions
      - vt.maskc
      - vt.maskcn
    that can be used in constructing branchless sequences for
    various conditional-arithmetic, conditional-logical, and
    conditional-select operations.

    To support such vendor-defined instructions in the mainline binutils,
    this change also adds a riscv_supported_vendor_x_ext secondary
    dispatch table (but also keeps the behaviour of allowing any unknow
    X-extension to be specified in addition to the known ones from this
    table).

    As discussed, this change already includes the planned/agreed future
    requirements for X-extensions (which are likely to be captured in the
    riscv-toolchain-conventions repository):
      - a public specification document is available (see above) and is
        referenced from the gas-documentation
      - the naming follows chapter 27 of the RISC-V ISA specification
      - instructions are prefixed by a vendor-prefix (vt for Ventana)
        to ensure that they neither conflict with future standard
        extensions nor clash with other vendors

    bfd/ChangeLog:

            * elfxx-riscv.c (riscv_get_default_ext_version): Add riscv_supported_vendor_x_ext.
            (riscv_multi_subset_supports): Recognize INSN_CLASS_XVENTANACONDOPS.

    gas/ChangeLog:

            * doc/c-riscv.texi: Add section to list custom extensions and
              their documentation URLs.
            * testsuite/gas/riscv/x-ventana-condops.d: New test.
            * testsuite/gas/riscv/x-ventana-condops.s: New test.

    include/ChangeLog:

            * opcode/riscv-opc.h Add vt.maskc and vt.maskcn.
            * opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_XVENTANACONDOPS.

    opcodes/ChangeLog:

            * riscv-opc.c: Add vt.maskc and vt.maskcn.

    Series-version: 1
    Series-to: binutils@sourceware.org
    Series-cc: Kito Cheng <kito.cheng@sifive.com>
    Series-cc: Nelson Chu <nelson.chu@sifive.com>
    Series-cc: Greg Favor <gfavor@ventanamicro.com>
    Series-cc: Christoph Muellner <cmuellner@gcc.gnu.org>

1 files changed, 4 insertions, 0 deletions

diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index d9d69cd..1c3d9b0 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2009,6 +2009,10 @@ const struct riscv_opcode riscv_opcodes[] =
 {"th.sync.is",       0, INSN_CLASS_XTHEADSYNC,  "",   MATCH_TH_SYNC_IS,       MASK_TH_SYNC_IS,       match_opcode, 0},
 {"th.sync.s",        0, INSN_CLASS_XTHEADSYNC,  "",   MATCH_TH_SYNC_S,        MASK_TH_SYNC_S,        match_opcode, 0},
 
+/* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
+{"vt.maskc",    0, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 },
+{"vt.maskcn",   0, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKCN, MASK_VT_MASKCN, match_opcode, 0 },
+
 /* Terminate the list.  */
 {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
 };