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| author | Maciej W. Rozycki <macro@orcam.me.uk> | 2021-05-29 03:26:32 +0200 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@orcam.me.uk> | 2021-05-29 03:26:32 +0200 |
| commit | b930964c425533f2344c6b26d4af17200bb42928 (patch) | |
| tree | 949f69c94cfa475f597e0cd80128fb7fe13f3f6b /opcodes | |
| parent | 21629cf8bc2b16d3c75dff0c3f1222b714bf90c2 (diff) | |
| download | gdb-b930964c425533f2344c6b26d4af17200bb42928.zip gdb-b930964c425533f2344c6b26d4af17200bb42928.tar.gz gdb-b930964c425533f2344c6b26d4af17200bb42928.tar.bz2 | |
MIPS/opcodes: Disassemble the RFE instruction
Fix a commit b015e599c772 ("[MIPS] Add new virtualization instructions"),
<https://sourceware.org/ml/binutils/2013-05/msg00118.html>, regression
and bring the disassembly of the RFE instruction back for the relevant
ISA levels.
It is because the "rfe" opcode table entry was incorrectly moved behind
the catch-all generic "c0" entry for CP0 instructions, causing output
like:
00: 42000010 c0 0x10
to be produced rather than:
00: 42000010 rfe
even for ISA levels that do include the RFE instruction.
Move the "rfe" entry ahead of "c0" then, correcting the problem. Add a
suitable test case.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
of "c0".
gas/
* testsuite/gas/mips/rfe.d: New test.
* testsuite/gas/mips/rfe.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new test.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/mips-opc.c | 5 |
2 files changed, 8 insertions, 2 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 795391d..2e93d56 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,10 @@ 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk> + * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead + of "c0". + +2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk> + * mips-dis.c (mips_cp1_names_mips): New variable. (mips_arch_choices): Use it rather than `mips_cp1_names_numeric' for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120", diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index 812fcc6..210d014 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -3399,6 +3399,9 @@ const struct mips_opcode mips_builtin_opcodes[] = {"ginvi", "s", 0x7c00003d, 0xfc1fffff, RD_1, 0, 0, GINV, 0 }, {"ginvt", "s,+\\", 0x7c0000bd, 0xfc1ffcff, RD_1, 0, 0, GINV, 0 }, +/* RFE conflicts with the new Virt spec instruction tlbgp. */ +{"rfe", "", 0x42000010, 0xffffffff, 0, 0, I1|T3, 0, 0 }, + /* No hazard protection on coprocessor instructions--they shouldn't change the state of the processor and if they do it's up to the user to put in nops as necessary. These are at the end so that the @@ -3411,8 +3414,6 @@ const struct mips_opcode mips_builtin_opcodes[] = {"cop1", "C", 0, (int) M_COP1, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, {"cop2", "C", 0, (int) M_COP2, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2 }, {"cop3", "C", 0, (int) M_COP3, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2 }, -/* RFE conflicts with the new Virt spec instruction tlbgp. */ -{"rfe", "", 0x42000010, 0xffffffff, 0, 0, I1|T3, 0, 0 }, }; #define MIPS_NUM_OPCODES \ |