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| author | Jan Beulich <jbeulich@suse.com> | 2021-03-29 12:03:31 +0200 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2021-03-29 12:03:31 +0200 |
| commit | 9df6f676c2c7280dc0c419c43927a07c6359814d (patch) | |
| tree | ebc12d8d2d39793ca514b4f004494a17c5a6710f /opcodes | |
| parent | 389d00a5e5b1fa6fcd9eda747b17ef73f58eb693 (diff) | |
| download | gdb-9df6f676c2c7280dc0c419c43927a07c6359814d.zip gdb-9df6f676c2c7280dc0c419c43927a07c6359814d.tar.gz gdb-9df6f676c2c7280dc0c419c43927a07c6359814d.tar.bz2 | |
x86: shrink some struct insn_template fields
Now that all base opcodes are only at most 2 bytes in size, shrink its
template field to just as much. By also shrinking extension_opcode and
operands to just what they really need, we can free up an entire 32-bit
slot (plus 4 left bits past the bitfields themselves).
At present this alters sizeof(struct insn_template) only for 32-bit
builds. In 64-bit builds it instead leaves a padding hole that will
allow to buffer future growth of other fields (opcode_modifier,
cpu_flags, operand_types[]).
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 6 | ||||
| -rw-r--r-- | opcodes/i386-opc.h | 8 |
2 files changed, 10 insertions, 4 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 82a1c5c..ff0ecf3 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,11 @@ 2021-03-29 Jan Beulich <jbeulich@suse.com> + * i386-opc.h (struct insn_template): Shrink base_opcode to 16 + bits. Shrink extension_opcode to 9 bits. Make it signed. Change + value of None. Shrink operands to 3 bits. + +2021-03-29 Jan Beulich <jbeulich@suse.com> + * i386-gen.c (process_i386_opcode_modifier): New parameter "space". (output_i386_opcode): New local variable "space". Adjust diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index 9ed0793..115895c 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -917,7 +917,7 @@ typedef struct insn_template /* base_opcode is the fundamental opcode byte without optional prefix(es). */ - unsigned int base_opcode; + unsigned int base_opcode:16; #define Opcode_D 0x2 /* Direction bit: set if Reg --> Regmem; unset if Regmem --> Reg. */ @@ -934,8 +934,8 @@ typedef struct insn_template AMD 3DNow! instructions. If this template has no extension opcode (the usual case) use None Instructions */ - unsigned short extension_opcode; -#define None 0xffff /* If no extension_opcode is possible. */ + signed int extension_opcode:9; +#define None (-1) /* If no extension_opcode is possible. */ /* Pseudo prefixes. */ #define Prefix_Disp8 0 /* {disp8} */ @@ -950,7 +950,7 @@ typedef struct insn_template #define Prefix_NoOptimize 9 /* {nooptimize} */ /* how many operands */ - unsigned char operands; + unsigned int operands:3; /* the bits in opcode_modifier are used to generate the final opcode from the base_opcode. These bits also are used to detect alternate forms of |