Add support for V850E3V5 architecture

3 files changed, 955 insertions, 197 deletions

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index c593d9d..b14b2bf 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,9 +1,14 @@
+2013-01-24  Nick Clifton  <nickc@redhat.com>
+
+	* v850-dis.c: Add support for e3v5 architecture.
+	* v850-opc.c: Likewise.
+
 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
 
 	* aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
 	* aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
 	* aarch64-opc.c (operand_general_constraint_met_p): For
-	AARCH64_MOD_LSL, move the range check on the shift amount before the 
+	AARCH64_MOD_LSL, move the range check on the shift amount before the
 	alignment check; change to call set_sft_amount_out_of_range_error
 	instead of set_imm_out_of_range_error.
 	* aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
diff --git a/opcodes/v850-dis.c b/opcodes/v850-dis.c
index 7d2e720..648846b 100644
--- a/opcodes/v850-dis.c
+++ b/opcodes/v850-dis.c
@@ -1,6 +1,5 @@
 /* Disassemble V850 instructions.
-   Copyright 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2005, 2007, 2010,
-   2012  Free Software Foundation, Inc.
+   Copyright 1996-2013 Free Software Foundation, Inc.
 
    This file is part of the GNU opcodes library.
 
@@ -22,6 +21,7 @@
 
 #include "sysdep.h"
 #include <stdio.h>
+#include <string.h>
 #include "opcode/v850.h"
 #include "dis-asm.h"
 #include "opintl.h"
@@ -59,8 +59,37 @@ static const char *const v850_float_cc_names[] =
 };
 
 
+static const char *const v850_vreg_names[] =
+{
+  "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7", "vr8", "vr9",
+  "vr10", "vr11", "vr12", "vr13", "vr14", "vr15", "vr16", "vr17", "vr18",
+  "vr19", "vr20", "vr21", "vr22", "vr23", "vr24", "vr25", "vr26", "vr27",
+  "vr28", "vr29", "vr30", "vr31"
+};
+
+static const char *const v850_cacheop_names[] =
+{
+  "chbii", "cibii", "cfali", "cisti", "cildi", "chbid", "chbiwbd",
+  "chbwbd", "cibid", "cibiwbd", "cibwbd", "cfald", "cistd", "cildd"
+};
+
+static const int const v850_cacheop_codes[] =
+{
+  0x00, 0x20, 0x40, 0x60, 0x61, 0x04, 0x06,
+  0x07, 0x24, 0x26, 0x27, 0x44, 0x64, 0x65, -1
+};
+
+static const char *const v850_prefop_names[] =
+{ "prefi", "prefd" };
+
+static const int const v850_prefop_codes[] =
+{ 0x00, 0x04, -1};
+
 static void
-print_value (int flags, bfd_vma memaddr, struct disassemble_info *info, long value)
+print_value (int flags,
+	     bfd_vma memaddr,
+	     struct disassemble_info *info,
+	     long value)
 {
   if (flags & V850_PCREL)
     {
@@ -78,7 +107,8 @@ print_value (int flags, bfd_vma memaddr, struct disassemble_info *info, long val
           info->fprintf_func (info->stream, "%lu", value);
         }
     }
-  else if (flags & V850E_IMMEDIATE32)
+  else if ((flags & V850E_IMMEDIATE32)
+	   || (flags & V850E_IMMEDIATE16HI))
     {
       info->fprintf_func (info->stream, "0x%lx", value);
     }
@@ -186,9 +216,12 @@ get_operand_value (const struct v850_operand *operand,
 
 
 static int
-disassemble (bfd_vma memaddr, struct disassemble_info *info, int bytes_read, unsigned long insn)
+disassemble (bfd_vma memaddr,
+	     struct disassemble_info *info,
+	     int bytes_read,
+	     unsigned long insn)
 {
-  struct v850_opcode *op = (struct v850_opcode *)v850_opcodes;
+  struct v850_opcode *op = (struct v850_opcode *) v850_opcodes;
   const struct v850_operand *operand;
   int match = 0;
   int target_processor;
@@ -215,6 +248,10 @@ disassemble (bfd_vma memaddr, struct disassemble_info *info, int bytes_read, uns
     case bfd_mach_v850e2v3:
       target_processor = PROCESSOR_V850E2V3;
       break;
+
+    case bfd_mach_v850e3v5:
+      target_processor = PROCESSOR_V850E3V5;
+      break;
     }
 
   /* If this is a two byte insn, then mask off the high bits.  */
@@ -242,7 +279,8 @@ disassemble (bfd_vma memaddr, struct disassemble_info *info, int bytes_read, uns
 
 	      operand = &v850_operands[*opindex_ptr];
 
-	      value = get_operand_value (operand, insn, bytes_read, memaddr, info, 1, &invalid);
+	      value = get_operand_value (operand, insn, bytes_read, memaddr,
+					 info, 1, &invalid);
 
 	      if (invalid)
 		goto next_opcode;
@@ -291,7 +329,8 @@ disassemble (bfd_vma memaddr, struct disassemble_info *info, int bytes_read, uns
 
 	      operand = &v850_operands[*opindex_ptr];
 
-	      value = get_operand_value (operand, insn, bytes_read, memaddr, info, 0, 0);
+	      value = get_operand_value (operand, insn, bytes_read, memaddr,
+					 info, 0, 0);
 
 	      /* The first operand is always output without any
 		 special handling.
@@ -331,8 +370,24 @@ disassemble (bfd_vma memaddr, struct disassemble_info *info, int bytes_read, uns
 		  info->fprintf_func (info->stream, "%s[", prefix);
 		  square = TRUE;
 		}
+	      else if (   (strcmp ("stc.w", op->name) == 0
+			|| strcmp ("cache", op->name) == 0
+			|| strcmp ("pref",  op->name) == 0)
+		       && opnum == 2 && opnum == memop)
+		{
+		  info->fprintf_func (info->stream, ", [");
+		  square = TRUE;
+		}
+	      else if (   (strcmp (op->name, "pushsp") == 0
+			|| strcmp (op->name, "popsp") == 0
+			|| strcmp (op->name, "dbpush" ) == 0)
+		       && opnum == 2)
+		{
+		  info->fprintf_func (info->stream, "-");
+		}
 	      else if (opnum > 1
-		       && (v850_operands[*(opindex_ptr - 1)].flags & V850_OPERAND_DISP) != 0
+		       && (v850_operands[*(opindex_ptr - 1)].flags
+			   & V850_OPERAND_DISP) != 0
 		       && opnum == memop)
 		{
 		  info->fprintf_func (info->stream, "%s[", prefix);
@@ -351,22 +406,33 @@ disassemble (bfd_vma memaddr, struct disassemble_info *info, int bytes_read, uns
 	      else if (opnum > 1)
 		info->fprintf_func (info->stream, ", %s", prefix);
 
- 	      /* Extract the flags, ignoring ones which do not effect disassembly output.  */
+ 	      /* Extract the flags, ignoring ones which do not
+		 effect disassembly output.  */
 	      flag = operand->flags & (V850_OPERAND_REG
 				       | V850_REG_EVEN
 				       | V850_OPERAND_EP
 				       | V850_OPERAND_SRG
 				       | V850E_OPERAND_REG_LIST
 				       | V850_OPERAND_CC
+				       | V850_OPERAND_VREG
+				       | V850_OPERAND_CACHEOP
+				       | V850_OPERAND_PREFOP
 				       | V850_OPERAND_FLOAT_CC);
 
 	      switch (flag)
 		{
-		case V850_OPERAND_REG:  info->fprintf_func (info->stream, "%s", v850_reg_names[value]); break;
-		case (V850_OPERAND_REG|V850_REG_EVEN):  info->fprintf_func (info->stream, "%s", v850_reg_names[value*2]); break;
-		case V850_OPERAND_EP:   info->fprintf_func (info->stream, "ep"); break;
-		case V850_OPERAND_SRG:  info->fprintf_func (info->stream, "%s", v850_sreg_names[value]); break;
-
+		case V850_OPERAND_REG:
+		  info->fprintf_func (info->stream, "%s", v850_reg_names[value]);
+		  break;
+		case (V850_OPERAND_REG|V850_REG_EVEN):
+		  info->fprintf_func (info->stream, "%s", v850_reg_names[value * 2]);
+		  break;
+		case V850_OPERAND_EP:
+		  info->fprintf_func (info->stream, "ep");
+		  break;
+		case V850_OPERAND_SRG:
+		  info->fprintf_func (info->stream, "%s", v850_sreg_names[value]);
+		  break;
 		case V850E_OPERAND_REG_LIST:
 		  {
 		    static int list12_regs[32]   = { 30, 0, 0, 0, 0, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
@@ -376,13 +442,12 @@ disassemble (bfd_vma memaddr, struct disassemble_info *info, int bytes_read, uns
 		    unsigned long int mask = 0;
 		    int pc = 0;
 
-
 		    switch (operand->shift)
 		      {
 		      case 0xffe00001: regs = list12_regs; break;
 		      default:
 			/* xgettext:c-format */
-			fprintf (stderr, _("unknown operand shift: %x\n"), operand->shift );
+			fprintf (stderr, _("unknown operand shift: %x\n"), operand->shift);
 			abort ();
 		      }
 
@@ -443,8 +508,53 @@ disassemble (bfd_vma memaddr, struct disassemble_info *info, int bytes_read, uns
 		  }
 		  break;
 
-		case V850_OPERAND_CC:   info->fprintf_func (info->stream, "%s", v850_cc_names[value]); break;
-		case V850_OPERAND_FLOAT_CC:   info->fprintf_func (info->stream, "%s", v850_float_cc_names[value]); break;
+		case V850_OPERAND_CC:
+		  info->fprintf_func (info->stream, "%s", v850_cc_names[value]);
+		  break;
+
+		case V850_OPERAND_FLOAT_CC:
+		  info->fprintf_func (info->stream, "%s", v850_float_cc_names[value]);
+		  break;
+
+		case V850_OPERAND_CACHEOP:
+		  {
+		    int idx;
+
+		    for (idx = 0; v850_cacheop_codes[idx] != -1; idx++)
+		      {
+			if (value == v850_cacheop_codes[idx])
+			  {
+			    info->fprintf_func (info->stream, "%s",
+						v850_cacheop_names[idx]);
+			    goto MATCH_CACHEOP_CODE;
+			  }
+		      }
+		    info->fprintf_func (info->stream, "%d", (int) value);
+		  }
+		MATCH_CACHEOP_CODE:
+		  break;
+
+		case V850_OPERAND_PREFOP:
+		  {
+		    int idx;
+
+		    for (idx = 0; v850_prefop_codes[idx] != -1; idx++)
+		      {
+			if (value == v850_prefop_codes[idx])
+			  {
+			    info->fprintf_func (info->stream, "%s",
+			      v850_prefop_names[idx]);
+			    goto MATCH_PREFOP_CODE;
+			  }
+		      }
+		    info->fprintf_func (info->stream, "%d", (int) value);
+		  }
+		MATCH_PREFOP_CODE:
+		  break;
+
+		case V850_OPERAND_VREG:
+		  info->fprintf_func (info->stream, "%s", v850_vreg_names[value]);
+		  break;
 
 		default:
 		  print_value (operand->flags, memaddr, info, value);
@@ -496,6 +606,10 @@ print_insn_v850 (bfd_vma memaddr, struct disassemble_info * info)
     case bfd_mach_v850e2v3:
       target_processor = PROCESSOR_V850E2V3;
       break;
+
+    case bfd_mach_v850e3v5:
+      target_processor = PROCESSOR_V850E3V5;
+      break;
     }
 
   status = info->read_memory_func (memaddr, buffer, 2, info);
@@ -518,8 +632,7 @@ print_insn_v850 (bfd_vma memaddr, struct disassemble_info * info)
 
   /* Special case.  */
   if (length == 0
-      && (target_processor == PROCESSOR_V850E2
-	  || target_processor == PROCESSOR_V850E2V3))
+      && ((target_processor & PROCESSOR_V850E2_UP) != 0))
     {
       if ((insn & 0xffff) == 0x02e0		/* jr 32bit */
 	  && !status2 && (insn2 & 0x1) == 0)
@@ -542,7 +655,20 @@ print_insn_v850 (bfd_vma memaddr, struct disassemble_info * info)
     }
 
   if (length == 0
-      && target_processor == PROCESSOR_V850E2V3)
+      && ((target_processor & PROCESSOR_V850E3V5_UP) != 0))
+    {
+      if (   ((insn & 0xffe0) == 0x07a0		/* ld.dw 23bit (v850e3v5) */
+	      && !status2 && (insn2 & 0x000f) == 0x0009)
+	  || ((insn & 0xffe0) == 0x07a0		/* st.dw 23bit (v850e3v5) */
+	      && !status2 && (insn2 & 0x000f) == 0x000f))
+	{
+	  length = 4;
+	  code_length = 6;
+	}
+    }
+
+  if (length == 0
+      && ((target_processor & PROCESSOR_V850E2V3_UP) != 0))
     {
       if (((insn & 0xffe0) == 0x0780		/* ld.b 23bit */
 	   && !status2 && (insn2 & 0x000f) == 0x0005)
@@ -626,6 +752,10 @@ print_insn_v850 (bfd_vma memaddr, struct disassemble_info * info)
   if (length == 2)
     insn &= 0xffff;
 
+  /* when the last 2 bytes of section is 0xffff, length will be 0 and cause infinitive loop */
+  if (length == 0)
+    return -1;
+
   match = disassemble (memaddr, info, length, insn);
 
   if (!match)
diff --git a/opcodes/v850-opc.c b/opcodes/v850-opc.c
index 806651f..0b25f3b 100644
--- a/opcodes/v850-opc.c
+++ b/opcodes/v850-opc.c
@@ -1,6 +1,5 @@
 /* Assemble V850 instructions.
-   Copyright 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2005, 2007, 2010,
-   2012 Free Software Foundation, Inc.
+   Copyright 1996-2013 Free Software Foundation, Inc.
 
    This file is part of the GNU opcodes library.
 
@@ -25,7 +24,6 @@
 #include "bfd.h"
 #include "opintl.h"
 
-
 /* Regular opcodes.  */
 #define OP(x)		((x & 0x3f) << 5)
 #define OP_MASK		OP (0x3f)
@@ -60,7 +58,13 @@ static const char * immediate_out_of_range = N_ ("immediate value is out of rang
 static const char * branch_out_of_range = N_ ("branch value out of range");
 static const char * branch_out_of_range_and_odd_offset = N_ ("branch value not in range and to odd offset");
 static const char * branch_to_odd_offset = N_ ("branch to odd offset");
-
+static const char * pos_out_of_range = N_ ("position value is out of range");
+static const char * width_out_of_range = N_ ("width value is out of range");
+static const char * selid_out_of_range = N_ ("SelID is out of range");
+static const char * vector8_out_of_range = N_ ("vector8 is out of range");
+static const char * vector5_out_of_range = N_ ("vector5 is out of range");
+static const char * imm10_out_of_range = N_ ("imm10 is out of range");
+static const char * sr_selid_out_of_range = N_ ("SR/SelID is out of range");
 
 int
 v850_msg_is_out_of_range (const char* msg)
@@ -114,7 +118,7 @@ insert_i5div2 (unsigned long insn, long value, const char ** errmsg)
 
   value = (32 - value)/2;
 
-  return (insn | ((value << (2+16)) & 0x3c0000));
+  return insn | ((value << (2 + 16)) & 0x3c0000);
 }
 
 static unsigned long
@@ -143,7 +147,7 @@ insert_i5div3 (unsigned long insn, long value, const char ** errmsg)
 
   value = (32 - value)/2;
 
-  return (insn | ((value << (2+16)) & 0x3c0000));
+  return insn | ((value << (2+16)) & 0x3c0000);
 }
 
 static unsigned long
@@ -429,6 +433,22 @@ insert_d23 (unsigned long insn, long value, const char ** errmsg)
 }
 
 static unsigned long
+insert_d23_align1 (unsigned long insn, long value, const char ** errmsg)
+{
+  if (value > 0x3fffff || value < -0x400000)
+    {
+      if (value & 0x1)
+	* errmsg = _(not_valid);
+      else
+	* errmsg = _(out_of_range);
+    }
+  else if (value & 0x1)
+    * errmsg = _(not_aligned);
+
+  return insn | ((value & 0x7e) << 4) | ((value & 0x7fff80) << (16 - 7));
+}
+
+static unsigned long
 extract_d23 (unsigned long insn, int * invalid)
 {
   signed long ret = ((insn >> 4) & 0x7f) | ((insn >> (16-7)) & 0x7fff80);
@@ -508,20 +528,436 @@ insert_r4 (unsigned long insn, long v, const char ** errmsg)
   unsigned long value = (unsigned long) v;
 
   if (value >= 32)
-    {
-      * errmsg = _("invalid register name");
-    }
+    * errmsg = _("invalid register name");
 
-  return insn | ((value & 0x10) << (23-4)) | ((value & 0x0f) << (17));
+  return insn | ((value & 0x01) << 23) | ((value & 0x1e) << 16);
 }
 
 static unsigned long
 extract_r4 (unsigned long insn, int * invalid)
 {
-  unsigned long ret = ((insn >> (23-4)) & 0x10) | ((insn >> 17) & 0x0f);
+  unsigned long r4;
+  unsigned long insn2;
+
+  insn2 = insn >> 16;
+  r4 = (((insn2 & 0x0080) >> 7) | (insn2 & 0x001e));
+
+  if (invalid != 0)
+    *invalid = 0;
+
+  return r4;
+}
+
+static unsigned long G_pos;
+
+static unsigned long
+insert_POS (unsigned long insn, long pos, const char ** errmsg)
+{
+  if (pos > 0x1f || pos < 0)
+    * errmsg = _(pos_out_of_range);
+
+  G_pos = (unsigned long) pos;
+
+  return insn; /* Not an oparaton until WIDTH.  */
+}
+
+static unsigned long
+extract_POS_U (unsigned long insn, int * invalid)
+{
+  unsigned long pos,lsb;
+  unsigned long insn2;
+  insn2 = insn >> 16;
+
+  lsb = ((insn2 & 0x0800) >>  8)
+      | ((insn2 & 0x000e) >>  1);
+  lsb += 16;
+  pos = lsb;
+
+  if (invalid != 0)
+    *invalid = 0;
+
+  return pos;
+}
+
+static unsigned long
+extract_POS_L (unsigned long insn, int * invalid)
+{
+  unsigned long pos,lsb;
+  unsigned long insn2;
+  insn2 = insn >> 16;
+
+  lsb = ((insn2 & 0x0800) >>  8)
+      | ((insn2 & 0x000e) >>  1);
+  pos = lsb;
+
+  if (invalid != 0)
+    *invalid = 0;
+
+  return pos;
+}
+
+static unsigned long
+insert_WIDTH (unsigned long insn, long width, const char ** errmsg)
+{
+  unsigned long msb, lsb, opc, ret;
+  unsigned long msb_expand, lsb_expand;
+
+  msb = (unsigned long)width + G_pos - 1;
+  lsb = G_pos;
+  opc = 0;
+  G_pos = 0;
+
+  if (width > 0x20 || width < 0)
+    * errmsg = _(width_out_of_range);
+
+  if ((msb >= 16) && (lsb >= 16))
+    opc = 0x0090;
+  else if ((msb >= 16) && (lsb < 16))
+    opc = 0x00b0;
+  else if ((msb < 16) && (lsb < 16))
+    opc = 0x00d0;
+  else
+    * errmsg = _(width_out_of_range);
+
+  msb &= 0x0f;
+  msb_expand = msb << 12;
+  lsb &= 0x0f;
+  lsb_expand = ((lsb & 0x8) << 8)|((lsb & 0x7) << 1);
+
+  ret = (insn & 0x0000ffff) | ((opc | msb_expand | lsb_expand) << 16);
+
+  return ret;
+}
+
+static unsigned long
+extract_WIDTH_U (unsigned long insn, int * invalid)
+{
+  unsigned long width, msb, lsb;
+  unsigned long insn2;
+  insn2 = insn >> 16;
+
+  msb = ((insn2 & 0xf000) >> 12);
+  msb += 16;
+  lsb = ((insn2 & 0x0800) >>  8)
+      | ((insn2 & 0x000e) >>  1);
+  lsb += 16;
+
+  if (invalid != 0)
+    *invalid = 0;
+
+  width = msb - lsb + 1;
+
+  return width;
+}
+
+static unsigned long
+extract_WIDTH_M (unsigned long insn, int * invalid)
+{
+  unsigned long width, msb, lsb;
+  unsigned long insn2;
+  insn2 = insn >> 16;
+
+  msb = ((insn2 & 0xf000) >> 12) ;
+  msb += 16;
+  lsb = ((insn2 & 0x0800) >>  8)
+      | ((insn2 & 0x000e) >>  1);
+
+  if (invalid != 0)
+    *invalid = 0;
+
+  width = msb - lsb + 1;
+
+  return width;
+}
+
+static unsigned long
+extract_WIDTH_L (unsigned long insn, int * invalid)
+{
+  unsigned long width, msb, lsb;
+  unsigned long insn2;
+  insn2 = insn >> 16;
+
+  msb = ((insn2 & 0xf000) >> 12) ;
+  lsb = ((insn2 & 0x0800) >>  8)
+      | ((insn2 & 0x000e) >>  1);
+
+  if (invalid != 0)
+    *invalid = 0;
+
+  width = msb - lsb + 1;
+
+  return width;
+}
+
+static unsigned long
+insert_SELID (unsigned long insn, long selid, const char ** errmsg)
+{
+  unsigned long ret;
+
+  if (selid > 0x1f || selid < 0)
+    * errmsg = _(selid_out_of_range);
+
+  ret = (insn | ((selid & 0x1f) << 27));
+
+  return ret;
+}
+
+static unsigned long
+extract_SELID (unsigned long insn, int * invalid)
+{
+  unsigned long selid;
+  unsigned long insn2;
+
+  insn2 = insn >> 16;
+
+  selid = ((insn2 & 0xf800) >> 11);
+
+  if (invalid != 0)
+    *invalid = 0;
+
+  return selid;
+}
+
+static unsigned long
+insert_VECTOR8 (unsigned long insn, long vector8, const char ** errmsg)
+{
+  unsigned long ret;
+  unsigned long VVV,vvvvv;
+
+  if (vector8 > 0xff || vector8 < 0)
+    * errmsg = _(vector8_out_of_range);
+
+  VVV   = (vector8 & 0xe0) >> 5;
+  vvvvv = (vector8 & 0x1f);
+
+  ret = (insn | (VVV << 27) | vvvvv);
+
+  return ret;
+}
+
+static unsigned long
+extract_VECTOR8 (unsigned long insn, int * invalid)
+{
+  unsigned long vector8;
+  unsigned long VVV,vvvvv;
+  unsigned long insn2;
+
+  insn2   = insn >> 16;
+  VVV     = ((insn2 & 0x3800) >> 11);
+  vvvvv   = (insn & 0x001f);
+  vector8 = VVV << 5 | vvvvv;
+
+  if (invalid != 0)
+    *invalid = 0;
+
+  return vector8;
+}
+
+static unsigned long
+insert_VECTOR5 (unsigned long insn, long vector5, const char ** errmsg)
+{
+  unsigned long ret;
+  unsigned long vvvvv;
+
+  if (vector5 > 0x1f || vector5 < 0)
+    * errmsg = _(vector5_out_of_range);
+
+  vvvvv = (vector5 & 0x1f);
+
+  ret = (insn | vvvvv);
+
+  return ret;
+}
+
+static unsigned long
+extract_VECTOR5 (unsigned long insn, int * invalid)
+{
+  unsigned long vector5;
+
+  vector5 = (insn & 0x001f);
+
+  if (invalid != 0)
+    *invalid = 0;
+
+  return vector5;
+}
+
+static unsigned long
+insert_CACHEOP (unsigned long insn, long cacheop, const char ** errmsg ATTRIBUTE_UNUSED)
+{
+  unsigned long ret;
+  unsigned long pp,PPPPP;
+
+  pp    = (cacheop & 0x60) >> 5;
+  PPPPP = (cacheop & 0x1f);
+
+  ret = insn | (pp << 11) | (PPPPP << 27);
+
+  return ret;
+}
+
+static unsigned long
+extract_CACHEOP (unsigned long insn, int * invalid)
+{
+  unsigned long ret;
+  unsigned long pp,PPPPP;
+  unsigned long insn2;
+
+  insn2 = insn >> 16;
+
+  PPPPP = ((insn2 & 0xf800) >> 11);
+  pp    = ((insn  & 0x1800) >> 11);
+
+  ret   = (pp << 5) | PPPPP;
+
+  if (invalid != 0)
+    *invalid = 0;
+
+  return ret;
+}
+
+static unsigned long
+insert_PREFOP (unsigned long insn, long prefop, const char ** errmsg ATTRIBUTE_UNUSED)
+{
+  unsigned long ret;
+  unsigned long PPPPP;
+
+  PPPPP = (prefop & 0x1f);
+
+  ret = insn | (PPPPP << 27);
+
+  return ret;
+}
+
+static unsigned long
+extract_PREFOP (unsigned long insn, int * invalid)
+{
+  unsigned long ret;
+  unsigned long PPPPP;
+  unsigned long insn2;
+
+  insn2 = insn >> 16;
+
+  PPPPP = (insn2 & 0xf800) >> 11;
+
+  ret   = PPPPP;
+
+  if (invalid != 0)
+    *invalid = 0;
+
+  return ret;
+}
+
+static unsigned long
+insert_IMM10U (unsigned long insn, long value, const char ** errmsg)
+{
+  unsigned long imm10, ret;
+  unsigned long iiiii,IIIII;
+
+  if (value > 0x3ff || value < 0)
+    * errmsg = _(imm10_out_of_range);
+
+  imm10 = ((unsigned long) value) & 0x3ff;
+  IIIII = (imm10 >> 5) & 0x1f;
+  iiiii =  imm10       & 0x1f;
+
+  ret = insn | IIIII << 27 | iiiii;
+
+  return ret;
+}
+
+static unsigned long
+extract_IMM10U (unsigned long insn, int * invalid)
+{
+  unsigned long ret;
+  unsigned long iiiii,IIIII;
+  unsigned long insn2;
+  insn2 = insn >> 16;
+
+  IIIII = ((insn2 & 0xf800) >> 11);
+  iiiii = (insn   & 0x001f);
+
+  ret = (IIIII << 5) | iiiii;
+
+  if (invalid != 0)
+    *invalid = 0;
+
+  return ret;
+}
+
+static unsigned long
+insert_SRSEL1 (unsigned long insn, long value, const char ** errmsg)
+{
+  unsigned long imm10, ret;
+  unsigned long sr,selid;
+
+  if (value > 0x3ff || value < 0)
+    * errmsg = _(sr_selid_out_of_range);
+
+  imm10 = (unsigned long) value;
+  selid = (imm10 & 0x3e0) >> 5;
+  sr    =  imm10 & 0x1f;
+
+  ret   = insn | selid << 27 | sr;
+
+  return ret;
+}
+
+static unsigned long
+extract_SRSEL1 (unsigned long insn, int * invalid)
+{
+  unsigned long ret;
+  unsigned long sr, selid;
+  unsigned long insn2;
+
+  insn2 = insn >> 16;
+
+  selid = ((insn2 & 0xf800) >> 11);
+  sr    = (insn  & 0x001f);
+
+  ret   = (selid << 5) | sr;
+
+  if (invalid != 0)
+    *invalid = 0;
+
+  return ret;
+}
+
+static unsigned long
+insert_SRSEL2 (unsigned long insn, long value, const char ** errmsg)
+{
+  unsigned long imm10, ret;
+  unsigned long sr, selid;
+
+  if (value > 0x3ff || value < 0)
+    * errmsg = _(sr_selid_out_of_range);
+
+  imm10 = (unsigned long) value;
+  selid = (imm10 & 0x3e0) >> 5;
+  sr    =  imm10 & 0x1f;
+
+  ret   = insn | selid << 27 | sr << 11;
+
+  return ret;
+}
+
+static unsigned long
+extract_SRSEL2 (unsigned long insn, int * invalid)
+{
+  unsigned long ret;
+  unsigned long sr, selid;
+  unsigned long insn2;
+
+  insn2 = insn >> 16;
+
+  selid = ((insn2 & 0xf800) >> 11);
+  sr    = ((insn  & 0xf800) >> 11);
+
+  ret   = (selid << 5) | sr;
 
   if (invalid != 0)
     *invalid = 0;
+
   return ret;
 }
 
@@ -606,13 +1042,19 @@ const struct v850_operand v850_operands[] =
   { -1, 0xffe00001, NULL, NULL, V850E_OPERAND_REG_LIST, BFD_RELOC_NONE },
 
 /* System register operands.  */
-#define SR1	(LIST12 + 1)
+#define OLDSR1	(LIST12 + 1)
   { 5, 0, NULL, NULL, V850_OPERAND_SRG, BFD_RELOC_NONE },
 
+#define SR1	(OLDSR1 + 1)
+  { 0, 0, insert_SRSEL1, extract_SRSEL1, V850_OPERAND_SRG, BFD_RELOC_NONE },
+
 /* The R2 field as a system register.  */
-#define SR2	(SR1 + 1)
+#define OLDSR2	(SR1 + 1)
   { 5, 11, NULL, NULL, V850_OPERAND_SRG, BFD_RELOC_NONE },
 
+#define SR2	(OLDSR2 + 1)
+  { 0, 0, insert_SRSEL2, extract_SRSEL2, V850_OPERAND_SRG, BFD_RELOC_NONE },
+
 /* FPU CC bit position.  */
 #define FFF (SR2 + 1)
   { 3, 17, NULL, NULL, 0, BFD_RELOC_NONE },
@@ -743,12 +1185,8 @@ const struct v850_operand v850_operands[] =
 #define I16	(D9_RELAX + 1)
   { 16, 16, NULL, NULL, V850_OPERAND_SIGNED, BFD_RELOC_16 },
 
-/* The 16 bit immediate following a 32 bit instruction.  */
-#define IMM16	(I16 + 1)
-  { 16, 32, NULL, NULL, V850E_IMMEDIATE16, BFD_RELOC_16 },
-
 /* The signed 16 bit immediate following a prepare instruction.  */
-#define IMM16LO	(IMM16 + 1)
+#define IMM16LO	(I16 + 1)
   { 16, 32, NULL, NULL, V850E_IMMEDIATE16 | V850_OPERAND_SIGNED, BFD_RELOC_LO16 },
 
 /* The hi 16 bit immediate following a 32 bit instruction.  */
@@ -773,7 +1211,7 @@ const struct v850_operand v850_operands[] =
 
 /* The unsigned DISP16 field in a format 7 insn.  */
 #define D16_LOOP	(D16_15 + 1)
-  { 16, 0, insert_u16_loop, extract_u16_loop, V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_16_PCREL },
+  { 16, 0, insert_u16_loop, extract_u16_loop, V850_OPERAND_RELAX | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_16_PCREL },
 
 /* The DISP17 field in a format 7 insn.  */
 #define D17_16	(D16_LOOP + 1)
@@ -788,8 +1226,11 @@ const struct v850_operand v850_operands[] =
 #define D23	(D22 + 1)
   { 23, 0, insert_d23, extract_d23, V850E_IMMEDIATE23 | V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_V850_23 },
 
+#define D23_ALIGN1	(D23 + 1)
+  { 23, 0, insert_d23_align1, extract_d23, V850E_IMMEDIATE23 | V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_V850_23 },
+
 /* The 32 bit immediate following a 32 bit instruction.  */
-#define IMM32	(D23 + 1)
+#define IMM32	(D23_ALIGN1 + 1)
   { 32, 32, NULL, NULL, V850E_IMMEDIATE32, BFD_RELOC_32 },
 
 #define D32_31	(IMM32 + 1)
@@ -798,6 +1239,53 @@ const struct v850_operand v850_operands[] =
 #define D32_31_PCREL	(D32_31 + 1)
   { 32, 32, NULL, NULL, V850E_IMMEDIATE32 | V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_32_PCREL },
 
+#define POS_U	(D32_31_PCREL + 1)
+  { 0, 0, insert_POS, extract_POS_U, 0, BFD_RELOC_NONE },
+
+#define POS_M	(POS_U + 1)
+  { 0, 0, insert_POS, extract_POS_L, 0, BFD_RELOC_NONE },
+
+#define POS_L	(POS_M + 1)
+  { 0, 0, insert_POS, extract_POS_L, 0, BFD_RELOC_NONE },
+
+#define WIDTH_U	(POS_L + 1)
+  { 0, 0, insert_WIDTH, extract_WIDTH_U, 0, BFD_RELOC_NONE },
+
+#define WIDTH_M	(WIDTH_U + 1)
+  { 0, 0, insert_WIDTH, extract_WIDTH_M, 0, BFD_RELOC_NONE },
+
+#define WIDTH_L	(WIDTH_M + 1)
+  { 0, 0, insert_WIDTH, extract_WIDTH_L, 0, BFD_RELOC_NONE },
+
+#define SELID	(WIDTH_L + 1)
+  { 5, 27, insert_SELID, extract_SELID, 0, BFD_RELOC_NONE },
+
+#define RIE_IMM5	(SELID + 1)
+  { 5, 11, NULL, NULL, 0, BFD_RELOC_NONE },
+
+#define RIE_IMM4	(RIE_IMM5 + 1)
+  { 4, 0, NULL, NULL, 0, BFD_RELOC_NONE },
+
+#define VECTOR8	(RIE_IMM4 + 1)
+  { 0, 0, insert_VECTOR8, extract_VECTOR8, 0, BFD_RELOC_NONE },
+
+#define VECTOR5	(VECTOR8 + 1)
+  { 0, 0, insert_VECTOR5, extract_VECTOR5, 0, BFD_RELOC_NONE },
+
+#define VR1	(VECTOR5 + 1)
+  { 5, 0, NULL, NULL, V850_OPERAND_VREG, BFD_RELOC_NONE },
+
+#define VR2	(VR1 + 1)
+  { 5, 11, NULL, NULL, V850_OPERAND_VREG, BFD_RELOC_NONE },
+
+#define CACHEOP	(VR2 + 1)
+  { 0, 0, insert_CACHEOP, extract_CACHEOP, V850_OPERAND_CACHEOP, BFD_RELOC_NONE },
+
+#define PREFOP	(CACHEOP + 1)
+  { 0, 0, insert_PREFOP, extract_PREFOP, V850_OPERAND_PREFOP, BFD_RELOC_NONE },
+
+#define IMM10U	(PREFOP + 1)
+  { 0, 0, insert_IMM10U, extract_IMM10U, 0, BFD_RELOC_NONE },
 };
 
 
@@ -858,7 +1346,7 @@ const struct v850_opcode v850_opcodes[] =
 
 { "addi",	OP  (0x30),		OP_MASK,		IF6, 			0, PROCESSOR_ALL },
 
-{ "adf",	two (0x07e0, 0x03a0),	two (0x07e0, 0x07e1),	{CCCC_NOTSA, R1, R2, R3},    	0, PROCESSOR_V850E2_ALL },
+{ "adf",	two (0x07e0, 0x03a0),	two (0x07e0, 0x07e1),	{CCCC_NOTSA, R1, R2, R3},    	0, PROCESSOR_V850E2_UP },
 
 { "and",	OP (0x0a),		OP_MASK,		IF1, 			0, PROCESSOR_ALL },
 
@@ -891,13 +1379,79 @@ const struct v850_opcode v850_opcodes[] =
 { "bv",		BOP (0x0),		BOP_MASK,		IF3, 			0, PROCESSOR_ALL },
 { "bz",		BOP (0x2),		BOP_MASK,		IF3, 			0, PROCESSOR_ALL },
 
+/* Signed integer.  */
+{ "bge",  two (0x07ee, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
+{ "bgt",  two (0x07ef, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
+{ "ble",  two (0x07e7, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
+{ "blt",  two (0x07e6, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
+/* Unsigned integer.  */			      	 
+{ "bh",   two (0x07eb, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
+{ "bl",   two (0x07e1, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
+{ "bnh",  two (0x07e3, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
+{ "bnl",  two (0x07e9, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
+/* Common.  */					      	 
+{ "be",   two (0x07e2, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
+{ "bne",  two (0x07ea, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
+/* Others.  */					      	 
+{ "bc",   two (0x07e1, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
+{ "bf",   two (0x07ea, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
+{ "bn",   two (0x07e4, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
+{ "bnc",  two (0x07e9, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
+{ "bnv",  two (0x07e8, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
+{ "bnz",  two (0x07ea, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
+{ "bp",   two (0x07ec, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
+{ "br",   two (0x07e5, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
+{ "bsa",  two (0x07ed, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
+{ "bt",   two (0x07e2, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
+{ "bv",   two (0x07e0, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
+{ "bz",   two (0x07e2, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
+/* Bcond disp17 Gas local alias(not defined in spec).  */
+
+/* Signed integer.  */
+{ "bge17",  two (0x07ee, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
+{ "bgt17",  two (0x07ef, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
+{ "ble17",  two (0x07e7, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
+{ "blt17",  two (0x07e6, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
+/* Unsigned integer.  */
+{ "bh17",   two (0x07eb, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
+{ "bl17",   two (0x07e1, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
+{ "bnh17",  two (0x07e3, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
+{ "bnl17",  two (0x07e9, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
+/* Common.  */
+{ "be17",   two (0x07e2, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
+{ "bne17",  two (0x07ea, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
+/* Others.  */
+{ "bc17",   two (0x07e1, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
+{ "bf17",   two (0x07ea, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
+{ "bn17",   two (0x07e4, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
+{ "bnc17",  two (0x07e9, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
+{ "bnv17",  two (0x07e8, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
+{ "bnz17",  two (0x07ea, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
+{ "bp17",   two (0x07ec, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
+{ "br17",   two (0x07e5, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
+{ "bsa17",  two (0x07ed, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
+{ "bt17",   two (0x07e2, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
+{ "bv17",   two (0x07e0, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
+{ "bz17",   two (0x07e2, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
+
 { "bsh",	two (0x07e0, 0x0342),	two (0x07ff, 0x07ff), 	{R2, R3}, 		0, PROCESSOR_NOT_V850 },
 
 { "bsw",	two (0x07e0, 0x0340),	two (0x07ff, 0x07ff), 	{R2, R3}, 		0, PROCESSOR_NOT_V850 },
 
+/* v850e3v5 bitfield instructions.  */
+{ "bins",	two (0x07e0, 0x0090),	two (0x07e0, 0x07f1), {R1, POS_U, WIDTH_U, R2}, 		0, PROCESSOR_V850E3V5_UP },
+{ "bins",	two (0x07e0, 0x00b0),	two (0x07e0, 0x07f1), {R1, POS_M, WIDTH_M, R2}, 		0, PROCESSOR_V850E3V5_UP },
+{ "bins",	two (0x07e0, 0x00d0),	two (0x07e0, 0x07f1), {R1, POS_L, WIDTH_L, R2}, 		0, PROCESSOR_V850E3V5_UP },
+/* Gas local alias(not defined in spec).  */
+{ "binsu",two (0x07e0, 0x0090),	two (0x07e0, 0x07f1), {R1, POS_U, WIDTH_U, R2},			0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
+{ "binsm",two (0x07e0, 0x00b0),	two (0x07e0, 0x07f1), {R1, POS_M, WIDTH_M, R2}, 		0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
+{ "binsl",two (0x07e0, 0x00d0),	two (0x07e0, 0x07f1), {R1, POS_L, WIDTH_L, R2}, 		0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
+
+{ "cache",	two (0xe7e0, 0x0160),	two (0xe7e0, 0x07ff),	{CACHEOP, R1}, 		2, PROCESSOR_V850E3V5_UP },
+
 { "callt",	one (0x0200),		one (0xffc0), 	      	{IMM6},			0, PROCESSOR_NOT_V850 },
 
-{ "caxi",	two (0x07e0, 0x00ee),	two (0x07e0, 0x07ff),	{R1, R2, R3},		1, PROCESSOR_V850E2_ALL },
+{ "caxi",	two (0x07e0, 0x00ee),	two (0x07e0, 0x07ff),	{R1, R2, R3},		1, PROCESSOR_V850E2_UP },
 
 { "clr1",	two (0x87c0, 0x0000),	two (0xc7e0, 0x0000),	{B3, D16, R1}, 		3, PROCESSOR_ALL },
 { "clr1",	two (0x07e0, 0x00e4),	two (0x07e0, 0xffff),   {R2, R1},    		3, PROCESSOR_NOT_V850 },
@@ -910,8 +1464,16 @@ const struct v850_opcode v850_opcodes[] =
 
 { "ctret", 	two (0x07e0, 0x0144),	two (0xffff, 0xffff), 	{0}, 			0, PROCESSOR_NOT_V850 },
 
+{ "dbcp",	one (0xe840),		one (0xffff),		{0},			0, PROCESSOR_V850E3V5_UP },
+
+{ "dbhvtrap",	one (0xe040),		one (0xffff),		{0},			0, PROCESSOR_V850E3V5_UP },
+
+{ "dbpush",	two (0x5fe0, 0x0160),	two (0xffe0, 0x07ff),	{R1, R3}, 		0, PROCESSOR_V850E3V5_UP },
+
 { "dbret",	two (0x07e0, 0x0146),	two (0xffff, 0xffff),	{0},			0, PROCESSOR_NOT_V850 },
 
+{ "dbtag",	two (0xcfe0, 0x0160),	two (0xffe0, 0x07ff),	{IMM10U},		0, PROCESSOR_V850E3V5_UP },
+
 { "dbtrap",	one (0xf840),		one (0xffff),		{0},			0, PROCESSOR_NOT_V850 },
 
 { "di",		two (0x07e0, 0x0160),	two (0xffff, 0xffff),	{0}, 			0, PROCESSOR_ALL },
@@ -931,50 +1493,61 @@ const struct v850_opcode v850_opcodes[] =
 { "divhun",	two (0x07e0, 0x0282),	two (0x07e0, 0x07c3), 	{I5DIV1, R1, R2, R3}, 	0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION },
 { "divn",	two (0x07e0, 0x02c0),	two (0x07e0, 0x07c3), 	{I5DIV2, R1, R2, R3}, 	0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION },
 
-{ "divq",	two (0x07e0, 0x02fc),   two (0x07e0, 0x07ff), 	{R1, R2, R3},		0, PROCESSOR_V850E2_ALL },
+{ "divq",	two (0x07e0, 0x02fc),   two (0x07e0, 0x07ff), 	{R1, R2, R3},		0, PROCESSOR_V850E2_UP },
 
-{ "divqu",	two (0x07e0, 0x02fe),   two (0x07e0, 0x07ff), 	{R1, R2, R3},		0, PROCESSOR_V850E2_ALL },
+{ "divqu",	two (0x07e0, 0x02fe),   two (0x07e0, 0x07ff), 	{R1, R2, R3},		0, PROCESSOR_V850E2_UP },
 
 { "divu",	two (0x07e0, 0x02c2),	two (0x07e0, 0x07ff), 	{R1, R2, R3}, 		0, PROCESSOR_NOT_V850 },
 
 { "divun",	two (0x07e0, 0x02c2),	two (0x07e0, 0x07c3), 	{I5DIV2, R1, R2, R3}, 	0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION },
 
+{ "dst",	two (0x07e0, 0x0134),	two (0xfffff, 0xffff),	{0}, 		0, PROCESSOR_V850E3V5_UP },
+
 { "ei",		two (0x87e0, 0x0160),	two (0xffff, 0xffff),	{0}, 			0, PROCESSOR_ALL },
 
-{ "eiret",	two (0x07e0, 0x0148),	two (0xffff, 0xffff),	{0},			0, PROCESSOR_V850E2_ALL },
+{ "eiret",	two (0x07e0, 0x0148),	two (0xffff, 0xffff),	{0},			0, PROCESSOR_V850E2_UP },
+
+{ "est",	two (0x07e0, 0x0132),	two (0xfffff, 0xffff),	{0}, 		0, PROCESSOR_V850E3V5_UP },
 
-{ "feret",	two (0x07e0, 0x014a),	two (0xffff, 0xffff),	{0},			0, PROCESSOR_V850E2_ALL },
+{ "feret",	two (0x07e0, 0x014a),	two (0xffff, 0xffff),	{0},			0, PROCESSOR_V850E2_UP },
 
-{ "fetrap",	one (0x0040),		one (0x87ff),		{I4U_NOTIMM0},		0, PROCESSOR_V850E2_ALL },
+{ "fetrap",	one (0x0040),		one (0x87ff),		{I4U_NOTIMM0},		0, PROCESSOR_V850E2_UP },
 
 { "halt",	two (0x07e0, 0x0120),	two (0xffff, 0xffff),	{0}, 			0, PROCESSOR_ALL },
 
-{ "hsh",	two (0x07e0, 0x0346),	two (0x07ff, 0x07ff), 	{R2, R3}, 		0, PROCESSOR_V850E2_ALL },
+{ "hsh",	two (0x07e0, 0x0346),	two (0x07ff, 0x07ff), 	{R2, R3}, 		0, PROCESSOR_V850E2_UP },
 
 { "hsw",	two (0x07e0, 0x0344),	two (0x07ff, 0x07ff), 	{R2, R3}, 		0, PROCESSOR_NOT_V850 },
 
+{ "hvcall",	two (0xd7e0, 0x4160),	two (0xffe0, 0x41ff),	{VECTOR8}, 		0, PROCESSOR_V850E3V5_UP },
+{ "hvtrap",	two (0x07e0, 0x0110),	two (0xffe0, 0xffff),	{VECTOR5}, 		0, PROCESSOR_V850E3V5_UP },
+  
+{ "jarl",	two (0xc7e0, 0x0160),	two (0xffe0, 0x07ff),	{R1, R3_NOTR0},   	1, PROCESSOR_V850E3V5_UP},
 { "jarl",	two (0x0780, 0x0000),	two (0x07c0, 0x0001),	{D22, R2_NOTR0}, 	0, PROCESSOR_ALL},
-{ "jarl",	one (0x02e0),		one (0xffe0),		{D32_31_PCREL, R1_NOTR0}, 	0, PROCESSOR_V850E2_ALL },
-/* Gas local alias of mov imm22(not defined in spec).  */
+{ "jarl",	one (0x02e0),		one (0xffe0),		{D32_31_PCREL, R1_NOTR0}, 	0, PROCESSOR_V850E2_UP },
+/* Gas local alias (not defined in spec).  */
+{ "jarlr", two (0xc7e0, 0x0160),	two (0xffe0, 0x07ff),	{R1, R3_NOTR0}, 1, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS},
+/* Gas local alias of jarl imm22 (not defined in spec).  */
 { "jarl22",	two (0x0780, 0x0000),	two (0x07c0, 0x0001),	{D22, R2_NOTR0}, 	0, PROCESSOR_ALL | PROCESSOR_OPTION_ALIAS},
-/* Gas local alias of mov imm32(not defined in spec).  */
-{ "jarl32",	one (0x02e0),		one (0xffe0),		{D32_31_PCREL, R1_NOTR0}, 	0, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_ALIAS },
-{ "jarlw",	one (0x02e0),		one (0xffe0),		{D32_31_PCREL, R1_NOTR0}, 	0, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_ALIAS },
+/* Gas local alias of jarl imm32 (not defined in spec).  */
+{ "jarl32",	one (0x02e0),		one (0xffe0),		{D32_31_PCREL, R1_NOTR0}, 	0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS },
+{ "jarlw",	one (0x02e0),		one (0xffe0),		{D32_31_PCREL, R1_NOTR0}, 	0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS },
 
-{ "jmp",	one (0x06e0),		one (0xffe0),		{D32_31, R1}, 		2, PROCESSOR_V850E2_ALL },
+{ "jmp",	two (0x06e0, 0x0000),	two (0xffe0, 0x0001),	{D32_31, R1}, 		2, PROCESSOR_V850E3V5_UP },
+{ "jmp",	one (0x06e0),		one (0xffe0),		{D32_31, R1}, 		2, PROCESSOR_V850E2 | PROCESSOR_V850E2V3 },
 { "jmp",	one (0x0060),		one (0xffe0),	      	{R1}, 			1, PROCESSOR_ALL },
 /* Gas local alias of jmp disp22(not defined in spec).  */
 { "jmp22",	one (0x0060),		one (0xffe0),	      	{R1}, 			1, PROCESSOR_ALL | PROCESSOR_OPTION_ALIAS },
 /* Gas local alias of jmp disp32(not defined in spec).  */
-{ "jmp32",	one (0x06e0),		one (0xffe0),		{D32_31, R1}, 		2, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_ALIAS },
-{ "jmpw",	one (0x06e0),		one (0xffe0),		{D32_31, R1}, 		2, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_ALIAS },
+{ "jmp32",	one (0x06e0),		one (0xffe0),		{D32_31, R1}, 		2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS },
+{ "jmpw",	one (0x06e0),		one (0xffe0),		{D32_31, R1}, 		2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS },
 
 { "jr",		two (0x0780, 0x0000),	two (0xffc0, 0x0001),	{D22}, 			0, PROCESSOR_ALL },
-{ "jr",		one (0x02e0),		one (0xffff),		{D32_31_PCREL},		0, PROCESSOR_V850E2_ALL },
+{ "jr",		one (0x02e0),		one (0xffff),		{D32_31_PCREL},		0, PROCESSOR_V850E2_UP },
 /* Gas local alias of mov imm22(not defined in spec).  */
 { "jr22",	two (0x0780, 0x0000),	two (0xffc0, 0x0001),	{D22}, 			0, PROCESSOR_ALL | PROCESSOR_OPTION_ALIAS },
 /* Gas local alias of mov imm32(not defined in spec).  */
-{ "jr32",	one (0x02e0),		one (0xffff),		{D32_31_PCREL},		0, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_ALIAS },
+{ "jr32",	one (0x02e0),		one (0xffff),		{D32_31_PCREL},		0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS },
 
 /* Alias of bcond (same as CA850).  */
 { "jgt",	BOP (0xf),		BOP_MASK,		IF3, 			0, PROCESSOR_ALL },
@@ -1001,38 +1574,56 @@ const struct v850_opcode v850_opcodes[] =
 { "jbr",	BOP (0x5),		BOP_MASK,		IF3, 			0, PROCESSOR_ALL },
 
 
-{ "ldacc",	two (0x07e0, 0x0bc4),	two (0x07e0, 0xffff),	{R1, R2},		0, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_EXTENSION },
+{ "ldacc",	two (0x07e0, 0x0bc4),	two (0x07e0, 0xffff),	{R1, R2},		0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_EXTENSION },
 
 { "ld.b",	two (0x0700, 0x0000),	two (0x07e0, 0x0000), 	{D16, R1, R2}, 		2, PROCESSOR_ALL },
-{ "ld.b",	two (0x0780, 0x0005),	two (0x07e0, 0x000f), 	{D23, R1, R3}, 		2, PROCESSOR_V850E2_ALL },
-{ "ld.b23",	two (0x0780, 0x0005),	two (0x07e0, 0x000f), 	{D23, R1, R3}, 		2, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_ALIAS },
+{ "ld.b",	two (0x0780, 0x0005),	two (0x07e0, 0x000f), 	{D23, R1, R3}, 		2, PROCESSOR_V850E2_UP },
+{ "ld.b23",	two (0x0780, 0x0005),	two (0x07e0, 0x000f), 	{D23, R1, R3}, 		2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS },
 
 { "ld.bu",	two (0x0780, 0x0001),   two (0x07c0, 0x0001), 	{D16_16, R1, R2_NOTR0},	2, PROCESSOR_NOT_V850 },
-{ "ld.bu",	two (0x07a0, 0x0005),	two (0x07e0, 0x000f), 	{D23, R1, R3}, 		2, PROCESSOR_V850E2_ALL },
-{ "ld.bu23",	two (0x07a0, 0x0005),	two (0x07e0, 0x000f), 	{D23, R1, R3}, 		2, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_ALIAS },
+{ "ld.bu",	two (0x07a0, 0x0005),	two (0x07e0, 0x000f), 	{D23, R1, R3}, 		2, PROCESSOR_V850E2_UP },
+{ "ld.bu23",	two (0x07a0, 0x0005),	two (0x07e0, 0x000f), 	{D23, R1, R3}, 		2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS },
+
+{ "ld.dw",   	two (0x07a0, 0x0009), 	two (0xffe0, 0x001f), {D23_ALIGN1, R1, R3_EVEN}, 2, PROCESSOR_V850E3V5_UP },
+{ "ld.dw23", 	two (0x07a0, 0x0009), 	two (0xffe0, 0x001f), {D23_ALIGN1, R1, R3_EVEN}, 2, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
 
 { "ld.h",	two (0x0720, 0x0000),	two (0x07e0, 0x0001), 	{D16_15, R1, R2}, 	2, PROCESSOR_ALL },
-{ "ld.h",	two (0x0780, 0x0007),	two (0x07e0, 0x000f), 	{D23, R1, R3}, 		2, PROCESSOR_V850E2_ALL },
-{ "ld.h23",	two (0x0780, 0x0007),	two (0x07e0, 0x000f), 	{D23, R1, R3}, 		2, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_ALIAS },
+{ "ld.h",	two (0x0780, 0x0007),	two (0x07e0, 0x000f), 	{D23_ALIGN1, R1, R3}, 	2, PROCESSOR_V850E2_UP },
+{ "ld.h23",	two (0x0780, 0x0007),	two (0x07e0, 0x000f), 	{D23_ALIGN1, R1, R3}, 	2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS },
 
 { "ld.hu",	two (0x07e0, 0x0001),   two (0x07e0, 0x0001), 	{D16_15, R1, R2_NOTR0},	2, PROCESSOR_NOT_V850 },
-{ "ld.hu",	two (0x07a0, 0x0007),	two (0x07e0, 0x000f), 	{D23, R1, R3}, 		2, PROCESSOR_V850E2_ALL },
-{ "ld.hu23",	two (0x07a0, 0x0007),	two (0x07e0, 0x000f), 	{D23, R1, R3}, 		2, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_ALIAS },
-
+{ "ld.hu",	two (0x07a0, 0x0007),	two (0x07e0, 0x000f), 	{D23_ALIGN1, R1, R3}, 	2, PROCESSOR_V850E2_UP },
+{ "ld.hu23",	two (0x07a0, 0x0007),	two (0x07e0, 0x000f), 	{D23_ALIGN1, R1, R3}, 	2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS },
 
 { "ld.w",	two (0x0720, 0x0001),	two (0x07e0, 0x0001), 	{D16_15, R1, R2}, 	2, PROCESSOR_ALL },
-{ "ld.w",	two (0x0780, 0x0009),	two (0x07e0, 0x000f), 	{D23, R1, R3}, 		2, PROCESSOR_V850E2_ALL },
-{ "ld.w23",	two (0x0780, 0x0009),	two (0x07e0, 0x000f), 	{D23, R1, R3}, 		2, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_ALIAS },
+{ "ld.w",	two (0x0780, 0x0009),	two (0xffe0, 0x001f), 	{D23_ALIGN1, R1, R3}, 	2, PROCESSOR_V850E2_UP },
+{ "ld.w23",	two (0x0780, 0x0009),	two (0x07e0, 0x001f), 	{D23_ALIGN1, R1, R3}, 	2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS },
 
-{ "ldsr",	two (0x07e0, 0x0020),	two (0x07e0, 0xffff),	{R1, SR2}, 		0, PROCESSOR_ALL },
+{ "ldl.w",	two (0x07e0, 0x0378),	two (0xffe0, 0x07ff),	{R1, R3}, 		1, PROCESSOR_V850E3V5_UP },
 
-{ "macacc",	two (0x07e0, 0x0bc0),	two (0x07e0, 0xffff),	{R1, R2},		0, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_EXTENSION },
+{ "ldsr",	two (0x07e0, 0x0020),	two (0x07e0, 0x07ff),	{R1, SR2, SELID}, 	0, PROCESSOR_V850E3V5_UP },
+{ "ldsr",	two (0x07e0, 0x0020),	two (0x07e0, 0x07ff),	{R1, SR2}, 		0, PROCESSOR_V850E3V5_UP },
+{ "ldsr",	two (0x07e0, 0x0020),	two (0x07e0, 0x07ff),	{R1, OLDSR2}, 		0, (PROCESSOR_ALL & (~ PROCESSOR_V850E3V5_UP)) },
 
-{ "mac",	two (0x07e0, 0x03c0),	two (0x07e0, 0x0fe1),	{R1, R2, R3_EVEN, R4_EVEN},    	0, PROCESSOR_V850E2_ALL },
+{ "ldtc.gr",	two (0x07e0, 0x0032),	two (0x07e0, 0xffff),	{R1, R2}, 		0, PROCESSOR_V850E3V5_UP },
+{ "ldtc.sr",	two (0x07e0, 0x0030),	two (0x07e0, 0x07ff),	{R1, SR2, SELID}, 	0, PROCESSOR_V850E3V5_UP },
+{ "ldtc.sr",	two (0x07e0, 0x0030),	two (0x07e0, 0x07ff),	{R1, SR2},	 	0, PROCESSOR_V850E3V5_UP },
 
-{ "macu",	two (0x07e0, 0x03e0),	two (0x07e0, 0x0fe1),	{R1, R2, R3_EVEN, R4_EVEN},  	0, PROCESSOR_V850E2_ALL },
+{ "ldtc.vr",	two (0x07e0, 0x0832),	two (0x07e0, 0xffff),	{R1, VR2}, 		0, PROCESSOR_V850E3V5_UP },
+{ "ldtc.pc",	two (0x07e0, 0xf832),	two (0x07e0, 0xffff),	{R1}, 			0, PROCESSOR_V850E3V5_UP },
 
-{ "macuacc",	two (0x07e0, 0x0bc2),	two (0x07e0, 0xffff),	{R1, R2},		0, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_EXTENSION },
+{ "ldvc.sr",	two (0x07e0, 0x0034),	two (0x07e0, 0x07ff),	{R1, SR2, SELID}, 	0, PROCESSOR_V850E3V5_UP },
+{ "ldvc.sr",	two (0x07e0, 0x0034),	two (0x07e0, 0x07ff),	{R1, SR2},	 	0, PROCESSOR_V850E3V5_UP },
+
+{ "loop",	two (0x06e0, 0x0001),	two (0xffe0, 0x0001), 	{R1, D16_LOOP}, 	0, PROCESSOR_V850E3V5_UP },
+
+{ "macacc",	two (0x07e0, 0x0bc0),	two (0x07e0, 0xffff),	{R1, R2},		0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_EXTENSION },
+
+{ "mac",	two (0x07e0, 0x03c0),	two (0x07e0, 0x0fe1),	{R1, R2, R3_EVEN, R4_EVEN},    	0, PROCESSOR_V850E2_UP },
+
+{ "macu",	two (0x07e0, 0x03e0),	two (0x07e0, 0x0fe1),	{R1, R2, R3_EVEN, R4_EVEN},  	0, PROCESSOR_V850E2_UP },
+
+{ "macuacc",	two (0x07e0, 0x0bc2),	two (0x07e0, 0xffff),	{R1, R2},		0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_EXTENSION },
 
 { "mov",        OP  (0x00),		OP_MASK,		{R1, R2_NOTR0},		0, PROCESSOR_ALL },
 { "mov",	OP  (0x10),		OP_MASK,		{I5, R2_NOTR0},		0, PROCESSOR_ALL },
@@ -1066,40 +1657,49 @@ const struct v850_opcode v850_opcodes[] =
 
 { "ori",	OP (0x34),		OP_MASK,		IF6U, 			0, PROCESSOR_ALL },
 
+{ "popsp",	two (0x67e0, 0x0160),	two (0xffe0, 0x07ff),	{R1, R3}, 		0, PROCESSOR_V850E3V5_UP },
+
+{ "pref",	two (0xdfe0, 0x0160),	two (0xffe0, 0x07ff),	{PREFOP, R1}, 		2, PROCESSOR_V850E3V5_UP },
+
 { "prepare",    two (0x0780, 0x0003),	two (0xffc0, 0x001f), 	{LIST12, IMM5, SP}, 	0, PROCESSOR_NOT_V850 },
 { "prepare",    two (0x0780, 0x000b),	two (0xffc0, 0x001f), 	{LIST12, IMM5, IMM16LO},0, PROCESSOR_NOT_V850 },
 { "prepare",    two (0x0780, 0x0013),	two (0xffc0, 0x001f), 	{LIST12, IMM5, IMM16HI},0, PROCESSOR_NOT_V850 },
 { "prepare",    two (0x0780, 0x001b),	two (0xffc0, 0x001f), 	{LIST12, IMM5, IMM32}, 	0, PROCESSOR_NOT_V850 },
 { "prepare",    two (0x0780, 0x0001),	two (0xffc0, 0x001f), 	{LIST12, IMM5}, 	0, PROCESSOR_NOT_V850 },
 
+{ "pushsp",	two (0x47e0, 0x0160),	two (0xffe0, 0x07ff),	{R1, R3}, 		0, PROCESSOR_V850E3V5_UP },
+
+{ "rotl",	two (0x07e0, 0x00c6),	two (0x07e0, 0x07ff), 	{R1, R2, R3}, 		0, PROCESSOR_V850E3V5_UP },
+{ "rotl",	two (0x07e0, 0x00c4),	two (0x07e0, 0x07ff), 	{I5U, R2, R3}, 		0, PROCESSOR_V850E3V5_UP },
+
 { "reti",	two (0x07e0, 0x0140),	two (0xffff, 0xffff),	{0}, 			0, PROCESSOR_ALL },
 
-{ "sar",	two (0x07e0, 0x00a2),	two (0x07e0, 0x07ff), 	{R1, R2, R3}, 		0, PROCESSOR_V850E2_ALL },
+{ "sar",	two (0x07e0, 0x00a2),	two (0x07e0, 0x07ff), 	{R1, R2, R3}, 		0, PROCESSOR_V850E2_UP },
 { "sar",	OP (0x15),		OP_MASK,		{I5U, R2}, 		0, PROCESSOR_ALL },
 { "sar",	two (0x07e0, 0x00a0),	two (0x07e0, 0xffff), 	{R1,  R2}, 		0, PROCESSOR_ALL },
 
 { "sasf",       two (0x07e0, 0x0200),	two (0x07f0, 0xffff), 	{CCCC, R2}, 		0, PROCESSOR_NOT_V850 },
 
-{ "satadd",	two (0x07e0, 0x03ba),	two (0x07e0, 0x07ff), 	{R1, R2, R3},		0, PROCESSOR_V850E2_ALL },
+{ "satadd",	two (0x07e0, 0x03ba),	two (0x07e0, 0x07ff), 	{R1, R2, R3},		0, PROCESSOR_V850E2_UP },
 { "satadd",	OP (0x11),		OP_MASK,		{I5, R2_NOTR0},		0, PROCESSOR_ALL },
 { "satadd",	OP (0x06),		OP_MASK,		{R1, R2_NOTR0},		0, PROCESSOR_ALL },
 
-{ "satsub",	two (0x07e0, 0x039a),	two (0x07e0, 0x07ff), 	{R1, R2, R3},		0, PROCESSOR_V850E2_ALL },
+{ "satsub",	two (0x07e0, 0x039a),	two (0x07e0, 0x07ff), 	{R1, R2, R3},		0, PROCESSOR_V850E2_UP },
 { "satsub",	OP (0x05),		OP_MASK,		{R1, R2_NOTR0},		0, PROCESSOR_ALL },
 
 { "satsubi",	OP (0x33),		OP_MASK,		{I16, R1, R2_NOTR0},	0, PROCESSOR_ALL },
 
 { "satsubr",	OP (0x04),		OP_MASK,		{R1, R2_NOTR0},		0, PROCESSOR_ALL },
 
-{ "sbf",	two (0x07e0, 0x0380),	two (0x07e0, 0x07e1),	{CCCC_NOTSA, R1, R2, R3},    	0, PROCESSOR_V850E2_ALL },
+{ "sbf",	two (0x07e0, 0x0380),	two (0x07e0, 0x07e1),	{CCCC_NOTSA, R1, R2, R3},    	0, PROCESSOR_V850E2_UP },
 
-{ "sch0l",	two (0x07e0, 0x0364),	two (0x07ff, 0x07ff), 	{R2, R3}, 		0, PROCESSOR_V850E2_ALL },
+{ "sch0l",	two (0x07e0, 0x0364),	two (0x07ff, 0x07ff), 	{R2, R3}, 		0, PROCESSOR_V850E2_UP },
 
-{ "sch0r",	two (0x07e0, 0x0360),	two (0x07ff, 0x07ff), 	{R2, R3}, 		0, PROCESSOR_V850E2_ALL },
+{ "sch0r",	two (0x07e0, 0x0360),	two (0x07ff, 0x07ff), 	{R2, R3}, 		0, PROCESSOR_V850E2_UP },
 
-{ "sch1l",	two (0x07e0, 0x0366),	two (0x07ff, 0x07ff), 	{R2, R3}, 		0, PROCESSOR_V850E2_ALL },
+{ "sch1l",	two (0x07e0, 0x0366),	two (0x07ff, 0x07ff), 	{R2, R3}, 		0, PROCESSOR_V850E2_UP },
 
-{ "sch1r",	two (0x07e0, 0x0362),	two (0x07ff, 0x07ff), 	{R2, R3}, 		0, PROCESSOR_V850E2_ALL },
+{ "sch1r",	two (0x07e0, 0x0362),	two (0x07ff, 0x07ff), 	{R2, R3}, 		0, PROCESSOR_V850E2_UP },
 
 { "sdivhn",	two (0x07e0, 0x0180),	two (0x07e0, 0x07c3), 	{I5DIV3, R1, R2, R3}, 	0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION },
 { "sdivhun",	two (0x07e0, 0x0182),	two (0x07e0, 0x07c3), 	{I5DIV3, R1, R2, R3}, 	0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION },
@@ -1111,11 +1711,11 @@ const struct v850_opcode v850_opcodes[] =
 
 { "setf",	two (0x07e0, 0x0000),	two (0x07f0, 0xffff), 	{CCCC, R2}, 		0, PROCESSOR_ALL },
 
-{ "shl",	two (0x07e0, 0x00c2),	two (0x07e0, 0x07ff), 	{R1, R2, R3}, 		0, PROCESSOR_V850E2_ALL },
+{ "shl",	two (0x07e0, 0x00c2),	two (0x07e0, 0x07ff), 	{R1, R2, R3}, 		0, PROCESSOR_V850E2_UP },
 { "shl",	OP  (0x16),		OP_MASK,	      	{I5U, R2}, 		0, PROCESSOR_ALL },
 { "shl",	two (0x07e0, 0x00c0),	two (0x07e0, 0xffff), 	{R1,  R2}, 		0, PROCESSOR_ALL },
 
-{ "shr",	two (0x07e0, 0x0082),	two (0x07e0, 0x07ff), 	{R1, R2, R3}, 		0, PROCESSOR_V850E2_ALL },
+{ "shr",	two (0x07e0, 0x0082),	two (0x07e0, 0x07ff), 	{R1, R2, R3}, 		0, PROCESSOR_V850E2_UP },
 { "shr",	OP  (0x14),		OP_MASK,	      	{I5U, R2}, 		0, PROCESSOR_ALL },
 { "shr",	two (0x07e0, 0x0080),	two (0x07e0, 0xffff), 	{R1,  R2}, 		0, PROCESSOR_ALL },
 
@@ -1129,28 +1729,46 @@ const struct v850_opcode v850_opcodes[] =
 
 { "sld.w",	one (0x0500),		one (0x0781),	      	{D8_6U,EP,   R2}, 	2, PROCESSOR_ALL },
 
+{ "snooze",	two (0x0fe0, 0x0120),	two (0xffff, 0xffff),	{0},	 		0, PROCESSOR_V850E3V5_UP },
+
 { "sst.b",	one (0x0380),		one (0x0780),	      	{R2,   D7U,  EP}, 	3, PROCESSOR_ALL },
 
 { "sst.h",	one (0x0480),		one (0x0780),	      	{R2,   D8_7U,EP}, 	3, PROCESSOR_ALL },
 
 { "sst.w",	one (0x0501),		one (0x0781),	      	{R2,   D8_6U,EP}, 	3, PROCESSOR_ALL },
 
-{ "stacch",	two (0x07e0, 0x0bca),	two (0x07ff, 0xffff),	{R2},			0, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_EXTENSION },
-{ "staccl",	two (0x07e0, 0x0bc8),	two (0x07ff, 0xffff),	{R2},			0, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_EXTENSION },
+{ "stacch",	two (0x07e0, 0x0bca),	two (0x07ff, 0xffff),	{R2},			0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_EXTENSION },
+{ "staccl",	two (0x07e0, 0x0bc8),	two (0x07ff, 0xffff),	{R2},			0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_EXTENSION },
 
 { "st.b",	two (0x0740, 0x0000),	two (0x07e0, 0x0000), 	{R2, D16, R1}, 		3, PROCESSOR_ALL },
-{ "st.b",	two (0x0780, 0x000d),	two (0x07e0, 0x000f), 	{R3, D23, R1}, 		3, PROCESSOR_V850E2_ALL },
-{ "st.b23",	two (0x0780, 0x000d),	two (0x07e0, 0x000f), 	{R3, D23, R1}, 		3, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_ALIAS },
+{ "st.b",	two (0x0780, 0x000d),	two (0x07e0, 0x000f), 	{R3, D23, R1}, 		3, PROCESSOR_V850E2_UP },
+{ "st.b23",	two (0x0780, 0x000d),	two (0x07e0, 0x000f), 	{R3, D23, R1}, 		3, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS },
+
+{ "st.dw",   	two (0x07a0, 0x000f), 	two (0xffe0, 0x001f), {R3_EVEN, D23_ALIGN1, R1}, 3, PROCESSOR_V850E3V5_UP },
+{ "st.dw23", 	two (0x07a0, 0x000f), 	two (0xffe0, 0x001f), {R3_EVEN, D23_ALIGN1, R1}, 3, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
 
 { "st.h",	two (0x0760, 0x0000),	two (0x07e0, 0x0001), 	{R2, D16_15, R1}, 	3, PROCESSOR_ALL },
-{ "st.h",	two (0x07a0, 0x000d),	two (0x07e0, 0x000f), 	{R3, D23, R1}, 		3, PROCESSOR_V850E2_ALL },
-{ "st.h23",	two (0x07a0, 0x000d),	two (0x07e0, 0x000f), 	{R3, D23, R1}, 		3, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_ALIAS },
+{ "st.h",	two (0x07a0, 0x000d),	two (0x07e0, 0x000f), 	{R3, D23_ALIGN1, R1}, 	3, PROCESSOR_V850E2_UP },
+{ "st.h23",	two (0x07a0, 0x000d),	two (0x07e0, 0x000f), 	{R3, D23_ALIGN1, R1}, 	3, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS },
 
 { "st.w",	two (0x0760, 0x0001),	two (0x07e0, 0x0001), 	{R2, D16_15, R1}, 	3, PROCESSOR_ALL },
-{ "st.w",	two (0x0780, 0x000f),	two (0x07e0, 0x000f), 	{R3, D23, R1}, 		3, PROCESSOR_V850E2_ALL },
-{ "st.w23",	two (0x0780, 0x000f),	two (0x07e0, 0x000f), 	{R3, D23, R1}, 		3, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_ALIAS },
+{ "st.w",	two (0x0780, 0x000f),	two (0x07e0, 0x000f), 	{R3, D23_ALIGN1, R1}, 	3, PROCESSOR_V850E2_UP },
+{ "st.w23",	two (0x0780, 0x000f),	two (0x07e0, 0x000f), 	{R3, D23_ALIGN1, R1}, 	3, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS },
+
+{ "stc.w",	two (0x07e0, 0x037a),	two (0xffe0, 0x07ff),	{R3, R1},		2, PROCESSOR_V850E3V5_UP },
+
+{ "stsr",	two (0x07e0, 0x0040),	two (0x07e0, 0x07ff),	{SR1, R2, SELID}, 	0, PROCESSOR_V850E3V5_UP },
+{ "stsr",	two (0x07e0, 0x0040),	two (0x07e0, 0x07ff),	{SR1, R2}, 		0, PROCESSOR_V850E3V5_UP },
+{ "stsr",	two (0x07e0, 0x0040),	two (0x07e0, 0x07ff),	{OLDSR1, R2}, 		0, (PROCESSOR_ALL & (~ PROCESSOR_V850E3V5_UP)) },
+
+{ "sttc.gr",	two (0x07e0, 0x0052),	two (0x07e0, 0xffff),	{R1, R2}, 		0, PROCESSOR_V850E3V5_UP },
+{ "sttc.sr",	two (0x07e0, 0x0050),	two (0x07e0, 0x07ff),	{SR1, R2, SELID}, 	0, PROCESSOR_V850E3V5_UP },
+{ "sttc.sr",	two (0x07e0, 0x0050),	two (0x07e0, 0x07ff),	{SR1, R2},	 	0, PROCESSOR_V850E3V5_UP },
+{ "sttc.vr",	two (0x07e0, 0x0852),	two (0x07e0, 0xffff),	{VR1, R2}, 		0, PROCESSOR_V850E3V5_UP },
+{ "sttc.pc",	two (0x07e0, 0xf852),	two (0x07e0, 0xffff),	{R2}, 			0, PROCESSOR_V850E3V5_UP },
 
-{ "stsr",	two (0x07e0, 0x0040),	two (0x07e0, 0xffff),	{SR1, R2}, 		0, PROCESSOR_ALL },
+{ "stvc.sr",	two (0x07e0, 0x0054),	two (0x07e0, 0x07ff),	{SR1, R2, SELID}, 	0, PROCESSOR_V850E3V5_UP },
+{ "stvc.sr",	two (0x07e0, 0x0054),	two (0x07e0, 0x07ff),	{SR1, R2},	 	0, PROCESSOR_V850E3V5_UP },
 
 { "sub",	OP  (0x0d),		OP_MASK,		IF1, 			0, PROCESSOR_ALL },
 
@@ -1162,6 +1780,12 @@ const struct v850_opcode v850_opcodes[] =
 
 { "sxh",	one (0x00e0),		one (0xffe0),	      	{R1},			0, PROCESSOR_NOT_V850 },
 
+{ "tlbai",	two (0x87e0, 0x8960),	two (0xffff, 0xffff),	{0},	 		0, PROCESSOR_V850E3V5_UP },
+{ "tlbr",	two (0x87e0, 0xe960),	two (0xffff, 0xffff),	{0},	 		0, PROCESSOR_V850E3V5_UP },
+{ "tlbs",	two (0x87e0, 0xc160),	two (0xffff, 0xffff),	{0},	 		0, PROCESSOR_V850E3V5_UP },
+{ "tlbvi",	two (0x87e0, 0x8160),	two (0xffff, 0xffff),	{0},	 		0, PROCESSOR_V850E3V5_UP },
+{ "tlbw",	two (0x87e0, 0xe160),	two (0xffff, 0xffff),	{0},	 		0, PROCESSOR_V850E3V5_UP },
+
 { "trap",	two (0x07e0, 0x0100),	two (0xffe0, 0xffff),	{I5U}, 			0, PROCESSOR_ALL },
 
 { "tst",	OP (0x0b),		OP_MASK,		IF1, 			0, PROCESSOR_ALL },
@@ -1178,113 +1802,112 @@ const struct v850_opcode v850_opcodes[] =
 { "zxh",	one (0x00c0),		one (0xffe0), 	      	{R1},			0, PROCESSOR_NOT_V850 },
 
 /* Floating point operation.  */
-{ "absf.d",	two (0x07e0, 0x0458),	two (0x0fff, 0x0fff),	{R2_EVEN, R3_EVEN},			0, PROCESSOR_V850E2V3 },
-{ "absf.s",	two (0x07e0, 0x0448),	two (0x07ff, 0x07ff),	{R2, R3},				0, PROCESSOR_V850E2V3 },
-{ "addf.d",	two (0x07e0, 0x0470),	two (0x0fe1, 0x0fff),	{R1_EVEN, R2_EVEN, R3_EVEN},		0, PROCESSOR_V850E2V3 },
-{ "addf.s",	two (0x07e0, 0x0460),	two (0x07e0, 0x07ff),	{R1, R2, R3},				0, PROCESSOR_V850E2V3 },
-{ "ceilf.dl",	two (0x07e2, 0x0454),	two (0x0fff, 0x0fff),	{R2_EVEN, R3_EVEN},			0, PROCESSOR_V850E2V3 },
-{ "ceilf.dul",	two (0x07f2, 0x0454),	two (0x0fff, 0x0fff),	{R2_EVEN, R3_EVEN},			0, PROCESSOR_V850E2V3 },
-{ "ceilf.duw",	two (0x07f2, 0x0450),	two (0x0fff, 0x07ff),	{R2_EVEN, R3},				0, PROCESSOR_V850E2V3 },
-{ "ceilf.dw",	two (0x07e2, 0x0450),	two (0x0fff, 0x07ff),	{R2_EVEN, R3},				0, PROCESSOR_V850E2V3 },
-{ "ceilf.sl",	two (0x07e2, 0x0444),	two (0x07ff, 0x0fff),	{R2, R3_EVEN},				0, PROCESSOR_V850E2V3 },
-{ "ceilf.sul",	two (0x07f2, 0x0444),	two (0x07ff, 0x0fff),	{R2, R3_EVEN},				0, PROCESSOR_V850E2V3 },
-{ "ceilf.suw",	two (0x07f2, 0x0440),	two (0x07ff, 0x07ff),	{R2, R3},				0, PROCESSOR_V850E2V3 },
-{ "ceilf.sw",	two (0x07e2, 0x0440),	two (0x07ff, 0x07ff),	{R2, R3},				0, PROCESSOR_V850E2V3 },
-{ "ceilf.sw",	two (0x07e2, 0x0440),	two (0x07ff, 0x07ff),	{R2, R3},				0, PROCESSOR_V850E2V3 },
-{ "cmovf.d",	two (0x07e0, 0x0410),	two (0x0fe1, 0x0ff1),	{FFF, R1_EVEN, R2_EVEN, R3_EVEN_NOTR0},	0, PROCESSOR_V850E2V3 },
+{ "absf.d",	two (0x07e0, 0x0458),	two (0x0fff, 0x0fff),	{R2_EVEN, R3_EVEN},			0, PROCESSOR_V850E2V3_UP },
+{ "absf.s",	two (0x07e0, 0x0448),	two (0x07ff, 0x07ff),	{R2, R3},				0, PROCESSOR_V850E2V3_UP },
+{ "addf.d",	two (0x07e0, 0x0470),	two (0x0fe1, 0x0fff),	{R1_EVEN, R2_EVEN, R3_EVEN},		0, PROCESSOR_V850E2V3_UP },
+{ "addf.s",	two (0x07e0, 0x0460),	two (0x07e0, 0x07ff),	{R1, R2, R3},				0, PROCESSOR_V850E2V3_UP },
+{ "ceilf.dl",	two (0x07e2, 0x0454),	two (0x0fff, 0x0fff),	{R2_EVEN, R3_EVEN},			0, PROCESSOR_V850E2V3_UP },
+{ "ceilf.dul",	two (0x07f2, 0x0454),	two (0x0fff, 0x0fff),	{R2_EVEN, R3_EVEN},			0, PROCESSOR_V850E2V3_UP },
+{ "ceilf.duw",	two (0x07f2, 0x0450),	two (0x0fff, 0x07ff),	{R2_EVEN, R3},				0, PROCESSOR_V850E2V3_UP },
+{ "ceilf.dw",	two (0x07e2, 0x0450),	two (0x0fff, 0x07ff),	{R2_EVEN, R3},				0, PROCESSOR_V850E2V3_UP },
+{ "ceilf.sl",	two (0x07e2, 0x0444),	two (0x07ff, 0x0fff),	{R2, R3_EVEN},				0, PROCESSOR_V850E2V3_UP },
+{ "ceilf.sul",	two (0x07f2, 0x0444),	two (0x07ff, 0x0fff),	{R2, R3_EVEN},				0, PROCESSOR_V850E2V3_UP },
+{ "ceilf.suw",	two (0x07f2, 0x0440),	two (0x07ff, 0x07ff),	{R2, R3},				0, PROCESSOR_V850E2V3_UP },
+{ "ceilf.sw",	two (0x07e2, 0x0440),	two (0x07ff, 0x07ff),	{R2, R3},				0, PROCESSOR_V850E2V3_UP },
+{ "ceilf.sw",	two (0x07e2, 0x0440),	two (0x07ff, 0x07ff),	{R2, R3},				0, PROCESSOR_V850E2V3_UP },
+{ "cmovf.d",	two (0x07e0, 0x0410),	two (0x0fe1, 0x0ff1),	{FFF, R1_EVEN, R2_EVEN, R3_EVEN_NOTR0},	0, PROCESSOR_V850E2V3_UP },
 /* Default value for FFF is 0(not defined in spec).  */
-{ "cmovf.d",	two (0x07e0, 0x0410),	two (0x0fe1, 0x0fff),	{R1_EVEN, R2_EVEN, R3_EVEN_NOTR0},	0, PROCESSOR_V850E2V3 },
-{ "cmovf.s",	two (0x07e0, 0x0400),	two (0x07e0, 0x07f1),	{FFF, R1, R2, R3_NOTR0},		0, PROCESSOR_V850E2V3 },
+{ "cmovf.d",	two (0x07e0, 0x0410),	two (0x0fe1, 0x0fff),	{R1_EVEN, R2_EVEN, R3_EVEN_NOTR0},	0, PROCESSOR_V850E2V3_UP },
+{ "cmovf.s",	two (0x07e0, 0x0400),	two (0x07e0, 0x07f1),	{FFF, R1, R2, R3_NOTR0},		0, PROCESSOR_V850E2V3_UP },
 /* Default value for FFF is 0(not defined in spec).  */
-{ "cmovf.s",	two (0x07e0, 0x0400),	two (0x07e0, 0x07ff),	{R1, R2, R3_NOTR0},			0, PROCESSOR_V850E2V3 },
-{ "cmpf.d",	two (0x07e0, 0x0430),	two (0x0fe1, 0x87f1),	{FLOAT_CCCC, R2_EVEN, R1_EVEN, FFF},	0, PROCESSOR_V850E2V3 },
-{ "cmpf.d",	two (0x07e0, 0x0430),	two (0x0fe1, 0x87ff),	{FLOAT_CCCC, R2_EVEN, R1_EVEN},		0, PROCESSOR_V850E2V3 },
-{ "cmpf.s",	two (0x07e0, 0x0420),	two (0x07e0, 0x87f1),	{FLOAT_CCCC, R2, R1, FFF},		0, PROCESSOR_V850E2V3 },
-{ "cmpf.s",	two (0x07e0, 0x0420),	two (0x07e0, 0x87ff),	{FLOAT_CCCC, R2, R1},			0, PROCESSOR_V850E2V3 },
-{ "cvtf.dl",	two (0x07e4, 0x0454),	two (0x0fff, 0x0fff),	{R2_EVEN, R3_EVEN},			0, PROCESSOR_V850E2V3 },
-{ "cvtf.ds",	two (0x07e3, 0x0452),	two (0x0fff, 0x07ff),	{R2_EVEN, R3},				0, PROCESSOR_V850E2V3 },
-{ "cvtf.dul",	two (0x07f4, 0x0454),	two (0x0fff, 0x0fff),	{R2_EVEN, R3_EVEN},			0, PROCESSOR_V850E2V3 },
-{ "cvtf.duw",	two (0x07f4, 0x0450),	two (0x0fff, 0x07ff),	{R2_EVEN, R3},				0, PROCESSOR_V850E2V3 },
-{ "cvtf.dw",	two (0x07e4, 0x0450),	two (0x0fff, 0x07ff),	{R2_EVEN, R3},				0, PROCESSOR_V850E2V3 },
-{ "cvtf.ld",	two (0x07e1, 0x0452),	two (0x0fff, 0x0fff),	{R2_EVEN, R3_EVEN},			0, PROCESSOR_V850E2V3 },
-{ "cvtf.ls",	two (0x07e1, 0x0442),	two (0x0fff, 0x07ff),	{R2_EVEN, R3},				0, PROCESSOR_V850E2V3 },
-{ "cvtf.sd",	two (0x07e2, 0x0452),	two (0x07ff, 0x0fff),	{R2, R3_EVEN},				0, PROCESSOR_V850E2V3 },
-{ "cvtf.sl",	two (0x07e4, 0x0444),	two (0x07ff, 0x0fff),	{R2, R3_EVEN},				0, PROCESSOR_V850E2V3 },
-{ "cvtf.sul",	two (0x07f4, 0x0444),	two (0x07ff, 0x0fff),	{R2, R3_EVEN},				0, PROCESSOR_V850E2V3 },
-{ "cvtf.suw",	two (0x07f4, 0x0440),	two (0x07ff, 0x07ff),	{R2, R3},				0, PROCESSOR_V850E2V3 },
-{ "cvtf.sw",	two (0x07e4, 0x0440),	two (0x07ff, 0x07ff),	{R2, R3},				0, PROCESSOR_V850E2V3 },
-{ "cvtf.uld",	two (0x07f1, 0x0452),	two (0x0fff, 0x0fff),	{R2_EVEN, R3_EVEN},			0, PROCESSOR_V850E2V3 },
-{ "cvtf.uls",	two (0x07f1, 0x0442),	two (0x0fff, 0x07ff),	{R2_EVEN, R3},				0, PROCESSOR_V850E2V3 },
-{ "cvtf.uwd",	two (0x07f0, 0x0452),	two (0x07ff, 0x0fff),	{R2, R3_EVEN},				0, PROCESSOR_V850E2V3 },
-{ "cvtf.uws",	two (0x07f0, 0x0442),	two (0x07ff, 0x07ff),	{R2, R3},				0, PROCESSOR_V850E2V3 },
-{ "cvtf.wd",	two (0x07e0, 0x0452),	two (0x07ff, 0x0fff),	{R2, R3_EVEN},				0, PROCESSOR_V850E2V3 },
-{ "cvtf.ws",	two (0x07e0, 0x0442),	two (0x07ff, 0x07ff),	{R2, R3},				0, PROCESSOR_V850E2V3 },
-{ "divf.d",	two (0x07e0, 0x047e),	two (0x0fe1, 0x0fff),	{R1_EVEN, R2_EVEN, R3_EVEN},		0, PROCESSOR_V850E2V3 },
-{ "divf.s",	two (0x07e0, 0x046e),	two (0x07e0, 0x07ff),	{R1_NOTR0, R2, R3},			0, PROCESSOR_V850E2V3 },
-{ "floorf.dl",	two (0x07e3, 0x0454),	two (0x0fff, 0x0fff),	{R2_EVEN, R3_EVEN},			0, PROCESSOR_V850E2V3 },
-{ "floorf.dul",	two (0x07f3, 0x0454),	two (0x0fff, 0x0fff),	{R2_EVEN, R3_EVEN},			0, PROCESSOR_V850E2V3 },
-{ "floorf.duw",	two (0x07f3, 0x0450),	two (0x0fff, 0x07ff),	{R2_EVEN, R3},				0, PROCESSOR_V850E2V3 },
-{ "floorf.dw",	two (0x07e3, 0x0450),	two (0x0fff, 0x07ff),	{R2_EVEN, R3},				0, PROCESSOR_V850E2V3 },
-{ "floorf.sl",	two (0x07e3, 0x0444),	two (0x07ff, 0x0fff),	{R2, R3_EVEN},				0, PROCESSOR_V850E2V3 },
-{ "floorf.sul",	two (0x07f3, 0x0444),	two (0x07ff, 0x0fff),	{R2, R3_EVEN},				0, PROCESSOR_V850E2V3 },
-{ "floorf.suw",	two (0x07f3, 0x0440),	two (0x07ff, 0x07ff),	{R2, R3},				0, PROCESSOR_V850E2V3 },
-{ "floorf.sw",	two (0x07e3, 0x0440),	two (0x07ff, 0x07ff),	{R2, R3},				0, PROCESSOR_V850E2V3 },
-{ "maddf.s",	two (0x07e0, 0x0500),	two (0x07e0, 0x0761),	{R1, R2, R3, R4},			0, PROCESSOR_V850E2V3 },
-{ "maxf.d",	two (0x07e0, 0x0478),	two (0x0fe1, 0x0fff),	{R1_EVEN, R2_EVEN, R3_EVEN},		0, PROCESSOR_V850E2V3 },
-{ "maxf.s",	two (0x07e0, 0x0468),	two (0x07e0, 0x07ff),	{R1, R2, R3},				0, PROCESSOR_V850E2V3 },
-{ "minf.d",	two (0x07e0, 0x047a),	two (0x0fe1, 0x0fff),	{R1_EVEN, R2_EVEN, R3_EVEN},		0, PROCESSOR_V850E2V3 },
-{ "minf.s",	two (0x07e0, 0x046a),	two (0x07e0, 0x07ff),	{R1, R2, R3},				0, PROCESSOR_V850E2V3 },
-{ "msubf.s",	two (0x07e0, 0x0520),	two (0x07e0, 0x0761),	{R1, R2, R3, R4},			0, PROCESSOR_V850E2V3 },
-{ "mulf.d",	two (0x07e0, 0x0474),	two (0x0fe1, 0x0fff),	{R1_EVEN, R2_EVEN, R3_EVEN},		0, PROCESSOR_V850E2V3 },
-{ "mulf.s",	two (0x07e0, 0x0464),	two (0x07e0, 0x07ff),	{R1, R2, R3},				0, PROCESSOR_V850E2V3 },
-{ "negf.d",	two (0x07e1, 0x0458),	two (0x0fff, 0x0fff),	{R2_EVEN, R3_EVEN},			0, PROCESSOR_V850E2V3 },
-{ "negf.s",	two (0x07e1, 0x0448),	two (0x07ff, 0x07ff),	{R2, R3},				0, PROCESSOR_V850E2V3 },
-{ "nmaddf.s",	two (0x07e0, 0x0540),	two (0x07e0, 0x0761),	{R1, R2, R3, R4},			0, PROCESSOR_V850E2V3 },
-{ "nmsubf.s",	two (0x07e0, 0x0560),	two (0x07e0, 0x0761),	{R1, R2, R3, R4},			0, PROCESSOR_V850E2V3 },
-{ "recipf.d",	two (0x07e1, 0x045e),	two (0x0fff, 0x0fff),	{R2_EVEN, R3_EVEN},			0, PROCESSOR_V850E2V3 },
-{ "recipf.s",	two (0x07e1, 0x044e),	two (0x07ff, 0x07ff),	{R2, R3},				0, PROCESSOR_V850E2V3 },
-
-{ "roundf.dl",	two (0x07e0, 0x0454),   two (0x0fff, 0x0fff),	{R2_EVEN, R3_EVEN},			0, PROCESSOR_V850E2V3 | PROCESSOR_OPTION_EXTENSION },
-{ "roundf.dul",	two (0x07f0, 0x0454),   two (0x0fff, 0x0fff),	{R2_EVEN, R3_EVEN},			0, PROCESSOR_V850E2V3 | PROCESSOR_OPTION_EXTENSION },
-{ "roundf.duw",	two (0x07f0, 0x0450),   two (0x0fff, 0x07ff),	{R2_EVEN, R3},				0, PROCESSOR_V850E2V3 | PROCESSOR_OPTION_EXTENSION },
-{ "roundf.dw",	two (0x07e0, 0x0450),   two (0x0fff, 0x07ff),	{R2_EVEN, R3},				0, PROCESSOR_V850E2V3 | PROCESSOR_OPTION_EXTENSION },
-{ "roundf.sl",	two (0x07e0, 0x0444),   two (0x07ff, 0x0fff),	{R2, R3_EVEN},				0, PROCESSOR_V850E2V3 | PROCESSOR_OPTION_EXTENSION },
-{ "roundf.sul",	two (0x07f0, 0x0444),   two (0x07ff, 0x0fff),	{R2, R3_EVEN},				0, PROCESSOR_V850E2V3 | PROCESSOR_OPTION_EXTENSION },
-{ "roundf.suw",	two (0x07f0, 0x0440),	two (0x07ff, 0x07ff),	{R2, R3},				0, PROCESSOR_V850E2V3 | PROCESSOR_OPTION_EXTENSION },
-{ "roundf.sw",	two (0x07e0, 0x0440),	two (0x07ff, 0x07ff),	{R2, R3},				0, PROCESSOR_V850E2V3 | PROCESSOR_OPTION_EXTENSION },
-
-{ "rsqrtf.d",	two (0x07e2, 0x045e),	two (0x0fff, 0x0fff),	{R2_EVEN, R3_EVEN},			0, PROCESSOR_V850E2V3 },
-{ "rsqrtf.s",	two (0x07e2, 0x044e),	two (0x07ff, 0x07ff),	{R2, R3},				0, PROCESSOR_V850E2V3 },
-{ "sqrtf.d",	two (0x07e0, 0x045e),	two (0x0fff, 0x0fff),	{R2_EVEN, R3_EVEN},			0, PROCESSOR_V850E2V3 },
-{ "sqrtf.s",	two (0x07e0, 0x044e),	two (0x07ff, 0x07ff),	{R2, R3},				0, PROCESSOR_V850E2V3 },
-{ "subf.d",	two (0x07e0, 0x0472),	two (0x0fe1, 0x0fff),	{R1_EVEN, R2_EVEN, R3_EVEN},		0, PROCESSOR_V850E2V3 },
-{ "subf.s",	two (0x07e0, 0x0462),	two (0x07e0, 0x07ff),	{R1, R2, R3},				0, PROCESSOR_V850E2V3 },
-{ "trfsr",	two (0x07e0, 0x0400),	two (0xffff, 0xfff1),	{FFF},					0, PROCESSOR_V850E2V3 },
-{ "trfsr",	two (0x07e0, 0x0400),	two (0xffff, 0xffff),	{0},					0, PROCESSOR_V850E2V3 },
-{ "trncf.dl",	two (0x07e1, 0x0454),	two (0x0fff, 0x0fff),	{R2_EVEN, R3_EVEN},			0, PROCESSOR_V850E2V3 },
-{ "trncf.dul",	two (0x07f1, 0x0454),	two (0x0fff, 0x0fff),	{R2_EVEN, R3_EVEN},			0, PROCESSOR_V850E2V3 },
-{ "trncf.duw",	two (0x07f1, 0x0450),	two (0x0fff, 0x07ff),	{R2_EVEN, R3},				0, PROCESSOR_V850E2V3 },
-{ "trncf.dw",	two (0x07e1, 0x0450),	two (0x0fff, 0x07ff),	{R2_EVEN, R3},				0, PROCESSOR_V850E2V3 },
-{ "trncf.sl",	two (0x07e1, 0x0444),	two (0x07ff, 0x0fff),	{R2, R3_EVEN},				0, PROCESSOR_V850E2V3 },
-{ "trncf.sul",	two (0x07f1, 0x0444),	two (0x07ff, 0x07ff),	{R2, R3},			0, PROCESSOR_V850E2V3 },
-{ "trncf.suw",	two (0x07f1, 0x0440),	two (0x07ff, 0x07ff),	{R2, R3},				0, PROCESSOR_V850E2V3 },
-{ "trncf.sw",	two (0x07e1, 0x0440),	two (0x07ff, 0x07ff),	{R2, R3},				0, PROCESSOR_V850E2V3 },
+{ "cmovf.s",	two (0x07e0, 0x0400),	two (0x07e0, 0x07ff),	{R1, R2, R3_NOTR0},			0, PROCESSOR_V850E2V3_UP },
+{ "cmpf.d",	two (0x07e0, 0x0430),	two (0x0fe1, 0x87f1),	{FLOAT_CCCC, R2_EVEN, R1_EVEN, FFF},	0, PROCESSOR_V850E2V3_UP },
+{ "cmpf.d",	two (0x07e0, 0x0430),	two (0x0fe1, 0x87ff),	{FLOAT_CCCC, R2_EVEN, R1_EVEN},		0, PROCESSOR_V850E2V3_UP },
+{ "cmpf.s",	two (0x07e0, 0x0420),	two (0x07e0, 0x87f1),	{FLOAT_CCCC, R2, R1, FFF},		0, PROCESSOR_V850E2V3_UP },
+{ "cmpf.s",	two (0x07e0, 0x0420),	two (0x07e0, 0x87ff),	{FLOAT_CCCC, R2, R1},			0, PROCESSOR_V850E2V3_UP },
+{ "cvtf.dl",	two (0x07e4, 0x0454),	two (0x0fff, 0x0fff),	{R2_EVEN, R3_EVEN},			0, PROCESSOR_V850E2V3_UP },
+{ "cvtf.ds",	two (0x07e3, 0x0452),	two (0x0fff, 0x07ff),	{R2_EVEN, R3},				0, PROCESSOR_V850E2V3_UP },
+{ "cvtf.dul",	two (0x07f4, 0x0454),	two (0x0fff, 0x0fff),	{R2_EVEN, R3_EVEN},			0, PROCESSOR_V850E2V3_UP },
+{ "cvtf.duw",	two (0x07f4, 0x0450),	two (0x0fff, 0x07ff),	{R2_EVEN, R3},				0, PROCESSOR_V850E2V3_UP },
+{ "cvtf.dw",	two (0x07e4, 0x0450),	two (0x0fff, 0x07ff),	{R2_EVEN, R3},				0, PROCESSOR_V850E2V3_UP },
+{ "cvtf.ld",	two (0x07e1, 0x0452),	two (0x0fff, 0x0fff),	{R2_EVEN, R3_EVEN},			0, PROCESSOR_V850E2V3_UP },
+{ "cvtf.ls",	two (0x07e1, 0x0442),	two (0x0fff, 0x07ff),	{R2_EVEN, R3},				0, PROCESSOR_V850E2V3_UP },
+{ "cvtf.sd",	two (0x07e2, 0x0452),	two (0x07ff, 0x0fff),	{R2, R3_EVEN},				0, PROCESSOR_V850E2V3_UP },
+{ "cvtf.sl",	two (0x07e4, 0x0444),	two (0x07ff, 0x0fff),	{R2, R3_EVEN},				0, PROCESSOR_V850E2V3_UP },
+{ "cvtf.sul",	two (0x07f4, 0x0444),	two (0x07ff, 0x0fff),	{R2, R3_EVEN},				0, PROCESSOR_V850E2V3_UP },
+{ "cvtf.suw",	two (0x07f4, 0x0440),	two (0x07ff, 0x07ff),	{R2, R3},				0, PROCESSOR_V850E2V3_UP },
+{ "cvtf.sw",	two (0x07e4, 0x0440),	two (0x07ff, 0x07ff),	{R2, R3},				0, PROCESSOR_V850E2V3_UP },
+{ "cvtf.uld",	two (0x07f1, 0x0452),	two (0x0fff, 0x0fff),	{R2_EVEN, R3_EVEN},			0, PROCESSOR_V850E2V3_UP },
+{ "cvtf.uls",	two (0x07f1, 0x0442),	two (0x0fff, 0x07ff),	{R2_EVEN, R3},				0, PROCESSOR_V850E2V3_UP },
+{ "cvtf.uwd",	two (0x07f0, 0x0452),	two (0x07ff, 0x0fff),	{R2, R3_EVEN},				0, PROCESSOR_V850E2V3_UP },
+{ "cvtf.uws",	two (0x07f0, 0x0442),	two (0x07ff, 0x07ff),	{R2, R3},				0, PROCESSOR_V850E2V3_UP },
+{ "cvtf.wd",	two (0x07e0, 0x0452),	two (0x07ff, 0x0fff),	{R2, R3_EVEN},				0, PROCESSOR_V850E2V3_UP },
+{ "cvtf.ws",	two (0x07e0, 0x0442),	two (0x07ff, 0x07ff),	{R2, R3},				0, PROCESSOR_V850E2V3_UP },
+{ "divf.d",	two (0x07e0, 0x047e),	two (0x0fe1, 0x0fff),	{R1_EVEN, R2_EVEN, R3_EVEN},		0, PROCESSOR_V850E2V3_UP },
+{ "divf.s",	two (0x07e0, 0x046e),	two (0x07e0, 0x07ff),	{R1_NOTR0, R2, R3},			0, PROCESSOR_V850E2V3_UP },
+{ "floorf.dl",	two (0x07e3, 0x0454),	two (0x0fff, 0x0fff),	{R2_EVEN, R3_EVEN},			0, PROCESSOR_V850E2V3_UP },
+{ "floorf.dul",	two (0x07f3, 0x0454),	two (0x0fff, 0x0fff),	{R2_EVEN, R3_EVEN},			0, PROCESSOR_V850E2V3_UP },
+{ "floorf.duw",	two (0x07f3, 0x0450),	two (0x0fff, 0x07ff),	{R2_EVEN, R3},				0, PROCESSOR_V850E2V3_UP },
+{ "floorf.dw",	two (0x07e3, 0x0450),	two (0x0fff, 0x07ff),	{R2_EVEN, R3},				0, PROCESSOR_V850E2V3_UP },
+{ "floorf.sl",	two (0x07e3, 0x0444),	two (0x07ff, 0x0fff),	{R2, R3_EVEN},				0, PROCESSOR_V850E2V3_UP },
+{ "floorf.sul",	two (0x07f3, 0x0444),	two (0x07ff, 0x0fff),	{R2, R3_EVEN},				0, PROCESSOR_V850E2V3_UP },
+{ "floorf.suw",	two (0x07f3, 0x0440),	two (0x07ff, 0x07ff),	{R2, R3},				0, PROCESSOR_V850E2V3_UP },
+{ "floorf.sw",	two (0x07e3, 0x0440),	two (0x07ff, 0x07ff),	{R2, R3},				0, PROCESSOR_V850E2V3_UP },
+{ "maddf.s",	two (0x07e0, 0x0500),	two (0x07e0, 0x0761),	{R1, R2, R3, R4},			0, PROCESSOR_V850E2V3_UP },
+{ "maxf.d",	two (0x07e0, 0x0478),	two (0x0fe1, 0x0fff),	{R1_EVEN, R2_EVEN, R3_EVEN},		0, PROCESSOR_V850E2V3_UP },
+{ "maxf.s",	two (0x07e0, 0x0468),	two (0x07e0, 0x07ff),	{R1, R2, R3},				0, PROCESSOR_V850E2V3_UP },
+{ "minf.d",	two (0x07e0, 0x047a),	two (0x0fe1, 0x0fff),	{R1_EVEN, R2_EVEN, R3_EVEN},		0, PROCESSOR_V850E2V3_UP },
+{ "minf.s",	two (0x07e0, 0x046a),	two (0x07e0, 0x07ff),	{R1, R2, R3},				0, PROCESSOR_V850E2V3_UP },
+{ "msubf.s",	two (0x07e0, 0x0520),	two (0x07e0, 0x0761),	{R1, R2, R3, R4},			0, PROCESSOR_V850E2V3_UP },
+{ "mulf.d",	two (0x07e0, 0x0474),	two (0x0fe1, 0x0fff),	{R1_EVEN, R2_EVEN, R3_EVEN},		0, PROCESSOR_V850E2V3_UP },
+{ "mulf.s",	two (0x07e0, 0x0464),	two (0x07e0, 0x07ff),	{R1, R2, R3},				0, PROCESSOR_V850E2V3_UP },
+{ "negf.d",	two (0x07e1, 0x0458),	two (0x0fff, 0x0fff),	{R2_EVEN, R3_EVEN},			0, PROCESSOR_V850E2V3_UP },
+{ "negf.s",	two (0x07e1, 0x0448),	two (0x07ff, 0x07ff),	{R2, R3},				0, PROCESSOR_V850E2V3_UP },
+{ "nmaddf.s",	two (0x07e0, 0x0540),	two (0x07e0, 0x0761),	{R1, R2, R3, R4},			0, PROCESSOR_V850E2V3_UP },
+{ "nmsubf.s",	two (0x07e0, 0x0560),	two (0x07e0, 0x0761),	{R1, R2, R3, R4},			0, PROCESSOR_V850E2V3_UP },
+{ "recipf.d",	two (0x07e1, 0x045e),	two (0x0fff, 0x0fff),	{R2_EVEN, R3_EVEN},			0, PROCESSOR_V850E2V3_UP },
+{ "recipf.s",	two (0x07e1, 0x044e),	two (0x07ff, 0x07ff),	{R2, R3},				0, PROCESSOR_V850E2V3_UP },
+
+{ "roundf.dl",	two (0x07e0, 0x0454),   two (0x0fff, 0x0fff),	{R2_EVEN, R3_EVEN},			0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION },
+{ "roundf.dul",	two (0x07f0, 0x0454),   two (0x0fff, 0x0fff),	{R2_EVEN, R3_EVEN},			0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION },
+{ "roundf.duw",	two (0x07f0, 0x0450),   two (0x0fff, 0x07ff),	{R2_EVEN, R3},				0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION },
+{ "roundf.dw",	two (0x07e0, 0x0450),   two (0x0fff, 0x07ff),	{R2_EVEN, R3},				0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION },
+{ "roundf.sl",	two (0x07e0, 0x0444),   two (0x07ff, 0x0fff),	{R2, R3_EVEN},				0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION },
+{ "roundf.sul",	two (0x07f0, 0x0444),   two (0x07ff, 0x0fff),	{R2, R3_EVEN},				0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION },
+{ "roundf.suw",	two (0x07f0, 0x0440),	two (0x07ff, 0x07ff),	{R2, R3},				0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION },
+{ "roundf.sw",	two (0x07e0, 0x0440),	two (0x07ff, 0x07ff),	{R2, R3},				0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION },
+
+{ "rsqrtf.d",	two (0x07e2, 0x045e),	two (0x0fff, 0x0fff),	{R2_EVEN, R3_EVEN},			0, PROCESSOR_V850E2V3_UP },
+{ "rsqrtf.s",	two (0x07e2, 0x044e),	two (0x07ff, 0x07ff),	{R2, R3},				0, PROCESSOR_V850E2V3_UP },
+{ "sqrtf.d",	two (0x07e0, 0x045e),	two (0x0fff, 0x0fff),	{R2_EVEN, R3_EVEN},			0, PROCESSOR_V850E2V3_UP },
+{ "sqrtf.s",	two (0x07e0, 0x044e),	two (0x07ff, 0x07ff),	{R2, R3},				0, PROCESSOR_V850E2V3_UP },
+{ "subf.d",	two (0x07e0, 0x0472),	two (0x0fe1, 0x0fff),	{R1_EVEN, R2_EVEN, R3_EVEN},		0, PROCESSOR_V850E2V3_UP },
+{ "subf.s",	two (0x07e0, 0x0462),	two (0x07e0, 0x07ff),	{R1, R2, R3},				0, PROCESSOR_V850E2V3_UP },
+{ "trfsr",	two (0x07e0, 0x0400),	two (0xffff, 0xfff1),	{FFF},					0, PROCESSOR_V850E2V3_UP },
+{ "trfsr",	two (0x07e0, 0x0400),	two (0xffff, 0xffff),	{0},					0, PROCESSOR_V850E2V3_UP },
+{ "trncf.dl",	two (0x07e1, 0x0454),	two (0x0fff, 0x0fff),	{R2_EVEN, R3_EVEN},			0, PROCESSOR_V850E2V3_UP },
+{ "trncf.dul",	two (0x07f1, 0x0454),	two (0x0fff, 0x0fff),	{R2_EVEN, R3_EVEN},			0, PROCESSOR_V850E2V3_UP },
+{ "trncf.duw",	two (0x07f1, 0x0450),	two (0x0fff, 0x07ff),	{R2_EVEN, R3},				0, PROCESSOR_V850E2V3_UP },
+{ "trncf.dw",	two (0x07e1, 0x0450),	two (0x0fff, 0x07ff),	{R2_EVEN, R3},				0, PROCESSOR_V850E2V3_UP },
+{ "trncf.sl",	two (0x07e1, 0x0444),	two (0x07ff, 0x0fff),	{R2, R3_EVEN},				0, PROCESSOR_V850E2V3_UP },
+{ "trncf.sul",	two (0x07f1, 0x0444),	two (0x07ff, 0x07ff),	{R2, R3},				0, PROCESSOR_V850E2V3_UP },
+{ "trncf.suw",	two (0x07f1, 0x0440),	two (0x07ff, 0x07ff),	{R2, R3},				0, PROCESSOR_V850E2V3_UP },
+{ "trncf.sw",	two (0x07e1, 0x0440),	two (0x07ff, 0x07ff),	{R2, R3},				0, PROCESSOR_V850E2V3_UP },
 
   /* Special instruction (from gdb) mov 1, r0.  */
 { "breakpoint",	one (0x0001),		one (0xffff),		{UNUSED},				0, PROCESSOR_ALL },
 
-  /* V850e2-v3.  */
-{ "synce",	one (0x001d),		one (0xffff),		{0},					0, PROCESSOR_V850E2V3 },
-{ "syncm",	one (0x001e),		one (0xffff),		{0},					0, PROCESSOR_V850E2V3 },
-{ "syncp",	one (0x001f),		one (0xffff),		{0},					0, PROCESSOR_V850E2V3 },
-{ "syscall",	two (0xd7e0, 0x0160),	two (0xffe0, 0xc7ff),	{V8},					0, PROCESSOR_V850E2V3 },
-  /* Alias of syncp.  */
-{ "sync",	one (0x001f),		one (0xffff),		{0},					0, PROCESSOR_V850E2V3 | PROCESSOR_OPTION_ALIAS },
-{ "rmtrap",	one (0xf040),		one (0xffff),		{0},					0, PROCESSOR_V850E2V3 },
-
+{ "synci",	one (0x001c),		one (0xffff),		{0},					0, PROCESSOR_V850E3V5_UP },
 
-{ "rie",	one (0x0040),		one (0xffff),		{0},					0, PROCESSOR_V850E2V3 },
-{ "rie",	two (0x07f0, 0x0000),	two (0x07f0, 0xffff),	{0},					0, PROCESSOR_V850E2V3 },
+{ "synce",	one (0x001d),		one (0xffff),		{0},					0, PROCESSOR_V850E2V3_UP },
+{ "syncm",	one (0x001e),		one (0xffff),		{0},					0, PROCESSOR_V850E2V3_UP },
+{ "syncp",	one (0x001f),		one (0xffff),		{0},					0, PROCESSOR_V850E2V3_UP },
+{ "syscall",	two (0xd7e0, 0x0160),	two (0xffe0, 0xc7ff),	{V8},					0, PROCESSOR_V850E2V3_UP },
+  /* Alias of syncp.  */
+{ "sync",	one (0x001f),		one (0xffff),		{0},					0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_ALIAS },
+{ "rmtrap",	one (0xf040),		one (0xffff),		{0},					0, PROCESSOR_V850E2V3_UP },
+{ "rie",	one (0x0040),		one (0xffff),		{0},					0, PROCESSOR_V850E2V3_UP },
+{ "rie",	two (0x07f0, 0x0000),	two (0x07f0, 0xffff),	{RIE_IMM5,RIE_IMM4},			0, PROCESSOR_V850E2V3_UP },
 
 { 0, 0, 0, {0}, 0, 0 },
 } ;