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authorRichard Sandiford <richard.sandiford@arm.com>2021-12-02 15:00:57 +0000
committerRichard Sandiford <richard.sandiford@arm.com>2021-12-02 15:00:57 +0000
commitbcca550b3dc542284715c19655c1885bdf2d3b67 (patch)
tree9595ba94a8add55664ce8192a82dc8594e8b137a /opcodes
parent63eff947512b36c770c92d45e4b22cb8a18a39be (diff)
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aarch64: Add BC instruction
This patch adds support for the Armv8.8-A BC instruction. [https://developer.arm.com/documentation/ddi0596/2021-09/Base-Instructions/BC-cond--Branch-Consistent-conditionally-?lang=en] include/ * opcode/aarch64.h (AARCH64_FEATURE_HBC): New macro. (AARCH64_ARCH_V8_8): Make armv8.8-a imply AARCH64_FEATURE_HBC. opcodes/ * aarch64-tbl.h (aarch64_feature_hbc): New variable. (HBC, HBC_INSN): New macros. (aarch64_opcode_table): Add BC.C. * aarch64-dis-2.c: Regenerate. gas/ * doc/c-aarch64.texi: Document +hbc. * config/tc-aarch64.c (aarch64_features): Add "hbc". * testsuite/gas/aarch64/hbc.s, testsuite/gas/aarch64/hbc.d: New test. * testsuite/gas/aarch64/hbc-invalid.s, testsuite/gas/aarch64/hbc-invalid.l, testsuite/gas/aarch64/hbc-invalid.d: New test.
Diffstat (limited to 'opcodes')
-rw-r--r--opcodes/aarch64-dis-2.c105
-rw-r--r--opcodes/aarch64-tbl.h7
2 files changed, 65 insertions, 47 deletions
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 70cbf90..37a0f8c 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -16913,87 +16913,98 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- if (((word >> 10) & 0x1) == 0)
+ if (((word >> 25) & 0x1) == 0)
{
- if (((word >> 21) & 0x1) == 0)
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1010100xxxxxxxxxxxxxxxxxxx1xxxx
+ bc.c. */
+ return 2631;
+ }
+ else
+ {
+ if (((word >> 10) & 0x1) == 0)
{
- if (((word >> 22) & 0x1) == 0)
+ if (((word >> 21) & 0x1) == 0)
{
- if (((word >> 23) & 0x1) == 0)
+ if (((word >> 22) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10101x0000xxxxxxxxxx0xxxxx1xxxx
- braaz. */
- return 647;
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1010110000xxxxxxxxxx0xxxxx1xxxx
+ braaz. */
+ return 647;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1010110100xxxxxxxxxx0xxxxx1xxxx
+ eretaa. */
+ return 653;
+ }
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x10101x0100xxxxxxxxxx0xxxxx1xxxx
- eretaa. */
- return 653;
+ x1010110x10xxxxxxxxxx0xxxxx1xxxx
+ retaa. */
+ return 651;
}
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x10101x0x10xxxxxxxxxx0xxxxx1xxxx
- retaa. */
- return 651;
+ x1010110xx1xxxxxxxxxx0xxxxx1xxxx
+ blraaz. */
+ return 649;
}
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10101x0xx1xxxxxxxxxx0xxxxx1xxxx
- blraaz. */
- return 649;
- }
- }
- else
- {
- if (((word >> 21) & 0x1) == 0)
- {
- if (((word >> 22) & 0x1) == 0)
+ if (((word >> 21) & 0x1) == 0)
{
- if (((word >> 23) & 0x1) == 0)
+ if (((word >> 22) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10101x0000xxxxxxxxxx1xxxxx1xxxx
- brabz. */
- return 648;
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1010110000xxxxxxxxxx1xxxxx1xxxx
+ brabz. */
+ return 648;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1010110100xxxxxxxxxx1xxxxx1xxxx
+ eretab. */
+ return 654;
+ }
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x10101x0100xxxxxxxxxx1xxxxx1xxxx
- eretab. */
- return 654;
+ x1010110x10xxxxxxxxxx1xxxxx1xxxx
+ retab. */
+ return 652;
}
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x10101x0x10xxxxxxxxxx1xxxxx1xxxx
- retab. */
- return 652;
+ x1010110xx1xxxxxxxxxx1xxxxx1xxxx
+ blrabz. */
+ return 650;
}
}
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10101x0xx1xxxxxxxxxx1xxxxx1xxxx
- blrabz. */
- return 650;
- }
}
}
}
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 51d8532..08721b1 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2497,6 +2497,8 @@ static const aarch64_feature_set aarch64_feature_mops =
AARCH64_FEATURE (AARCH64_FEATURE_MOPS, 0);
static const aarch64_feature_set aarch64_feature_mops_memtag =
AARCH64_FEATURE (AARCH64_FEATURE_MOPS | AARCH64_FEATURE_MEMTAG, 0);
+static const aarch64_feature_set aarch64_feature_hbc =
+ AARCH64_FEATURE (AARCH64_FEATURE_HBC, 0);
#define CORE &aarch64_feature_v8
#define FP &aarch64_feature_fp
@@ -2550,6 +2552,7 @@ static const aarch64_feature_set aarch64_feature_mops_memtag =
#define FLAGM &aarch64_feature_flagm
#define MOPS &aarch64_feature_mops
#define MOPS_MEMTAG &aarch64_feature_mops_memtag
+#define HBC &aarch64_feature_hbc
#define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL }
@@ -2681,6 +2684,8 @@ static const aarch64_feature_set aarch64_feature_mops_memtag =
#define MOPS_MEMTAG_INSN(NAME, OPCODE, MASK, CLASS, OPS, QUALS, FLAGS, CONSTRAINTS, VERIFIER) \
{ NAME, OPCODE, MASK, CLASS, 0, MOPS_MEMTAG, OPS, QUALS, FLAGS, \
CONSTRAINTS, 0, VERIFIER }
+#define HBC_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
+ { NAME, OPCODE, MASK, CLASS, 0, HBC, OPS, QUALS, FLAGS, 0, 0, NULL }
#define MOPS_CPY_OP1_OP2_PME_INSN(NAME, OPCODE, MASK, FLAGS, CONSTRAINTS) \
MOPS_INSN (NAME, OPCODE, MASK, 0, \
@@ -5417,6 +5422,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
setge setget setgen setgetn */
MOPS_SET_INSN ("setg", 0x1dc00400, 0xffe0fc00, MOPS_MEMTAG_INSN),
+ HBC_INSN ("bc.c", 0x54000010, 0xff000010, condbranch, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_COND),
+
{0, 0, 0, 0, 0, 0, {}, {}, 0, 0, 0, NULL},
};