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authorAlan Modra <amodra@gmail.com>2020-02-01 13:08:43 +1030
committerAlan Modra <amodra@gmail.com>2020-02-01 23:23:18 +1030
commitb2b1453ad4305f1a000a514e4dfcc09af49fb3dc (patch)
tree80574bc2d6544fdf014eea83e54e7c34b062de3c /opcodes
parentaa66aac47b4dd38f9524ddb5546c08cc09930d37 (diff)
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ubsan: frv: left shift of negative value
More non-bugs flagged by ubsan, unless you happen to be compiling for a 1's complement host. cpu/ * frv.cpu (f-u12): Multiply rather than left shift signed values. (f-label16, f-label24): Likewise. opcodes/ * frv-ibld.c: Regenerate.
Diffstat (limited to 'opcodes')
-rw-r--r--opcodes/ChangeLog4
-rw-r--r--opcodes/frv-ibld.c6
2 files changed, 7 insertions, 3 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index f163ad2..6349ff0 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2020-02-01 Alan Modra <amodra@gmail.com>
+
+ * frv-ibld.c: Regenerate.
+
2020-01-31 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
diff --git a/opcodes/frv-ibld.c b/opcodes/frv-ibld.c
index 34396f5..5e31df2 100644
--- a/opcodes/frv-ibld.c
+++ b/opcodes/frv-ibld.c
@@ -1090,7 +1090,7 @@ frv_cgen_extract_operand (CGEN_CPU_DESC cd,
{
long value;
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 15, 16, 32, total_length, pc, & value);
- value = ((((value) << (2))) + (pc));
+ value = ((((value) * (4))) + (pc));
fields->f_label16 = value;
}
break;
@@ -1101,7 +1101,7 @@ frv_cgen_extract_operand (CGEN_CPU_DESC cd,
length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 18, 32, total_length, pc, & fields->f_labelL18);
if (length <= 0) break;
{
- FLD (f_label24) = ((((((((FLD (f_labelH6)) << (18))) | (FLD (f_labelL18)))) << (2))) + (pc));
+ FLD (f_label24) = ((((((((FLD (f_labelH6)) * (((1) << (18))))) | (FLD (f_labelL18)))) * (4))) + (pc));
}
}
break;
@@ -1156,7 +1156,7 @@ frv_cgen_extract_operand (CGEN_CPU_DESC cd,
length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_u12_l);
if (length <= 0) break;
{
- FLD (f_u12) = ((((FLD (f_u12_h)) << (6))) | (FLD (f_u12_l)));
+ FLD (f_u12) = ((((FLD (f_u12_h)) * (64))) | (FLD (f_u12_l)));
}
}
break;