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| author | Cooper Qu <cooper.qu@linux.alibaba.com> | 2020-09-02 14:06:03 +0800 |
|---|---|---|
| committer | Lifang Xia <lifang_xia@c-sky.com> | 2020-09-02 14:21:31 +0800 |
| commit | 4211a3400108b45732415cda0cacb087ab8690b1 (patch) | |
| tree | 780aa663468ff715258195d610048c841aeda8ea /opcodes | |
| parent | 8119cc38379eb136a62b64f642ab4e3b6d4c6abd (diff) | |
| download | gdb-4211a3400108b45732415cda0cacb087ab8690b1.zip gdb-4211a3400108b45732415cda0cacb087ab8690b1.tar.gz gdb-4211a3400108b45732415cda0cacb087ab8690b1.tar.bz2 | |
CSKY: Add CPU CK803r3.
Move divul and divsl to CSKYV2_ISA_3E3R3 instruction set, which is
enabled by ck803r3, and it's still a part of enhance DSP instruction
set.
gas/
* config/tc-csky.c (csky_cpus): Add ck803r3.
(CSKY_ISA_803R3): Define.
(CSKY_ISA_803R2): Refine, use CSKY_ISA_803R1.
include/
* opcode/csky.h (CSKYV2_ISA_3E3R3): Define.
opcodes/
* csky-opc.h (csky_v2_opcodes): Move divul and divsl
to CSKYV2_ISA_3E3R3 instruction set.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/csky-opc.h | 4 |
2 files changed, 7 insertions, 2 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index a4e95ae..8481a13 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,10 @@ 2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com> + * csky-opc.h (csky_v2_opcodes): Move divul and divsl + to CSKYV2_ISA_3E3R3 instruction set. + +2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com> + * csky-opc.h (csky_v2_opcodes): Fix Encode of mulsws. 2020-09-01 Alan Modra <amodra@gmail.com> diff --git a/opcodes/csky-opc.h b/opcodes/csky-opc.h index 54203aa..5e2f1a5 100644 --- a/opcodes/csky-opc.h +++ b/opcodes/csky-opc.h @@ -5321,13 +5321,13 @@ const struct csky_opcode csky_v2_opcodes[] = (0_4, AREG, OPRND_SHIFT_0_BIT), (16_20, AREG, OPRND_SHIFT_0_BIT), (21_25, AREG, OPRND_SHIFT_0_BIT)), - CSKY_ISA_DSP_ENHANCE), + CSKYV2_ISA_3E3R3), OP32 ("divsl", OPCODE_INFO3 (0xf800e2e0, (0_4, AREG, OPRND_SHIFT_0_BIT), (16_20, AREG, OPRND_SHIFT_0_BIT), (21_25, AREG, OPRND_SHIFT_0_BIT)), - CSKY_ISA_DSP_ENHANCE), + CSKYV2_ISA_3E3R3), OP32 ("mulaca.s8", OPCODE_INFO3 (0xf800e4c0, (0_4, AREG, OPRND_SHIFT_0_BIT), |