2010-09-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>

	* s390-mkopc.c (enum s390_opcde_cpu_val): Add S390_OPCODE_Z196.
	(main): Recognize the new CPU string.
	* s390-opc.c: Add new instruction formats and masks.
	* s390-opc.txt: Add new z196 instructions.

2010-09-27  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>

	* opcode/s390.h: Add S390_OPCODE_Z196 to enum s390_opcode_cpu_val.

2010-09-27  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>

	* config/tc-s390.c: (md_parse_option): New option -march=z196.
	* doc/c-s390.texi: Document new option.

2010-09-27  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>

	* gas/s390/s390.exp: Run the zarch-z196 test.
	* gas/s390/zarch-z196.d: Add new instructions.
	* gas/s390/zarch-z196.s: Likewise.
	* gas/s390/zarch-z9-109.d: Likewise.
	* gas/s390/zarch-z9-109.s: Likewise.

4 files changed, 165 insertions, 4 deletions

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 8a7b998..e219100 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,12 @@
 2010-09-27  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 
+	* s390-mkopc.c (enum s390_opcde_cpu_val): Add S390_OPCODE_Z196.
+	(main): Recognize the new CPU string.
+	* s390-opc.c: Add new instruction formats and masks.
+	* s390-opc.txt: Add new z196 instructions.
+
+2010-09-27  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
+
 	* s390-dis.c (print_insn_s390): Pick instruction with most
 	specific mask.
 	* s390-opc.c: Add unused bits to the insn mask.
diff --git a/opcodes/s390-mkopc.c b/opcodes/s390-mkopc.c
index 1c1803e..84981cc 100644
--- a/opcodes/s390-mkopc.c
+++ b/opcodes/s390-mkopc.c
@@ -38,7 +38,8 @@ enum s390_opcode_cpu_val
     S390_OPCODE_Z990,
     S390_OPCODE_Z9_109,
     S390_OPCODE_Z9_EC,
-    S390_OPCODE_Z10
+    S390_OPCODE_Z10,
+    S390_OPCODE_Z196
   };
 
 struct op_struct
@@ -362,6 +363,8 @@ main (void)
 	    min_cpu = S390_OPCODE_Z9_EC;
 	  else if (strcmp (cpu_string, "z10") == 0)
 	    min_cpu = S390_OPCODE_Z10;
+	  else if (strcmp (cpu_string, "z196") == 0)
+	    min_cpu = S390_OPCODE_Z196;
 	  else {
 	    fprintf (stderr, "Couldn't parse cpu string %s\n", cpu_string);
 	    exit (1);
diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c
index 1a6628d..fea838e 100644
--- a/opcodes/s390-opc.c
+++ b/opcodes/s390-opc.c
@@ -178,7 +178,7 @@ const struct s390_operand s390_operands[] =
 
 /* Conditional mask operands.  */
 
-#define M_16   52                 /* 4 bit optional mask starting at 16 */
+#define M_16OPT   52              /* 4 bit optional mask starting at 16 */
   { 4, 16, S390_OPERAND_OPTIONAL },
 
 };
@@ -231,6 +231,7 @@ const struct s390_operand s390_operands[] =
 #define INSTR_RIE_RRP    6, { R_8,R_12,J16_16,0,0,0 }          /* e.g. brxhg */
 #define INSTR_RIE_RRPU   6, { R_8,R_12,U4_32,J16_16,0,0 }      /* e.g. crj   */
 #define INSTR_RIE_RRP0   6, { R_8,R_12,J16_16,0,0,0 }          /* e.g. crjne */
+#define INSTR_RIE_RRI0   6, { R_8,R_12,I16_16,0,0,0 }          /* e.g. ahik  */
 #define INSTR_RIE_RUPI   6, { R_8,I8_32,U4_12,J16_16,0,0 }     /* e.g. cij   */
 #define INSTR_RIE_R0PI   6, { R_8,I8_32,J16_16,0,0,0 }         /* e.g. cijne */
 #define INSTR_RIE_RUPU   6, { R_8,U8_32,U4_12,J16_16,0,0 }     /* e.g. clij  */
@@ -272,16 +273,20 @@ const struct s390_operand s390_operands[] =
 #define INSTR_RRF_F0FF2  4, { F_24,F_16,F_28,0,0,0 }           /* e.g. cpsdr */
 #define INSTR_RRF_F0FR   4, { F_24,F_16,R_28,0,0,0 }           /* e.g. iedtr */
 #define INSTR_RRF_FUFF   4, { F_24,F_16,F_28,U4_20,0,0 }       /* e.g. didbr */
+#define INSTR_RRF_FUFF2  4, { F_24,F_28,F_16,U4_20,0,0 }       /* e.g. adtra */
 #define INSTR_RRF_RURR   4, { R_24,R_28,R_16,U4_20,0,0 }       /* e.g. .insn */
 #define INSTR_RRF_R0RR   4, { R_24,R_16,R_28,0,0,0 }           /* e.g. idte  */
+#define INSTR_RRF_R0RR2  4, { R_24,R_28,R_16,0,0,0 }           /* e.g. ark   */
 #define INSTR_RRF_U0FF   4, { F_24,U4_16,F_28,0,0,0 }          /* e.g. fixr  */
 #define INSTR_RRF_U0RF   4, { R_24,U4_16,F_28,0,0,0 }          /* e.g. cfebr */
 #define INSTR_RRF_UUFF   4, { F_24,U4_16,F_28,U4_20,0,0 }      /* e.g. fidtr */
 #define INSTR_RRF_0UFF   4, { F_24,F_28,U4_20,0,0,0 }          /* e.g. ldetr */
 #define INSTR_RRF_FFRU   4, { F_24,F_16,R_28,U4_20,0,0 }       /* e.g. rrdtr */
-#define INSTR_RRF_M0RR   4, { R_24,R_28,M_16,0,0,0 }           /* e.g. sske  */
+#define INSTR_RRF_M0RR   4, { R_24,R_28,M_16OPT,0,0,0 }        /* e.g. sske  */
 #define INSTR_RRF_U0RR   4, { R_24,R_28,U4_16,0,0,0 }          /* e.g. clrt  */
 #define INSTR_RRF_00RR   4, { R_24,R_28,0,0,0,0 }              /* e.g. clrtne */
+#define INSTR_RRF_UUFR   4, { F_24,U4_16,R_28,U4_20,0,0 }      /* e.g. cdgtra */
+#define INSTR_RRF_UURF   4, { R_24,U4_16,F_28,U4_20,0,0 }      /* e.g. cgdtra */
 #define INSTR_RR_0R      2, { R_12, 0,0,0,0,0 }                /* e.g. br    */
 #define INSTR_RR_0R_OPT  2, { RO_12, 0,0,0,0,0 }               /* e.g. nopr  */
 #define INSTR_RR_FF      2, { F_8,F_12,0,0,0,0 }               /* e.g. adr   */
@@ -301,6 +306,8 @@ const struct s390_operand s390_operands[] =
 #define INSTR_RSY_RURD   6, { R_8,U4_12,D20_20,B_16,0,0 }      /* e.g. icmh  */
 #define INSTR_RSY_AARD   6, { A_8,A_12,D20_20,B_16,0,0 }       /* e.g. lamy  */
 #define INSTR_RSY_CCRD   6, { C_8,C_12,D20_20,B_16,0,0 }       /* e.g. lamy  */
+#define INSTR_RSY_RDRM   6, { R_8,D20_20,B_16,U4_12,0,0 }      /* e.g. loc   */
+#define INSTR_RSY_RDR0   6, { R_8,D20_20,B_16,0,0,0 }          /* e.g. loc   */
 #define INSTR_RS_AARD    4, { A_8,A_12,D_20,B_16,0,0 }         /* e.g. lam   */
 #define INSTR_RS_CCRD    4, { C_8,C_12,D_20,B_16,0,0 }         /* e.g. lctl  */
 #define INSTR_RS_R0RD    4, { R_8,D_20,B_16,0,0,0 }            /* e.g. sll   */
@@ -332,6 +339,7 @@ const struct s390_operand s390_operands[] =
 #define INSTR_SS_RRRDRD2 6, { R_8,D_20,B_16,R_12,D_36,B_32 }   /* e.g. plo   */
 #define INSTR_SS_RRRDRD3 6, { R_8,R_12,D_20,B_16,D_36,B_32 }   /* e.g. lmd   */
 #define INSTR_SSF_RRDRD  6, { D_20,B_16,D_36,B_32,R_8,0 }      /* e.g. mvcos */
+#define INSTR_SSF_RRDRD2 6, { R_8,D_20,B_16,D_36,B_32,0 }      /* e.g. lpd   */
 #define INSTR_S_00       4, { 0,0,0,0,0,0 }                    /* e.g. hsch  */
 #define INSTR_S_RD       4, { D_20,B_16,0,0,0,0 }              /* e.g. lpsw  */
 
@@ -339,6 +347,7 @@ const struct s390_operand s390_operands[] =
 #define MASK_RIE_RRP     { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 #define MASK_RIE_RRPU    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 #define MASK_RIE_RRP0    { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff }
+#define MASK_RIE_RRI0    { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff }
 #define MASK_RIE_RUPI    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 #define MASK_RIE_R0PI    { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff }
 #define MASK_RIE_RUPU    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
@@ -378,8 +387,10 @@ const struct s390_operand s390_operands[] =
 #define MASK_RRF_F0FF2   { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
 #define MASK_RRF_F0FR    { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
 #define MASK_RRF_FUFF    { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RRF_FUFF2   { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RRF_RURR    { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RRF_R0RR    { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RRF_R0RR2   { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RRF_U0FF    { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
 #define MASK_RRF_U0RF    { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
 #define MASK_RRF_UUFF    { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
@@ -388,6 +399,8 @@ const struct s390_operand s390_operands[] =
 #define MASK_RRF_M0RR    { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
 #define MASK_RRF_U0RR    { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
 #define MASK_RRF_00RR    { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
+#define MASK_RRF_UUFR    { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RRF_UURF    { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RR_0R       { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RR_0R_OPT   { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RR_FF       { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
@@ -412,6 +425,8 @@ const struct s390_operand s390_operands[] =
 #define MASK_RSY_RURD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 #define MASK_RSY_AARD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 #define MASK_RSY_CCRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+#define MASK_RSY_RDRM    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+#define MASK_RSY_RDR0    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 #define MASK_RXE_FRRD    { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff }
 #define MASK_RXE_RRRD    { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff }
 #define MASK_RXF_FRRDF   { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff }
@@ -438,6 +453,7 @@ const struct s390_operand s390_operands[] =
 #define MASK_SS_RRRDRD2  { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_SS_RRRDRD3  { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_SSF_RRDRD   { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_SSF_RRDRD2  { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_S_00        { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 }
 #define MASK_S_RD        { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
 
diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt
index 36a2d03..9393ba4 100644
--- a/opcodes/s390-opc.txt
+++ b/opcodes/s390-opc.txt
@@ -419,7 +419,7 @@ e3000000000e cvbg RXE_RRRD "convert to binary 64" z900 zarch
 e30000000024 stg RXE_RRRD "store 64" z900 zarch
 e30000000080 ng RXE_RRRD "and 64" z900 zarch
 e30000000021 clg RXE_RRRD "compare logical 64" z900 zarch
-e30000000031 clgf RXE_RRRD "comparee logical 64<32" z900 zarch
+e30000000031 clgf RXE_RRRD "compare logical 64<32" z900 zarch
 e30000000081 og RXE_RRRD "or 64" z900 zarch
 e30000000082 xg RXE_RRRD "exclusive or 64" z900 zarch
 e30000000004 lg RXE_RRRD "load 64" z900 zarch
@@ -776,6 +776,8 @@ b9b2 cu41 RRE_RR "convert utf-32 to utf-8" z9-109 zarch
 b2a7 cu12 RRF_M0RR "convert utf-8 to utf-16" z9-109 zarch
 b2a7 cutfu RRF_M0RR "convert utf-8 to unicode" z9-109 zarch
 b9b0 cu14 RRF_M0RR "convert utf-8 to utf-32" z9-109 zarch
+b9eb srstu RRE_RR "search string unicode" z9-109 zarch
+d0 trtr SS_L0RDRD "tranlate and test reverse" z9-109 zarch
 # z9-109 unnormalized hfp multiply & multiply and add
 b33b myr RRF_F0FF "multiply unnormalized long hfp" z9-109 zarch
 b33d myhr RRF_F0FF "multiply unnormalized long hfp high" z9-109 zarch
@@ -958,3 +960,136 @@ b9a2 ptf RRE_R0 "perform topology function" z10 zarch
 b9af pfmf RRE_RR "perform frame management function" z10 zarch
 b9bf trte RRF_M0RR "translate and test extended" z10 zarch
 b9bd trtre RRF_M0RR "translate and test reverse extended" z10 zarch
+b9c8 ahhhr RRF_R0RR2 "add high high" z196 zarch
+b9d8 ahhlr RRF_R0RR2 "add high low" z196 zarch
+cc08 aih RIL_RI "add immediate high" z196 zarch
+b9ca alhhhr RRF_R0RR2 "add logical high high" z196 zarch
+b9da alhhlr RRF_R0RR2 "add logical high low" z196 zarch
+cc0a alsih RIL_RI "add logical with signed immediate high with cc" z196 zarch
+cc0b alsihn RIL_RI "add logical with signed immediate high no cc" z196 zarch
+cc06 brcth RIL_RP "branch relative on count high" z196 zarch
+b9cd chhr RRE_RR "compare high high" z196 zarch
+b9dd chlr RRE_RR "compare high low" z196 zarch
+e300000000cd chf RXY_RRRD "compare high" z196 zarch
+cc0d cih RIL_RI "compare immediate high" z196 zarch
+b9cf clhhr RRE_RR "compare logical high high" z196 zarch
+b9df clhlr RRE_RR "compare logical high low" z196 zarch
+e300000000cf clhf RXY_RRRD "compare logical high" z196 zarch
+cc0f clih RIL_RI "compare logical immediate" z196 zarch
+e300000000c0 lbh RXY_RRRD "load byte high" z196 zarch
+e300000000c4 lhh RXY_RRRD "load halfword high" z196 zarch
+e300000000ca lfh RXY_RRRD "load high" z196 zarch
+e300000000c2 llch RXY_RRRD "load logical character high" z196 zarch
+e300000000c6 llhh RXY_RRRD "load logical halfword high" z196 zarch
+ec000000005D risbhg RIE_RRUUU "rotate then insert selected bits high" z196 zarch
+ec0000000051 risblg RIE_RRUUU "rotate then insert selected bits low" z196 zarch
+e300000000c3 stch RXY_RRRD "store character high" z196 zarch
+e300000000c7 sthh RXY_RRRD "store halfword high" z196 zarch
+e300000000cb stfh RXY_RRRD "store high" z196 zarch
+b9c9 shhhr RRF_R0RR2 "subtract high high" z196 zarch
+b9d9 shhlr RRF_R0RR2 "subtract high low" z196 zarch
+b9cb slhhhr RRF_R0RR2 "subtract logical high high" z196 zarch
+b9db slhhlr RRF_R0RR2 "subtract logical high low" z196 zarch
+eb00000000f8 laa RSY_RRRD "load and add 32 bit" z196 zarch
+eb00000000e8 laag RSY_RRRD "load and add 64 bit" z196 zarch
+eb00000000fa laal RSY_RRRD "load and add logical 32 bit" z196 zarch
+eb00000000ea laalg RSY_RRRD "load and add logical 64 bit" z196 zarch
+eb00000000f4 lan RSY_RRRD "load and and 32 bit" z196 zarch
+eb00000000e4 lang RSY_RRRD "load and and 64 bit" z196 zarch
+eb00000000f7 lax RSY_RRRD "load and exclusive or 32 bit" z196 zarch
+eb00000000e7 laxg RSY_RRRD "load and exclusive or 64 bit" z196 zarch
+eb00000000f6 lao RSY_RRRD "load and or 32 bit" z196 zarch
+eb00000000e6 laog RSY_RRRD "load and or 64 bit" z196 zarch
+c804 lpd SSF_RRDRD2 "load pair disjoint 32 bit" z196 zarch
+c805 lpdg SSF_RRDRD2 "load pair disjoint 64 bit" z196 zarch
+b9f2 locr RRF_U0RR "load on condition 32 bit" z196 zarch
+b9f200000000 locr*16 RRF_00RR "load on condition 32 bit" z196 zarch
+b9e2 locgr RRF_U0RR "load on condition 64  bit" z196 zarch
+b9e200000000 locgr*16 RRF_00RR "load on condition 64  bit" z196 zarch
+eb00000000f2 loc RSY_RDRM "load on condition 32 bit" z196 zarch
+eb00000000f2 loc*12 RSY_RDR0 "load on condition 32 bit" z196 zarch
+eb00000000e2 lgoc RSY_RDRM "load on condition 64 bit" z196 zarch
+eb00000000e2 lgoc*12 RSY_RDR0 "load on condition 64 bit" z196 zarch
+eb00000000f3 stoc RSY_RDRM "store on condition 32 bit" z196 zarch
+eb00000000f3 stoc*12 RSY_RDR0 "store on condition 32 bit" z196 zarch
+eb00000000e3 stgoc RSY_RDRM "store on condition 64 bit" z196 zarch
+eb00000000e3 stgoc*12 RSY_RDR0 "store on condition 64 bit" z196 zarch
+b9f8 ark RRF_R0RR2 "add 3 operands 32 bit" z196 zarch
+b9e8 agrk RRF_R0RR2 "add 3 operands 64 bit" z196 zarch
+ec00000000d8 ahik RIE_RRI0 "add immediate 3 operands 32 bit" z196 zarch
+ec00000000d9 aghik RIE_RRI0 "add immediate 3 operands 64 bit" z196 zarch
+b9fa alrk RRF_R0RR2 "add logical 3 operands 32 bit" z196 zarch
+b9ea algrk RRF_R0RR2 "add logical 3 operands 64 bit" z196 zarch
+ec00000000da alhsik RIE_RRI0 "add logical immediate 3 operands 32 bit" z196 zarch
+ec00000000db alghsik RIE_RRI0 "add logical immediate 3 operands 64 bit" z196 zarch
+b9f4 nrk RRF_R0RR2 "and 3 operands 32 bit" z196 zarch
+b9e4 ngrk RRF_R0RR2 "and 3 operands 64 bit" z196 zarch
+b9f7 xrk RRF_R0RR2 "xor 3 operands 32 bit" z196 zarch
+b9e7 xgrk RRF_R0RR2 "xor 3 operands 64 bit" z196 zarch
+b9f6 ork RRF_R0RR2 "or 3 operands 32 bit" z196 zarch
+b9e6 ogrk RRF_R0RR2 "or 3 operands 64 bit" z196 zarch
+eb00000000dd slak RSY_RRRD "shift left single 3 operands 32 bit" z196 zarch
+eb00000000df sllk RSY_RRRD "shift left single logical 3 operands 32 bit" z196 zarch
+eb00000000dc srak RSY_RRRD "shift right single 3 operands 32 bit" z196 zarch
+eb00000000de srlk RSY_RRRD "shift right single logical 3 operands 32 bit" z196 zarch
+b9f9 srk RRF_R0RR2 "subtract 3 operands 32 bit" z196 zarch
+b9e9 sgrk RRF_R0RR2 "subtract 3 operands 64 bit" z196 zarch
+b9fb slrk RRF_R0RR2 "subtract logical 3 operands 32 bit" z196 zarch
+b9eb slgrk RRF_R0RR2 "subtract logical 3 operands 64 bit" z196 zarch
+b9e1 popcnt RRE_RR "population count" z196 zarch
+b9ae rrbm RRE_RR "reset reference bits multiple" z196 zarch
+b394 cefbra RRF_UUFR "convert from 32 bit fixed to short bfp with rounding mode" z196 zarch
+b395 cdfbra RRF_UUFR "convert from 32 bit fixed to long bfp with rounding mode" z196 zarch
+b396 cxfbra RRF_UUFR "convert from 32 bit fixed to extended bfp with rounding mode" z196 zarch
+b3a4 cegbra RRF_UUFR "convert from 64 bit fixed to short bfp with rounding mode" z196 zarch
+b3a5 cdgbra RRF_UUFR "convert from 64 bit fixed to long bfp with rounding mode" z196 zarch
+b3a6 cxgbra RRF_UUFR "convert from 64 bit fixed to extended bfp with rounding mode" z196 zarch
+b390 celfbr RRF_UUFR "convert from 32 bit logical fixed to short bfp with rounding mode" z196 zarch
+b391 cdlfbr RRF_UUFR "convert from 32 bit logical fixed to long bfp with rounding mode" z196 zarch
+b392 cxlfbr RRF_UUFR "convert from 32 bit logical fixed to extended bfp with rounding mode" z196 zarch
+b3a0 celgbr RRF_UUFR "convert from 64 bit logical fixed to short bfp with rounding mode" z196 zarch
+b3a1 cdlgbr RRF_UUFR "convert from 64 bit logical fixed to long bfp with rounding mode" z196 zarch
+b3a2 cxlgbr RRF_UUFR "convert from 64 bit logical fixed to extended bfp with rounding mode" z196 zarch
+b398 cfebra RRF_UURF "convert to 32 bit fixed from short bfp with rounding mode" z196 zarch
+b399 cfdbra RRF_UURF "convert to 32 bit fixed from long bfp with rounding mode" z196 zarch
+b39a cfxbra RRF_UURF "convert to 32 bit fixed from extended bfp with rounding mode" z196 zarch
+b3a8 cgebra RRF_UURF "convert to 64 bit fixed from short bfp with rounding mode" z196 zarch
+b3a9 cgdbra RRF_UURF "convert to 64 bit fixed from long bfp with rounding mode" z196 zarch
+b3aa cgxbra RRF_UURF "convert to 64 bit fixed from extended bfp with rounding mode" z196 zarch
+b39c clfebr RRF_UURF "convert to 32 bit fixed logical from short bfp with rounding mode" z196 zarch
+b39d clfdbr RRF_UURF "convert to 32 bit fixed logical from long bfp with rounding mode" z196 zarch
+b39e clfxbr RRF_UURF "convert to 32 bit fixed logical from extended bfp with rounding mode" z196 zarch
+b3ac clgebr RRF_UURF "convert to 64 bit fixed logical from short bfp with rounding mode" z196 zarch
+b3ad clgdbr RRF_UURF "convert to 64 bit fixed logical from long bfp with rounding mode" z196 zarch
+b3ae clgxbr RRF_UURF "convert to 64 bit fixed logical from extended bfp with rounding mode" z196 zarch
+b357 fiebra RRF_UUFF "load fp integer short bfp with rounding mode" z196 zarch
+b35f fidbra RRF_UUFF "load fp integer long bfp with rounding mode" z196 zarch
+b347 fixbra RRF_UUFF "load fp integer extended bfp with rounding mode" z196 zarch
+b344 ledbra RRF_UUFF "load rounded short/long bfp to short/long bfp with rounding mode" z196 zarch
+b345 ldxbra RRF_UUFF "load rounded long/extended bfp to long/extended bfp with rounding mode" z196 zarch
+b346 lexbra RRF_UUFF "load rounded short/extended bfp to short/extended bfp with rounding mode" z196 zarch
+b3d2 adtra RRF_FUFF2 "add long dfp with rounding mode" z196 zarch
+b3da axtra RRF_FUFF2 "add extended dfp with rounding mode" z196 zarch
+b3f1 cdgtra RRF_UUFR "convert from fixed long dfp with rounding mode" z196 zarch
+b951 cdftr RRF_UUFR "convert from 32 bit fixed to long dfp with rounding mode" z196 zarch
+b959 cxftr RRF_UUFR "convert from 32 bit fixed to extended dfp with rounding mode" z196 zarch
+b3f9 cxgtra RRF_UUFR "convert from fixed extended dfp with rounding mode" z196 zarch
+b952 cdlgtr RRF_UUFR "convert from 64 bit fixed logical to long dfp with rounding mode" z196 zarch
+b95a cxlgtr RRF_UUFR "convert from 64 bit fixed logical to extended dfp with rounding mode" z196 zarch
+b953 cdlftr RRF_UUFR "convert from 32 bit fixed logical to long dfp with rounding mode" z196 zarch
+b95b cxlftr RRF_UUFR "convert from 32 bit fixed logical to extended dfp with rounding mode" z196 zarch
+b3e1 cgdtra RRF_UURF "convert to 64 bit fixed from long dfp with rounding mode" z196 zarch
+b3e9 cgxtra RRF_UURF "convert to 64 bit fixed from extended dfp with rounding mode" z196 zarch
+b941 cfdtr RRF_UURF "convert to 32 bit fixed from long dfp source with rounding mode" z196 zarch
+b949 cfxtr RRF_UURF "convert to 32 bit fixed from extended dfp source with rounding mode" z196 zarch
+b942 clgdtr RRF_UURF "convert to 64 bit fixed logical from long dfp with rounding mode" z196 zarch
+b94a clgxtr RRF_UURF "convert to 64 bit fixed logical from extended dfp with rounding mode" z196 zarch
+b943 clfdtr RRF_UURF "convert to 32 bit fixed logical from long dfp with rounding mode" z196 zarch
+b94b clfxtr RRF_UURF "convert to 32 bit fixed logical from extended dfp with rounding mode" z196 zarch
+b3d1 ddtra RRF_FUFF2 "divide long dfp with rounding mode" z196 zarch
+b3d9 dxtra RRF_FUFF2 "divide extended dfp with rounding mode" z196 zarch
+b3d0 mdtra RRF_FUFF2 "multiply long dfp with rounding mode" z196 zarch
+b3d8 mxtra RRF_FUFF2 "multiply extended dfp with rounding mode" z196 zarch
+b3d3 sdtra RRF_FUFF2 "subtract long dfp with rounding mode" z196 zarch
+b3db sxtra RRF_FUFF2 "subtract extended dfp with rounding mode" z196 zarch
+b2b8 srnmb S_RD "set 3 bit bfp rounding mode" z196 zarch