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| author | Martin Hunt <hunt@redhat.com> | 1996-08-03 00:49:00 +0000 |
|---|---|---|
| committer | Martin Hunt <hunt@redhat.com> | 1996-08-03 00:49:00 +0000 |
| commit | c5e1996f556dde0f9c04c0fd82619d276c705210 (patch) | |
| tree | 4eca3b2be8576065c641fab3354400518990cd12 /opcodes | |
| parent | 4c38885c8646a891e02e99166df57b0030bd6b2d (diff) | |
| download | gdb-c5e1996f556dde0f9c04c0fd82619d276c705210.zip gdb-c5e1996f556dde0f9c04c0fd82619d276c705210.tar.gz gdb-c5e1996f556dde0f9c04c0fd82619d276c705210.tar.bz2 | |
Fri Aug 2 17:47:03 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* d10v-opc.c (d10v_operands): Added 2 accumulator sub instructions.
Changed subi operand type to treat 0 as 16.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 7 | ||||
| -rw-r--r-- | opcodes/d10v-opc.c | 6 |
2 files changed, 11 insertions, 2 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 0f55073..d40b864 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,10 @@ +start-sanitize-d10v +Fri Aug 2 17:47:03 1996 Martin M. Hunt <hunt@pizza.cygnus.com> + + * d10v-opc.c (d10v_operands): Added 2 accumulator sub instructions. + Changed subi operand type to treat 0 as 16. + +end-sanitize-d10v Wed Jul 31 16:21:41 1996 Ian Lance Taylor <ian@cygnus.com> * m68k-opc.c: Add cpushl for the mcf5200. From Ken Rose diff --git a/opcodes/d10v-opc.c b/opcodes/d10v-opc.c index 07d5428..a8f6f8f 100644 --- a/opcodes/d10v-opc.c +++ b/opcodes/d10v-opc.c @@ -90,7 +90,7 @@ const struct d10v_operand d10v_operands[] = { 4, 1, OPERAND_NUM|OPERAND_SIGNED }, #define UNUM4 (NUM4 + 1) { 4, 1, OPERAND_NUM }, -#define UNUM4S (UNUM4 + 1) /* slli, srai, srli */ +#define UNUM4S (UNUM4 + 1) /* slli, srai, srli, subi */ { 4, 1, OPERAND_NUM|OPERAND_SHIFT }, #define UNUM8 (UNUM4S + 1) /* repi */ { 8, 16, OPERAND_NUM }, @@ -281,12 +281,14 @@ const struct d10v_opcode d10v_opcodes[] = { { "stb", SHORT_2, 1, MU, PAR, 0x7800, 0x7e01, { RSRC2, ATSIGN, RSRC } }, { "stop", SHORT_2, 1, MU, PAR, 0x5fe0, 0x7fff, { 0 } }, { "sub", SHORT_2, 1, EITHER, PAR, 0x0, 0x7e01, { RDST, RSRC } }, + { "sub", SHORT_2, 1, IU, PAR, 0x1001, 0x7ee3, { ADST, RSRC } }, + { "sub", SHORT_2, 1, IU, PAR, 0x1003, 0x7eef, { ADST, ASRC } }, { "sub2w", SHORT_2, 1, IU, PAR, 0x1000, 0x7e23, { RDSTE, RSRCE } }, { "subac3", LONG_R, 1, IU, SEQ, 0x17000000, 0x3ffffe22, { RDSTE, RSRCE, ASRC0 } }, { "subac3", LONG_R, 1, IU, SEQ, 0x17000002, 0x3ffffe2e, { RDSTE, ASRC, ASRC0 } }, { "subac3s", LONG_R, 1, IU, SEQ, 0x17001000, 0x3ffffe22, { RDSTE, RSRCE, ASRC0 } }, { "subac3s", LONG_R, 1, IU, SEQ, 0x17001002, 0x3ffffe2e, { RDSTE, ASRC, ASRC0 } }, - { "subi", SHORT_2, 1, EITHER, PAR, 0x1, 0x7e01, { RDST, UNUM4 } }, + { "subi", SHORT_2, 1, EITHER, PAR, 0x1, 0x7e01, { RDST, UNUM4S } }, { "trap", SHORT_2, 5, MU, PAR, 0x5f00, 0x7fe1, { UNUM4 } }, { "tst0i", LONG_L, 1, MU, SEQ, 0x7000000, 0x3f0f0000, { RSRC2, NUM16 } }, { "tst1i", LONG_L, 1, MU, SEQ, 0xf000000, 0x3f0f0000, { RSRC2, NUM16 } }, |