2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>

	* config/tc-s390.c (md_gather_operands): Emit an error for odd
	numbered registers used as register pair operand.

2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>

	* opcode/s390.h: Add S390_OPCODE_REG_EVEN flag.

2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>

	* s390-opc.c: Add new instruction types marking register pair
	operands.
	* s390-opc.txt: Match instructions having register pair operands
	to the new instruction types.

2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>

	* gas/s390/esa-g5.d: Fix register pair operands.
	* gas/s390/esa-g5.s: Likewise.
	* gas/s390/esa-z9-109.d: Likewise.
	* gas/s390/esa-z9-109.s: Likewise.
	* gas/s390/zarch-z196.d: Likewise.
	* gas/s390/zarch-z196.s: Likewise.
	* gas/s390/zarch-z9-109.d: Likewise.
	* gas/s390/zarch-z9-109.s: Likewise.
	* gas/s390/zarch-z900.d: Likewise.
	* gas/s390/zarch-z900.s: Likewise.
	* gas/s390/zarch-z990.d: Likewise.
	* gas/s390/zarch-z990.s: Likewise.

3 files changed, 329 insertions, 205 deletions

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index ac5e82c..9fd9b23 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,10 @@
+2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
+
+	* s390-opc.c: Add new instruction types marking register pair
+	operands.
+	* s390-opc.txt: Match instructions having register pair operands
+	to the new instruction types.
+
 2011-05-19  Nick Clifton  <nickc@redhat.com>
 
 	* v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2
diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c
index 2f1487d..8b544cf 100644
--- a/opcodes/s390-opc.c
+++ b/opcodes/s390-opc.c
@@ -50,7 +50,7 @@ const struct s390_operand s390_operands[] =
 #define R_12   2                  /* GPR starting at position 12 */
   { 4, 12, S390_OPERAND_GPR },
 #define RO_12  3                 /* optional GPR starting at position 12 */
-  { 4, 12, S390_OPERAND_GPR|S390_OPERAND_OPTIONAL },
+  { 4, 12, S390_OPERAND_GPR | S390_OPERAND_OPTIONAL },
 #define R_16   4                  /* GPR starting at position 16 */
   { 4, 16, S390_OPERAND_GPR },
 #define R_20   5                  /* GPR starting at position 20 */
@@ -64,121 +64,157 @@ const struct s390_operand s390_operands[] =
 #define R_32   9                  /* GPR starting at position 32 */
   { 4, 32, S390_OPERAND_GPR },
 
+/* General purpose register pair operands.  */
+
+#define RE_8    10                  /* GPR starting at position 8 */
+  { 4, 8, S390_OPERAND_GPR | S390_OPERAND_REG_EVEN },
+#define RE_12   11                  /* GPR starting at position 12 */
+  { 4, 12, S390_OPERAND_GPR | S390_OPERAND_REG_EVEN },
+#define RE_16   12                  /* GPR starting at position 16 */
+  { 4, 16, S390_OPERAND_GPR | S390_OPERAND_REG_EVEN },
+#define RE_20   13                  /* GPR starting at position 20 */
+  { 4, 20, S390_OPERAND_GPR | S390_OPERAND_REG_EVEN },
+#define RE_24   14                  /* GPR starting at position 24 */
+  { 4, 24, S390_OPERAND_GPR | S390_OPERAND_REG_EVEN },
+#define RE_28   15                  /* GPR starting at position 28 */
+  { 4, 28, S390_OPERAND_GPR | S390_OPERAND_REG_EVEN },
+#define RE_32   16                  /* GPR starting at position 32 */
+  { 4, 32, S390_OPERAND_GPR | S390_OPERAND_REG_EVEN },
+
+
 /* Floating point register operands.  */
 
-#define F_8    10                 /* FPR starting at position 8 */
+#define F_8    17                 /* FPR starting at position 8 */
   { 4, 8, S390_OPERAND_FPR },
-#define F_12   11                 /* FPR starting at position 12 */
+#define F_12   18                 /* FPR starting at position 12 */
   { 4, 12, S390_OPERAND_FPR },
-#define F_16   12                 /* FPR starting at position 16 */
+#define F_16   19                 /* FPR starting at position 16 */
   { 4, 16, S390_OPERAND_FPR },
-#define F_20   13                 /* FPR starting at position 16 */
+#define F_20   20                 /* FPR starting at position 16 */
   { 4, 16, S390_OPERAND_FPR },
-#define F_24   14                 /* FPR starting at position 24 */
+#define F_24   21                 /* FPR starting at position 24 */
   { 4, 24, S390_OPERAND_FPR },
-#define F_28   15                 /* FPR starting at position 28 */
+#define F_28   22                 /* FPR starting at position 28 */
   { 4, 28, S390_OPERAND_FPR },
-#define F_32   16                 /* FPR starting at position 32 */
+#define F_32   23                 /* FPR starting at position 32 */
   { 4, 32, S390_OPERAND_FPR },
 
+/* Floating point register pair operands.  */
+
+#define FE_8    24                 /* FPR starting at position 8 */
+  { 4, 8, S390_OPERAND_FPR | S390_OPERAND_REG_EVEN },
+#define FE_12   25                 /* FPR starting at position 12 */
+  { 4, 12, S390_OPERAND_FPR | S390_OPERAND_REG_EVEN },
+#define FE_16   26                 /* FPR starting at position 16 */
+  { 4, 16, S390_OPERAND_FPR | S390_OPERAND_REG_EVEN },
+#define FE_20   27                 /* FPR starting at position 16 */
+  { 4, 16, S390_OPERAND_FPR | S390_OPERAND_REG_EVEN },
+#define FE_24   28                 /* FPR starting at position 24 */
+  { 4, 24, S390_OPERAND_FPR | S390_OPERAND_REG_EVEN },
+#define FE_28   29                 /* FPR starting at position 28 */
+  { 4, 28, S390_OPERAND_FPR | S390_OPERAND_REG_EVEN },
+#define FE_32   30                 /* FPR starting at position 32 */
+  { 4, 32, S390_OPERAND_FPR | S390_OPERAND_REG_EVEN },
+
+
 /* Access register operands.  */
 
-#define A_8    17                 /* Access reg. starting at position 8 */
+#define A_8    31                 /* Access reg. starting at position 8 */
   { 4, 8, S390_OPERAND_AR },
-#define A_12   18                 /* Access reg. starting at position 12 */
+#define A_12   32                 /* Access reg. starting at position 12 */
   { 4, 12, S390_OPERAND_AR },
-#define A_24   19                 /* Access reg. starting at position 24 */
+#define A_24   33                 /* Access reg. starting at position 24 */
   { 4, 24, S390_OPERAND_AR },
-#define A_28   20                 /* Access reg. starting at position 28 */
+#define A_28   34                 /* Access reg. starting at position 28 */
   { 4, 28, S390_OPERAND_AR },
 
 /* Control register operands.  */
 
-#define C_8    21                 /* Control reg. starting at position 8 */
+#define C_8    35                 /* Control reg. starting at position 8 */
   { 4, 8, S390_OPERAND_CR },
-#define C_12   22                 /* Control reg. starting at position 12 */
+#define C_12   36                 /* Control reg. starting at position 12 */
   { 4, 12, S390_OPERAND_CR },
 
 /* Base register operands.  */
 
-#define B_16   23                 /* Base register starting at position 16 */
-  { 4, 16, S390_OPERAND_BASE|S390_OPERAND_GPR },
-#define B_32   24                 /* Base register starting at position 32 */
-  { 4, 32, S390_OPERAND_BASE|S390_OPERAND_GPR },
+#define B_16   37                 /* Base register starting at position 16 */
+  { 4, 16, S390_OPERAND_BASE | S390_OPERAND_GPR },
+#define B_32   38                 /* Base register starting at position 32 */
+  { 4, 32, S390_OPERAND_BASE | S390_OPERAND_GPR },
 
-#define X_12   25                 /* Index register starting at position 12 */
-  { 4, 12, S390_OPERAND_INDEX|S390_OPERAND_GPR },
+#define X_12   39                 /* Index register starting at position 12 */
+  { 4, 12, S390_OPERAND_INDEX | S390_OPERAND_GPR },
 
 /* Address displacement operands.  */
 
-#define D_20   26                 /* Displacement starting at position 20 */
+#define D_20   40                 /* Displacement starting at position 20 */
   { 12, 20, S390_OPERAND_DISP },
-#define DO_20  27                 /* optional Displ. starting at position 20 */
-  { 12, 20, S390_OPERAND_DISP|S390_OPERAND_OPTIONAL },
-#define D_36   28                 /* Displacement starting at position 36 */
+#define DO_20  41                 /* optional Displ. starting at position 20 */
+  { 12, 20, S390_OPERAND_DISP | S390_OPERAND_OPTIONAL },
+#define D_36   42                 /* Displacement starting at position 36 */
   { 12, 36, S390_OPERAND_DISP },
-#define D20_20 29		  /* 20 bit displacement starting at 20 */
-  { 20, 20, S390_OPERAND_DISP|S390_OPERAND_SIGNED },
+#define D20_20 43		  /* 20 bit displacement starting at 20 */
+  { 20, 20, S390_OPERAND_DISP | S390_OPERAND_SIGNED },
 
 /* Length operands.  */
 
-#define L4_8   30                 /* 4 bit length starting at position 8 */
+#define L4_8   44                 /* 4 bit length starting at position 8 */
   { 4, 8, S390_OPERAND_LENGTH },
-#define L4_12  31                 /* 4 bit length starting at position 12 */
+#define L4_12  45                 /* 4 bit length starting at position 12 */
   { 4, 12, S390_OPERAND_LENGTH },
-#define L8_8   32                 /* 8 bit length starting at position 8 */
+#define L8_8   46                 /* 8 bit length starting at position 8 */
   { 8, 8, S390_OPERAND_LENGTH },
 
 /* Signed immediate operands.  */
 
-#define I8_8   33		  /* 8 bit signed value starting at 8 */
+#define I8_8   47		  /* 8 bit signed value starting at 8 */
   { 8, 8, S390_OPERAND_SIGNED },
-#define I8_32  34		  /* 8 bit signed value starting at 32 */
+#define I8_32  48		  /* 8 bit signed value starting at 32 */
   { 8, 32, S390_OPERAND_SIGNED },
-#define I16_16 35                 /* 16 bit signed value starting at 16 */
+#define I16_16 49                 /* 16 bit signed value starting at 16 */
   { 16, 16, S390_OPERAND_SIGNED },
-#define I16_32 36                 /* 16 bit signed value starting at 32 */
+#define I16_32 50                 /* 16 bit signed value starting at 32 */
   { 16, 32, S390_OPERAND_SIGNED },
-#define I32_16 37		  /* 32 bit signed value starting at 16 */
+#define I32_16 51		  /* 32 bit signed value starting at 16 */
   { 32, 16, S390_OPERAND_SIGNED },
 
 /* Unsigned immediate operands.  */
 
-#define U4_8   38                 /* 4 bit unsigned value starting at 8 */
+#define U4_8   52                 /* 4 bit unsigned value starting at 8 */
   { 4, 8, 0 },
-#define U4_12  39                 /* 4 bit unsigned value starting at 12 */
+#define U4_12  53                 /* 4 bit unsigned value starting at 12 */
   { 4, 12, 0 },
-#define U4_16  40                 /* 4 bit unsigned value starting at 16 */
+#define U4_16  54                 /* 4 bit unsigned value starting at 16 */
   { 4, 16, 0 },
-#define U4_20  41                 /* 4 bit unsigned value starting at 20 */
+#define U4_20  55                 /* 4 bit unsigned value starting at 20 */
   { 4, 20, 0 },
-#define U4_32  42                 /* 4 bit unsigned value starting at 32 */
+#define U4_32  56                 /* 4 bit unsigned value starting at 32 */
   { 4, 32, 0 },
-#define U8_8   43                 /* 8 bit unsigned value starting at 8 */
+#define U8_8   57                 /* 8 bit unsigned value starting at 8 */
   { 8, 8, 0 },
-#define U8_16  44                 /* 8 bit unsigned value starting at 16 */
+#define U8_16  58                 /* 8 bit unsigned value starting at 16 */
   { 8, 16, 0 },
-#define U8_24  45                 /* 8 bit unsigned value starting at 24 */
+#define U8_24  59                 /* 8 bit unsigned value starting at 24 */
   { 8, 24, 0 },
-#define U8_32  46                 /* 8 bit unsigned value starting at 32 */
+#define U8_32  60                 /* 8 bit unsigned value starting at 32 */
   { 8, 32, 0 },
-#define U16_16 47                 /* 16 bit unsigned value starting at 16 */
+#define U16_16 61                 /* 16 bit unsigned value starting at 16 */
   { 16, 16, 0 },
-#define U16_32 48		  /* 16 bit unsigned value starting at 32 */
+#define U16_32 62		  /* 16 bit unsigned value starting at 32 */
   { 16, 32, 0 },
-#define U32_16 49		  /* 32 bit unsigned value starting at 16 */
+#define U32_16 63		  /* 32 bit unsigned value starting at 16 */
   { 32, 16, 0 },
 
 /* PC-relative address operands.  */
 
-#define J16_16 50                 /* PC relative jump offset at 16 */
+#define J16_16 64                 /* PC relative jump offset at 16 */
   { 16, 16, S390_OPERAND_PCREL },
-#define J32_16 51                 /* PC relative long offset at 16 */
+#define J32_16 65                 /* PC relative long offset at 16 */
   { 32, 16, S390_OPERAND_PCREL },
 
 /* Conditional mask operands.  */
 
-#define M_16OPT   52              /* 4 bit optional mask starting at 16 */
+#define M_16OPT   66              /* 4 bit optional mask starting at 16 */
   { 4, 16, S390_OPERAND_OPTIONAL },
 
 };
@@ -204,10 +240,13 @@ const struct s390_operand s390_operands[] =
       c - control register
       d - displacement, 12 bit
       f - floating pointer register
+      fe - even numbered floating point register operand
       i - signed integer, 4, 8, 16 or 32 bit
       l - length, 4 or 8 bit
       p - pc relative
       r - general purpose register
+      ro - optional register operand
+      re - even numbered register operand
       u - unsigned integer, 4, 8, 16 or 32 bit
       m - mode field, 4 bit
       0 - operand skipped.
@@ -260,49 +299,78 @@ const struct s390_operand s390_operands[] =
 #define INSTR_RRE_AA     4, { A_24,A_28,0,0,0,0 }              /* e.g. cpya  */
 #define INSTR_RRE_AR     4, { A_24,R_28,0,0,0,0 }              /* e.g. sar   */
 #define INSTR_RRE_F0     4, { F_24,0,0,0,0,0 }                 /* e.g. sqer  */
+#define INSTR_RRE_FE0    4, { FE_24,0,0,0,0,0 }                /* e.g. lzxr  */
 #define INSTR_RRE_FF     4, { F_24,F_28,0,0,0,0 }              /* e.g. debr  */
+#define INSTR_RRE_FEF    4, { FE_24,F_28,0,0,0,0 }             /* e.g. lxdbr */
+#define INSTR_RRE_FFE    4, { F_24,FE_28,0,0,0,0 }             /* e.g. lexr  */
+#define INSTR_RRE_FEFE   4, { FE_24,FE_28,0,0,0,0 }            /* e.g. dxr   */
 #define INSTR_RRE_R0     4, { R_24,0,0,0,0,0 }                 /* e.g. ipm   */
 #define INSTR_RRE_RA     4, { R_24,A_28,0,0,0,0 }              /* e.g. ear   */
 #define INSTR_RRE_RF     4, { R_24,F_28,0,0,0,0 }              /* e.g. cefbr */
+#define INSTR_RRE_RFE    4, { R_24,FE_28,0,0,0,0 }             /* e.g. csxtr */
 #define INSTR_RRE_RR     4, { R_24,R_28,0,0,0,0 }              /* e.g. lura  */
+#define INSTR_RRE_RER    4, { RE_24,R_28,0,0,0,0 }             /* e.g. tre   */
+#define INSTR_RRE_RERE   4, { RE_24,RE_28,0,0,0,0 }            /* e.g. cuse  */
 #define INSTR_RRE_FR     4, { F_24,R_28,0,0,0,0 }              /* e.g. ldgr  */
+#define INSTR_RRE_FER    4, { FE_24,R_28,0,0,0,0 }             /* e.g. cxfbr */
 /* Actually efpc and sfpc do not take an optional operand.
    This is just a workaround for existing code e.g. glibc.  */
 #define INSTR_RRE_RR_OPT 4, { R_24,RO_28,0,0,0,0 }             /* efpc, sfpc */
 #define INSTR_RRF_F0FF   4, { F_16,F_24,F_28,0,0,0 }           /* e.g. madbr */
+#define INSTR_RRF_FE0FF  4, { F_16,F_24,F_28,0,0,0 }           /* e.g. myr */
 #define INSTR_RRF_F0FF2  4, { F_24,F_16,F_28,0,0,0 }           /* e.g. cpsdr */
 #define INSTR_RRF_F0FR   4, { F_24,F_16,R_28,0,0,0 }           /* e.g. iedtr */
+#define INSTR_RRF_FE0FER 4, { FE_24,FE_16,R_28,0,0,0 }         /* e.g. iextr */
 #define INSTR_RRF_FUFF   4, { F_24,F_16,F_28,U4_20,0,0 }       /* e.g. didbr */
+#define INSTR_RRF_FEUFEFE 4, { FE_24,FE_16,FE_28,U4_20,0,0 }   /* e.g. qaxtr */
 #define INSTR_RRF_FUFF2  4, { F_24,F_28,F_16,U4_20,0,0 }       /* e.g. adtra */
+#define INSTR_RRF_FEUFEFE2 4, { FE_24,FE_28,FE_16,U4_20,0,0 }  /* e.g. axtra */
 #define INSTR_RRF_RURR   4, { R_24,R_28,R_16,U4_20,0,0 }       /* e.g. .insn */
 #define INSTR_RRF_R0RR   4, { R_24,R_16,R_28,0,0,0 }           /* e.g. idte  */
 #define INSTR_RRF_R0RR2  4, { R_24,R_28,R_16,0,0,0 }           /* e.g. ark   */
 #define INSTR_RRF_U0FF   4, { F_24,U4_16,F_28,0,0,0 }          /* e.g. fixr  */
+#define INSTR_RRF_U0FEFE 4, { FE_24,U4_16,FE_28,0,0,0 }        /* e.g. fixbr */
 #define INSTR_RRF_U0RF   4, { R_24,U4_16,F_28,0,0,0 }          /* e.g. cfebr */
+#define INSTR_RRF_U0RFE  4, { R_24,U4_16,FE_28,0,0,0 }         /* e.g. cfxbr */
 #define INSTR_RRF_UUFF   4, { F_24,U4_16,F_28,U4_20,0,0 }      /* e.g. fidtr */
+#define INSTR_RRF_UUFFE  4, { F_24,U4_16,FE_28,U4_20,0,0 }     /* e.g. ldxtr */
+#define INSTR_RRF_UUFEFE 4, { FE_24,U4_16,FE_28,U4_20,0,0 }    /* e.g. fixtr */
 #define INSTR_RRF_0UFF   4, { F_24,F_28,U4_20,0,0,0 }          /* e.g. ldetr */
+#define INSTR_RRF_0UFEF  4, { F_24,FE_28,U4_20,0,0,0 }         /* e.g. lxdtr */
 #define INSTR_RRF_FFRU   4, { F_24,F_16,R_28,U4_20,0,0 }       /* e.g. rrdtr */
+#define INSTR_RRF_FEFERU 4, { FE_24,FE_16,R_28,U4_20,0,0 }     /* e.g. rrxtr */
 #define INSTR_RRF_M0RR   4, { R_24,R_28,M_16OPT,0,0,0 }        /* e.g. sske  */
+#define INSTR_RRF_M0RER  4, { RE_24,R_28,M_16OPT,0,0,0 }       /* e.g. trte  */
+#define INSTR_RRF_M0RERE 4, { RE_24,RE_28,M_16OPT,0,0,0 }      /* e.g. troo  */
 #define INSTR_RRF_U0RR   4, { R_24,R_28,U4_16,0,0,0 }          /* e.g. clrt  */
 #define INSTR_RRF_00RR   4, { R_24,R_28,0,0,0,0 }              /* e.g. clrtne */
 #define INSTR_RRF_UUFR   4, { F_24,U4_16,R_28,U4_20,0,0 }      /* e.g. cdgtra */
+#define INSTR_RRF_UUFER  4, { FE_24,U4_16,R_28,U4_20,0,0 }     /* e.g. cxfbra */
 #define INSTR_RRF_UURF   4, { R_24,U4_16,F_28,U4_20,0,0 }      /* e.g. cgdtra */
+#define INSTR_RRF_UURFE  4, { R_24,U4_16,FE_28,U4_20,0,0 }     /* e.g. cfxbra */
 #define INSTR_RR_0R      2, { R_12, 0,0,0,0,0 }                /* e.g. br    */
 #define INSTR_RR_0R_OPT  2, { RO_12, 0,0,0,0,0 }               /* e.g. nopr  */
 #define INSTR_RR_FF      2, { F_8,F_12,0,0,0,0 }               /* e.g. adr   */
+#define INSTR_RR_FEF     2, { FE_8,F_12,0,0,0,0 }              /* e.g. mxdr  */
+#define INSTR_RR_FFE     2, { F_8,FE_12,0,0,0,0 }              /* e.g. ldxr  */
+#define INSTR_RR_FEFE    2, { FE_8,FE_12,0,0,0,0 }             /* e.g. axr   */
 #define INSTR_RR_R0      2, { R_8, 0,0,0,0,0 }                 /* e.g. spm   */
 #define INSTR_RR_RR      2, { R_8,R_12,0,0,0,0 }               /* e.g. lr    */
+#define INSTR_RR_RER     2, { RE_8,R_12,0,0,0,0 }              /* e.g. dr    */
 #define INSTR_RR_U0      2, { U8_8, 0,0,0,0,0 }                /* e.g. svc   */
 #define INSTR_RR_UR      2, { U4_8,R_12,0,0,0,0 }              /* e.g. bcr   */
 #define INSTR_RRR_F0FF   4, { F_24,F_28,F_16,0,0,0 }           /* e.g. ddtr  */
+#define INSTR_RRR_FE0FEFE 4, { FE_24,FE_28,FE_16,0,0,0 }       /* e.g. axtr  */
 #define INSTR_RRS_RRRDU  6, { R_8,R_12,U4_32,D_20,B_16 }       /* e.g. crb   */
 #define INSTR_RRS_RRRD0  6, { R_8,R_12,D_20,B_16,0 }           /* e.g. crbne */
 #define INSTR_RSE_RRRD   6, { R_8,R_12,D_20,B_16,0,0 }         /* e.g. lmh   */
+#define INSTR_RSE_RERERD 6, { RE_8,RE_12,D_20,B_16,0,0 }       /* e.g. mvclu */
 #define INSTR_RSE_CCRD   6, { C_8,C_12,D_20,B_16,0,0 }         /* e.g. lmh   */
 #define INSTR_RSE_RURD   6, { R_8,U4_12,D_20,B_16,0,0 }        /* e.g. icmh  */
 #define INSTR_RSL_R0RD   6, { D_20,L4_8,B_16,0,0,0 }           /* e.g. tp    */
 #define INSTR_RSI_RRP    4, { R_8,R_12,J16_16,0,0,0 }          /* e.g. brxh  */
 #define INSTR_RSY_RRRD   6, { R_8,R_12,D20_20,B_16,0,0 }       /* e.g. stmy  */
+#define INSTR_RSY_RERERD 6, { RE_8,RE_12,D20_20,B_16,0,0 }     /* e.g. cdsy  */
 #define INSTR_RSY_RURD   6, { R_8,U4_12,D20_20,B_16,0,0 }      /* e.g. icmh  */
 #define INSTR_RSY_AARD   6, { A_8,A_12,D20_20,B_16,0,0 }       /* e.g. lamy  */
 #define INSTR_RSY_CCRD   6, { C_8,C_12,D20_20,B_16,0,0 }       /* e.g. lamy  */
@@ -311,19 +379,28 @@ const struct s390_operand s390_operands[] =
 #define INSTR_RS_AARD    4, { A_8,A_12,D_20,B_16,0,0 }         /* e.g. lam   */
 #define INSTR_RS_CCRD    4, { C_8,C_12,D_20,B_16,0,0 }         /* e.g. lctl  */
 #define INSTR_RS_R0RD    4, { R_8,D_20,B_16,0,0,0 }            /* e.g. sll   */
+#define INSTR_RS_RE0RD   4, { RE_8,D_20,B_16,0,0,0 }           /* e.g. slda  */
 #define INSTR_RS_RRRD    4, { R_8,R_12,D_20,B_16,0,0 }         /* e.g. cs    */
+#define INSTR_RS_RERERD  4, { RE_8,RE_12,D_20,B_16,0,0 }       /* e.g. cds   */
 #define INSTR_RS_RURD    4, { R_8,U4_12,D_20,B_16,0,0 }        /* e.g. icm   */
 #define INSTR_RXE_FRRD   6, { F_8,D_20,X_12,B_16,0,0 }         /* e.g. axbr  */
+#define INSTR_RXE_FERRD  6, { FE_8,D_20,X_12,B_16,0,0 }        /* e.g. lxdb  */
 #define INSTR_RXE_RRRD   6, { R_8,D_20,X_12,B_16,0,0 }         /* e.g. lg    */
+#define INSTR_RXE_RERRD  6, { RE_8,D_20,X_12,B_16,0,0 }        /* e.g. dsg   */
 #define INSTR_RXF_FRRDF  6, { F_32,F_8,D_20,X_12,B_16,0 }      /* e.g. madb  */
+#define INSTR_RXF_FRRDFE 6, { FE_32,F_8,D_20,X_12,B_16,0 }     /* e.g. my    */
+#define INSTR_RXF_FERRDFE 6, { FE_32,FE_8,D_20,X_12,B_16,0 }   /* e.g. slxt  */
 #define INSTR_RXF_RRRDR  6, { R_32,R_8,D_20,X_12,B_16,0 }      /* e.g. .insn */
 #define INSTR_RXY_RRRD   6, { R_8,D20_20,X_12,B_16,0,0 }       /* e.g. ly    */
+#define INSTR_RXY_RERRD  6, { RE_8,D20_20,X_12,B_16,0,0 }      /* e.g. dsg   */
 #define INSTR_RXY_FRRD   6, { F_8,D20_20,X_12,B_16,0,0 }       /* e.g. ley   */
 #define INSTR_RXY_URRD   6, { U4_8,D20_20,X_12,B_16,0,0 }      /* e.g. pfd   */
 #define INSTR_RX_0RRD    4, { D_20,X_12,B_16,0,0,0 }           /* e.g. be    */
 #define INSTR_RX_0RRD_OPT 4, { DO_20,X_12,B_16,0,0,0 }         /* e.g. nop   */
 #define INSTR_RX_FRRD    4, { F_8,D_20,X_12,B_16,0,0 }         /* e.g. ae    */
+#define INSTR_RX_FERRD   4, { FE_8,D_20,X_12,B_16,0,0 }        /* e.g. mxd   */
 #define INSTR_RX_RRRD    4, { R_8,D_20,X_12,B_16,0,0 }         /* e.g. l     */
+#define INSTR_RX_RERRD   4, { RE_8,D_20,X_12,B_16,0,0 }        /* e.g. d     */
 #define INSTR_RX_URRD    4, { U4_8,D_20,X_12,B_16,0,0 }        /* e.g. bc    */
 #define INSTR_SI_URD     4, { D_20,B_16,U8_8,0,0,0 }           /* e.g. cli   */
 #define INSTR_SIY_URD    6, { D20_20,B_16,U8_8,0,0,0 }         /* e.g. tmy   */
@@ -339,7 +416,8 @@ const struct s390_operand s390_operands[] =
 #define INSTR_SS_RRRDRD2 6, { R_8,D_20,B_16,R_12,D_36,B_32 }   /* e.g. plo   */
 #define INSTR_SS_RRRDRD3 6, { R_8,R_12,D_20,B_16,D_36,B_32 }   /* e.g. lmd   */
 #define INSTR_SSF_RRDRD  6, { D_20,B_16,D_36,B_32,R_8,0 }      /* e.g. mvcos */
-#define INSTR_SSF_RRDRD2 6, { R_8,D_20,B_16,D_36,B_32,0 }      /* e.g. lpd   */
+#define INSTR_SSF_RRDRD2 6, { R_8,D_20,B_16,D_36,B_32,0 }
+#define INSTR_SSF_RERDRD2 6, { RE_8,D_20,B_16,D_36,B_32,0 }    /* e.g. lpd   */
 #define INSTR_S_00       4, { 0,0,0,0,0,0 }                    /* e.g. hsch  */
 #define INSTR_S_RD       4, { D_20,B_16,0,0,0,0 }              /* e.g. lpsw  */
 
@@ -376,42 +454,70 @@ const struct s390_operand s390_operands[] =
 #define MASK_RRE_AA      { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
 #define MASK_RRE_AR      { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
 #define MASK_RRE_F0      { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 }
+#define MASK_RRE_FE0     { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 }
 #define MASK_RRE_FF      { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
+#define MASK_RRE_FEF     { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
+#define MASK_RRE_FFE     { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
+#define MASK_RRE_FEFE    { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
 #define MASK_RRE_R0      { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 }
 #define MASK_RRE_RA      { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
 #define MASK_RRE_RF      { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
+#define MASK_RRE_RFE     { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
 #define MASK_RRE_RR      { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
+#define MASK_RRE_RER     { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
+#define MASK_RRE_RERE    { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
 #define MASK_RRE_FR      { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
+#define MASK_RRE_FER     { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
 #define MASK_RRE_RR_OPT  { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
 #define MASK_RRF_F0FF    { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
+#define MASK_RRF_FE0FF   { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
 #define MASK_RRF_F0FF2   { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
 #define MASK_RRF_F0FR    { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
+#define MASK_RRF_FE0FER  { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
 #define MASK_RRF_FUFF    { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RRF_FEUFEFE { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RRF_FUFF2   { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RRF_FEUFEFE2 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RRF_RURR    { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RRF_R0RR    { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RRF_R0RR2   { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RRF_U0FF    { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
+#define MASK_RRF_U0FEFE  { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
 #define MASK_RRF_U0RF    { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
+#define MASK_RRF_U0RFE   { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
 #define MASK_RRF_UUFF    { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RRF_UUFFE   { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RRF_UUFEFE  { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RRF_0UFF    { 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00 }
+#define MASK_RRF_0UFEF   { 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00 }
 #define MASK_RRF_FFRU    { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RRF_FEFERU  { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RRF_M0RR    { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
+#define MASK_RRF_M0RER   { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
+#define MASK_RRF_M0RERE  { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
 #define MASK_RRF_U0RR    { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
 #define MASK_RRF_00RR    { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
 #define MASK_RRF_UUFR    { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RRF_UUFER   { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RRF_UURF    { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RRF_UURFE   { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RR_0R       { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RR_0R_OPT   { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RR_FF       { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RR_FEF      { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RR_FFE      { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RR_FEFE     { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RR_R0       { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RR_RR       { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RR_RER      { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RR_U0       { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RR_UR       { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RRR_F0FF    { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
+#define MASK_RRR_FE0FEFE { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
 #define MASK_RRS_RRRDU   { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff }
 #define MASK_RRS_RRRD0   { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff }
 #define MASK_RSE_RRRD    { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff }
+#define MASK_RSE_RERERD  { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff }
 #define MASK_RSE_CCRD    { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff }
 #define MASK_RSE_RURD    { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff }
 #define MASK_RSL_R0RD    { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff }
@@ -419,25 +525,35 @@ const struct s390_operand s390_operands[] =
 #define MASK_RS_AARD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RS_CCRD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RS_R0RD     { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RS_RE0RD    { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RS_RRRD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RS_RERERD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RS_RURD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RSY_RRRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+#define MASK_RSY_RERERD  { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 #define MASK_RSY_RURD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 #define MASK_RSY_AARD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 #define MASK_RSY_CCRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 #define MASK_RSY_RDRM    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 #define MASK_RSY_RDR0    { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff }
 #define MASK_RXE_FRRD    { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff }
+#define MASK_RXE_FERRD   { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff }
 #define MASK_RXE_RRRD    { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff }
+#define MASK_RXE_RERRD   { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff }
 #define MASK_RXF_FRRDF   { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff }
+#define MASK_RXF_FRRDFE  { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff }
+#define MASK_RXF_FERRDFE { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff }
 #define MASK_RXF_RRRDR   { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff }
 #define MASK_RXY_RRRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+#define MASK_RXY_RERRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 #define MASK_RXY_FRRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 #define MASK_RXY_URRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 #define MASK_RX_0RRD     { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RX_0RRD_OPT { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RX_FRRD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RX_FERRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RX_RRRD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RX_RERRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RX_URRD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_SI_URD      { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_SIY_URD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
@@ -454,6 +570,7 @@ const struct s390_operand s390_operands[] =
 #define MASK_SS_RRRDRD3  { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_SSF_RRDRD   { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_SSF_RRDRD2  { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_SSF_RERDRD2 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_S_00        { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 }
 #define MASK_S_RD        { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
 
diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt
index 4aa0da7..e612ca1 100644
--- a/opcodes/s390-opc.txt
+++ b/opcodes/s390-opc.txt
@@ -16,7 +16,7 @@ fa ap SS_LLRDRD "add decimal" g5 esa,zarch
 3e aur RR_FF "add unnormalized (short)" g5 esa,zarch
 6e aw RX_FRRD "add unnormalized (long)" g5 esa,zarch
 2e awr RR_FF "add unnormalized (long)" g5 esa,zarch
-36 axr RR_FF "add normalized" g5 esa,zarch
+36 axr RR_FEFE "add normalized" g5 esa,zarch
 b240 bakr RRE_RR "branch and stack" g5 esa,zarch
 45 bal RX_RRRD "branch and link" g5 esa,zarch
 05 balr RR_RR "branch and link" g5 esa,zarch
@@ -34,7 +34,7 @@ b258 bsg RRE_RR "branch in subspace group" g5 esa,zarch
 59 c RX_RRRD "compare" g5 esa,zarch
 69 cd RX_FRRD "compare (long)" g5 esa,zarch
 29 cdr RR_FF "compare (long)" g5 esa,zarch
-bb cds RS_RRRD "compare double and swap" g5 esa,zarch
+bb cds RS_RERERD "compare double and swap" g5 esa,zarch
 79 ce RX_FRRD "compare (short)" g5 esa,zarch
 39 cer RR_FF "compare (short)" g5 esa,zarch
 b21a cfc S_RD "compare and form codeword" g5 esa,zarch
@@ -51,19 +51,19 @@ b24d cpya RRE_AA "copy access" g5 esa,zarch
 19 cr RR_RR "compare" g5 esa,zarch
 ba cs RS_RRRD "compare and swap" g5 esa,zarch
 b230 csch S_00 "clear subchannel" g5 esa,zarch
-b257 cuse RRE_RR "compare until substring equal" g5 esa,zarch
+b257 cuse RRE_RERE "compare until substring equal" g5 esa,zarch
 b250 csp RRE_RR "compare and swap and purge" g5 esa,zarch
 4f cvb RX_RRRD "convert to binary" g5 esa,zarch
 4e cvd RX_RRRD "convert to decimal" g5 esa,zarch
-5d d RX_RRRD "divide" g5 esa,zarch
+5d d RX_RERRD "divide" g5 esa,zarch
 6d dd RX_FRRD "divide (long)" g5 esa,zarch
 2d ddr RR_FF "divide (long)" g5 esa,zarch
 7d de RX_FRRD "divide (short)" g5 esa,zarch
 3d der RR_FF "divide (short)" g5 esa,zarch
 83 diag RS_RRRD "diagnose" g5 esa,zarch
 fd dp SS_LLRDRD "divide decimal" g5 esa,zarch
-1d dr RR_RR "divide" g5 esa,zarch
-b22d dxr RRE_FF "divide (ext.)" g5 esa,zarch
+1d dr RR_RER "divide" g5 esa,zarch
+b22d dxr RRE_FEFE "divide (ext.)" g5 esa,zarch
 b24f ear RRE_RA "extract access" g5 esa,zarch
 de ed SS_L0RDRD "edit" g5 esa,zarch
 df edmk SS_L0RDRD "edit and mark" g5 esa,zarch
@@ -107,15 +107,15 @@ b7 lctl RS_CCRD "load control" g5 esa,zarch
 82 lpsw S_RD "load PSW" g5 esa,zarch
 18 lr RR_RR "load" g5 esa,zarch
 b1 lra RX_RRRD "load real address" g5 esa,zarch
-25 ldxr RR_FF "load rounded (ext. to long)" g5 esa,zarch
-25 lrdr RR_FF "load rounded (ext. to long)" g5 esa,zarch
+25 ldxr RR_FFE "load rounded (ext. to long)" g5 esa,zarch
+25 lrdr RR_FFE "load rounded (ext. to long)" g5 esa,zarch
 35 ledr RR_FF "load rounded (long to short)" g5 esa,zarch
 35 lrer RR_FF "load rounded (long to short)" g5 esa,zarch
 22 ltdr RR_FF "load and test (long)" g5 esa,zarch
 32 lter RR_FF "load and test (short)" g5 esa,zarch
 12 ltr RR_RR "load and test" g5 esa,zarch
 b24b lura RRE_RR "load using real address" g5 esa,zarch
-5c m RX_RRRD "multiply" g5 esa,zarch
+5c m RX_RERRD "multiply" g5 esa,zarch
 af mc SI_URD "monitor call" g5 esa,zarch
 6c md RX_FRRD "multiply (long)" g5 esa,zarch
 2c mdr RR_FF "multiply (long)" g5 esa,zarch
@@ -125,7 +125,7 @@ af mc SI_URD "monitor call" g5 esa,zarch
 3c mer RR_FF "multiply (short to long)" g5 esa,zarch
 4c mh RX_RRRD "multiply halfword" g5 esa,zarch
 fc mp SS_LLRDRD "multiply decimal" g5 esa,zarch
-1c mr RR_RR "multiply" g5 esa,zarch
+1c mr RR_RER "multiply" g5 esa,zarch
 b232 msch S_RD "modify subchannel" g5 esa,zarch
 b247 msta RRE_R0 "modify stacked state" g5 esa,zarch
 d2 mvc SS_L0RDRD "move" g5 esa,zarch
@@ -142,9 +142,9 @@ f1 mvo SS_LLRDRD "move with offset" g5 esa,zarch
 b254 mvpg RRE_RR "move page" g5 esa,zarch
 b255 mvst RRE_RR "move string" g5 esa,zarch
 d3 mvz SS_L0RDRD "move zones" g5 esa,zarch
-67 mxd RX_FRRD "multiply (long to ext.)" g5 esa,zarch
-27 mxdr RR_FF "multiply (long to ext.)" g5 esa,zarch
-26 mxr RR_FF "multiply (ext.)" g5 esa,zarch
+67 mxd RX_FERRD "multiply (long to ext.)" g5 esa,zarch
+27 mxdr RR_FEF "multiply (long to ext.)" g5 esa,zarch
+26 mxr RR_FEFE "multiply (ext.)" g5 esa,zarch
 54 n RX_RRRD "AND" g5 esa,zarch
 d4 nc SS_L0RDRD "AND" g5 esa,zarch
 94 ni SI_URD "AND" g5 esa,zarch
@@ -179,8 +179,8 @@ b214 sie S_RD "start interpretive execution" g5 esa,zarch
 ae sigp RS_RRRD "signal processor" g5 esa,zarch
 5f sl RX_RRRD "subtract logical" g5 esa,zarch
 8b sla RS_R0RD "shift left single" g5 esa,zarch
-8f slda RS_R0RD "shift left double (long)" g5 esa,zarch
-8d sldl RS_R0RD "shift left double logical (long)" g5 esa,zarch
+8f slda RS_RE0RD "shift left double (long)" g5 esa,zarch
+8d sldl RS_RE0RD "shift left double logical (long)" g5 esa,zarch
 89 sll RS_R0RD "shift left single logical" g5 esa,zarch
 1f slr RR_RR "subtract logical" g5 esa,zarch
 fb sp SS_LLRDRD "subtract decimal" g5 esa,zarch
@@ -192,8 +192,8 @@ b244 sqdr RRE_FF "square root (long)" g5 esa,zarch
 b245 sqer RRE_FF "square root (short)" g5 esa,zarch
 1b sr RR_RR "subtract" g5 esa,zarch
 8a sra RS_R0RD "shift right single" g5 esa,zarch
-8e srda RS_R0RD "shift right double (long)" g5 esa,zarch
-8c srdl RS_R0RD "shift right double logical (long)" g5 esa,zarch
+8e srda RS_RE0RD "shift right double (long)" g5 esa,zarch
+8c srdl RS_RE0RD "shift right double logical (long)" g5 esa,zarch
 88 srl RS_R0RD "shift right single logical" g5 esa,zarch
 f0 srp SS_LIRDRD "shift and round decimal" g5 esa,zarch
 b25e srst RRE_RR "search string" g5 esa,zarch
@@ -227,7 +227,7 @@ b246 stura RRE_RR "store using real address" g5 esa,zarch
 0a svc RR_U0 "supervisor call" g5 esa,zarch
 6f sw RX_FRRD "subtract unnormalized (long)" g5 esa,zarch
 2f swr RR_FF "subtract unnormalized (long)" g5 esa,zarch
-37 sxr RR_FF "subtract normalized (ext.)" g5 esa,zarch
+37 sxr RR_FEFE "subtract normalized (ext.)" g5 esa,zarch
 b24c tar RRE_AR "test access" g5 esa,zarch
 b22c tb RRE_0R "test block" g5 esa,zarch
 91 tm SI_URD "test under mask" g5 esa,zarch
@@ -255,7 +255,7 @@ b241 cksm RRE_RR "checksum" g5 esa,zarch
 a70e chi RI_RI "compare halfword immediate" g5 esa,zarch
 a9 clcle RS_RRRD "compare logical long extended" g5 esa,zarch
 a708 lhi RI_RI "load halfword immediate" g5 esa,zarch
-a8 mvcle RS_RRRD "move long extended" g5 esa,zarch
+a8 mvcle RS_RERERD "move long extended" g5 esa,zarch
 a70c mhi RI_RI "multiply halfword immediate" g5 esa,zarch
 b252 msr RRE_RR "multiply single" g5 esa,zarch
 71 ms RX_RRRD "multiply single" g5 esa,zarch
@@ -271,12 +271,12 @@ a701 tml RI_RU "test under mask low" g5 esa,zarch
 47f0 b RX_0RRD "unconditional branch" g5 esa,zarch
 a704 j*8 RI_0P "conditional jump" g5 esa,zarch
 a7f4 j RI_0P "unconditional jump" g5 esa,zarch
-b34a axbr RRE_FF "add extended bfp" g5 esa,zarch
+b34a axbr RRE_FEFE "add extended bfp" g5 esa,zarch
 b31a adbr RRE_FF "add long bfp" g5 esa,zarch
 ed000000001a adb RXE_FRRD "add long bfp" g5 esa,zarch
 b30a aebr RRE_FF "add short bfp" g5 esa,zarch
 ed000000000a aeb RXE_FRRD "add short bfp" g5 esa,zarch
-b349 cxbr RRE_FF "compare extended bfp" g5 esa,zarch
+b349 cxbr RRE_FEFE "compare extended bfp" g5 esa,zarch
 b319 cdbr RRE_FF "compare long bfp" g5 esa,zarch
 ed0000000019 cdb RXE_FRRD "compare long bfp" g5 esa,zarch
 b309 cebr RRE_FF "compare short bfp" g5 esa,zarch
@@ -286,13 +286,13 @@ b318 kdbr RRE_FF "compare and signal long bfp" g5 esa,zarch
 ed0000000018 kdb RXE_FRRD "compare and signal long bfp" g5 esa,zarch
 b308 kebr RRE_FF "compare and signal short bfp" g5 esa,zarch
 ed0000000008 keb RXE_FRRD "compare and signal short bfp" g5 esa,zarch
-b396 cxfbr RRE_FR "convert from fixed 32 to extended bfp" g5 esa,zarch
+b396 cxfbr RRE_FER "convert from fixed 32 to extended bfp" g5 esa,zarch
 b395 cdfbr RRE_FR "convert from fixed 32 to long bfp" g5 esa,zarch
 b394 cefbr RRE_FR "convert from fixed 32 to short bfp" g5 esa,zarch
-b39a cfxbr RRF_U0RF "convert to fixed extended bfp to 32" g5 esa,zarch
+b39a cfxbr RRF_U0RFE "convert to fixed extended bfp to 32" g5 esa,zarch
 b399 cfdbr RRF_U0RF "convert to fixed long bfp to 32" g5 esa,zarch
 b398 cfebr RRF_U0RF "convert to fixed short bfp to 32" g5 esa,zarch
-b34d dxbr RRE_FF "divide extended bfp" g5 esa,zarch
+b34d dxbr RRE_FEFE "divide extended bfp" g5 esa,zarch
 b31d ddbr RRE_FF "divide long bfp" g5 esa,zarch
 ed000000001d ddb RXE_FRRD "divide long bfp" g5 esa,zarch
 b30d debr RRE_FF "divide short bfp" g5 esa,zarch
@@ -300,36 +300,36 @@ ed000000000d deb RXE_FRRD "divide short bfp" g5 esa,zarch
 b35b didbr RRF_FUFF "divide to integer long bfp" g5 esa,zarch
 b353 diebr RRF_FUFF "divide to integer short bfp" g5 esa,zarch
 b38c efpc RRE_RR_OPT "extract fpc" g5 esa,zarch
-b342 ltxbr RRE_FF "load and test extended bfp" g5 esa,zarch
+b342 ltxbr RRE_FEFE "load and test extended bfp" g5 esa,zarch
 b312 ltdbr RRE_FF "load and test long bfp" g5 esa,zarch
 b302 ltebr RRE_FF "load and test short bfp" g5 esa,zarch
-b343 lcxbr RRE_FF "load complement extended bfp" g5 esa,zarch
+b343 lcxbr RRE_FEFE "load complement extended bfp" g5 esa,zarch
 b313 lcdbr RRE_FF "load complement long bfp" g5 esa,zarch
 b303 lcebr RRE_FF "load complement short bfp" g5 esa,zarch
-b347 fixbr RRF_U0FF "load fp integer extended bfp" g5 esa,zarch
+b347 fixbr RRF_U0FEFE "load fp integer extended bfp" g5 esa,zarch
 b35f fidbr RRF_U0FF "load fp integer long bfp" g5 esa,zarch
 b357 fiebr RRF_U0FF "load fp integer short bfp" g5 esa,zarch
 b29d lfpc S_RD "load fpc" g5 esa,zarch
-b305 lxdbr RRE_FF "load lengthened long to extended bfp" g5 esa,zarch
-ed0000000005 lxdb RXE_FRRD "load lengthened long to extended bfp" g5 esa,zarch
-b306 lxebr RRE_FF "load lengthened short to extended bfp" g5 esa,zarch
-ed0000000006 lxeb RXE_FRRD "load lengthened short to extended bfp" g5 esa,zarch
+b305 lxdbr RRE_FEF "load lengthened long to extended bfp" g5 esa,zarch
+ed0000000005 lxdb RXE_FERRD "load lengthened long to extended bfp" g5 esa,zarch
+b306 lxebr RRE_FEF "load lengthened short to extended bfp" g5 esa,zarch
+ed0000000006 lxeb RXE_FERRD "load lengthened short to extended bfp" g5 esa,zarch
 b304 ldebr RRE_FF "load lengthened short to long bfp" g5 esa,zarch
 ed0000000004 ldeb RXE_FRRD "load lengthened short to long bfp" g5 esa,zarch
-b341 lnxbr RRE_FF "load negative extended bfp" g5 esa,zarch
+b341 lnxbr RRE_FEFE "load negative extended bfp" g5 esa,zarch
 b311 lndbr RRE_FF "load negative long bfp" g5 esa,zarch
 b301 lnebr RRE_FF "load negative short bfp" g5 esa,zarch
-b340 lpxbr RRE_FF "load positive extended bfp" g5 esa,zarch
+b340 lpxbr RRE_FEFE "load positive extended bfp" g5 esa,zarch
 b310 lpdbr RRE_FF "load positive long bfp" g5 esa,zarch
 b300 lpebr RRE_FF "load positive short bfp" g5 esa,zarch
-b345 ldxbr RRE_FF "load rounded extended to long bfp" g5 esa,zarch
-b346 lexbr RRE_FF "load rounded extended to short bfp" g5 esa,zarch
+b345 ldxbr RRE_FEFE "load rounded extended to long bfp" g5 esa,zarch
+b346 lexbr RRE_FEFE "load rounded extended to short bfp" g5 esa,zarch
 b344 ledbr RRE_FF "load rounded long to short bfp" g5 esa,zarch
-b34c mxbr RRE_FF "multiply extended bfp" g5 esa,zarch
+b34c mxbr RRE_FEFE "multiply extended bfp" g5 esa,zarch
 b31c mdbr RRE_FF "multiply long bfp" g5 esa,zarch
 ed000000001c mdb RXE_FRRD "multiply long bfp" g5 esa,zarch
-b307 mxdbr RRE_FF "multiply long to extended bfp" g5 esa,zarch
-ed0000000007 mxdb RXE_FRRD "multiply long to extended bfp" g5 esa,zarch
+b307 mxdbr RRE_FEF "multiply long to extended bfp" g5 esa,zarch
+ed0000000007 mxdb RXE_FERRD "multiply long to extended bfp" g5 esa,zarch
 b317 meebr RRE_FF "multiply short bfp" g5 esa,zarch
 ed0000000017 meeb RXE_FRRD "multiply short bfp" g5 esa,zarch
 b30c mdebr RRE_FF "multiply short to long bfp" g5 esa,zarch
@@ -344,22 +344,22 @@ b30f msebr RRF_F0FF "multiply and subtract short bfp" g5 esa,zarch
 ed000000000f mseb RXF_FRRDF "multiply and subtract short bfp" g5 esa,zarch
 b384 sfpc RRE_RR_OPT "set fpc" g5 esa,zarch
 b299 srnm S_RD "set rounding mode" g5 esa,zarch
-b316 sqxbr RRE_FF "square root extended bfp" g5 esa,zarch
+b316 sqxbr RRE_FEFE "square root extended bfp" g5 esa,zarch
 b315 sqdbr RRE_FF "square root long bfp" g5 esa,zarch
 ed0000000015 sqdb RXE_FRRD "square root long bfp" g5 esa,zarch
 b314 sqebr RRE_FF "square root short bfp" g5 esa,zarch
 ed0000000014 sqeb RXE_FRRD "square root short bfp" g5 esa,zarch
 b29c stfpc S_RD "store fpc" g5 esa,zarch
-b34b sxbr RRE_FF "subtract extended bfp" g5 esa,zarch
+b34b sxbr RRE_FEFE "subtract extended bfp" g5 esa,zarch
 b31b sdbr RRE_FF "subtract long bfp" g5 esa,zarch
 ed000000001b sdb RXE_FRRD "subtract long bfp" g5 esa,zarch
 b30b sebr RRE_FF "subtract short bfp" g5 esa,zarch
 ed000000000b seb RXE_FRRD "subtract short bfp" g5 esa,zarch
-ed0000000012 tcxb RXE_FRRD "test data class extended bfp" g5 esa,zarch
+ed0000000012 tcxb RXE_FERRD "test data class extended bfp" g5 esa,zarch
 ed0000000011 tcdb RXE_FRRD "test data class long bfp" g5 esa,zarch
 ed0000000010 tceb RXE_FRRD "test data class short bfp" g5 esa,zarch
 b274 siga S_RD "signal adapter" g5 esa,zarch
-b2a6 cuutf RRE_RR "convert unicode to utf-8" g5 esa,zarch
+b2a6 cuutf RRE_RERE "convert unicode to utf-8" g5 esa,zarch
 b2a7 cutfu RRE_RR "convert utf-8 to unicode" g5 esa,zarch
 ee plo SS_RRRDRD2 "perform locked operation" g5 esa,zarch
 b25a bsa RRE_RR "branch and set authority" g5 esa,zarch
@@ -369,14 +369,14 @@ b27d stsi S_RD "store system information" g5 esa,zarch
 01ff trap2 E "trap" g5 esa,zarch
 b2ff trap4 S_RD "trap4" g5 esa,zarch
 b278 stcke S_RD "store clock extended" g5 esa,zarch
-b2a5 tre RRE_RR "translate extended" g5 esa,zarch
-eb000000008e mvclu RSE_RRRD "move long unicode" g5 esa,zarch
+b2a5 tre RRE_RER "translate extended" g5 esa,zarch
+eb000000008e mvclu RSE_RERERD "move long unicode" g5 esa,zarch
 e9 pka SS_L2RDRD "pack ascii" g5 esa,zarch
 e1 pku SS_L0RDRD "pack unicode" g5 esa,zarch
-b993 troo RRE_RR "translate one to one" g5 esa,zarch
-b992 trot RRE_RR "translate one to two" g5 esa,zarch
-b991 trto RRE_RR "translate two to one" g5 esa,zarch
-b990 trtt RRE_RR "translate two to two" g5 esa,zarch
+b993 troo RRE_RER "translate one to one" g5 esa,zarch
+b992 trot RRE_RER "translate one to two" g5 esa,zarch
+b991 trto RRE_RER "translate two to one" g5 esa,zarch
+b990 trtt RRE_RER "translate two to two" g5 esa,zarch
 ea unpka SS_L0RDRD "unpack ascii" g5 esa,zarch
 e2 unpku SS_L0RDRD "unpack unicode" g5 esa,zarch
 b358 thder RRE_FF "convert short bfp to long hfp" g5 esa,zarch
@@ -385,7 +385,7 @@ b350 tbedr RRF_U0FF "convert long hfp to short bfp" g5 esa,zarch
 b351 tbdr RRF_U0FF "convert long hfp to long bfp" g5 esa,zarch
 b374 lzer RRE_F0 "load short zero" g5 esa,zarch
 b375 lzdr RRE_F0 "load long zero" g5 esa,zarch
-b376 lzxr RRE_F0 "load extended zero" g5 esa,zarch
+b376 lzxr RRE_FE0 "load extended zero" g5 esa,zarch
 # Here are the new esame instructions:
 b946 bctgr RRE_RR "branch on count 64" z900 zarch
 b900 lpgr RRE_RR "load positive 64" z900 zarch
@@ -456,7 +456,7 @@ e50000000002 strag SSE_RDRD "store read address" z900 zarch
 eb0000000025 stctg RSE_CCRD "store control 64" z900 zarch
 eb000000002f lctlg RSE_CCRD "load control 64" z900 zarch
 eb0000000030 csg RSE_RRRD "compare and swap 64" z900 zarch
-eb000000003e cdsg RSE_RRRD "compare double and swap 64" z900 zarch
+eb000000003e cdsg RSE_RERERD "compare double and swap 64" z900 zarch
 eb0000000020 clmh RSE_RURD "compare logical characters under mask high" z900 zarch
 eb000000002c stcmh RSE_RURD "store characters under mask high" z900 zarch
 eb0000000080 icmh RSE_RURD "insert characters under mask high" z900 zarch
@@ -478,16 +478,16 @@ b90c msgr RRE_RR "multiply single 64" z900 zarch
 b91c msgfr RRE_RR "multiply single 64<32" z900 zarch
 b3a4 cegbr RRE_FR "convert from fixed 64 to short bfp" z900 zarch
 b3a5 cdgbr RRE_FR "convert from fixed 64 to long bfp" z900 zarch
-b3a6 cxgbr RRE_FR "convert from fixed 64 to extended bfp" z900 zarch
+b3a6 cxgbr RRE_FER "convert from fixed 64 to extended bfp" z900 zarch
 b3a8 cgebr RRF_U0RF "convert to fixed short bfd to 64" z900 zarch
 b3a9 cgdbr RRF_U0RF "convert to fixed long bfp to 64" z900 zarch
-b3aa cgxbr RRF_U0RF "convert to fixed extended bfp to 64" z900 zarch
+b3aa cgxbr RRF_U0RFE "convert to fixed extended bfp to 64" z900 zarch
 b3c4 cegr RRE_FR "convert from fixed 64 to short hfp" z900 zarch
 b3c5 cdgr RRE_FR "convert from fixed 64 to long hfp" z900 zarch
-b3c6 cxgr RRE_FR "convert from fixed 64 to extended hfp" z900 zarch
+b3c6 cxgr RRE_FER "convert from fixed 64 to extended hfp" z900 zarch
 b3c8 cger RRF_U0RF "convert to fixed short hfp to 64" z900 zarch
 b3c9 cgdr RRF_U0RF "convert to fixed long hfp to 64" z900 zarch
-b3ca cgxr RRF_U0RF "convert to fixed extended hfp to 64" z900 zarch
+b3ca cgxr RRF_U0RFE "convert to fixed extended hfp to 64" z900 zarch
 010b tam E "test addressing mode" z900 esa,zarch
 010c sam24 E "set addressing mode 24" z900 esa,zarch
 010d sam31 E "set addressing mode 31" z900 esa,zarch
@@ -510,41 +510,41 @@ a50e llilh RI_RU "load logical immediate low high" z900 zarch
 a50f llill RI_RU "load logical immediate low low" z900 zarch
 b2b1 stfl S_RD "store facility list" z900 esa,zarch
 b2b2 lpswe S_RD "load psw extended" z900 zarch
-b90d dsgr RRE_RR "divide single 64" z900 zarch
+b90d dsgr RRE_RER "divide single 64" z900 zarch
 b90f lrvgr RRE_RR "load reversed 64" z900 zarch
 b916 llgfr RRE_RR "load logical 64<32" z900 zarch
 b917 llgtr RRE_RR "load logical thirty one bits" z900 zarch
-b91d dsgfr RRE_RR "divide single 64<32" z900 zarch
+b91d dsgfr RRE_RER "divide single 64<32" z900 zarch
 b91f lrvr RRE_RR "load reversed 32" z900 esa,zarch
-b986 mlgr RRE_RR "multiply logical 64" z900 zarch
-b987 dlgr RRE_RR "divide logical 64" z900 zarch
+b986 mlgr RRE_RER "multiply logical 64" z900 zarch
+b987 dlgr RRE_RER "divide logical 64" z900 zarch
 b988 alcgr RRE_RR "add logical with carry 64" z900 zarch
 b989 slbgr RRE_RR "subtract logical with borrow 64" z900 zarch
 b98d epsw RRE_RR "extract psw" z900 esa,zarch
-b996 mlr RRE_RR "multiply logical 32" z900 esa,zarch
-b997 dlr RRE_RR "divide logical 32" z900 esa,zarch
+b996 mlr RRE_RER "multiply logical 32" z900 esa,zarch
+b997 dlr RRE_RER "divide logical 32" z900 esa,zarch
 b998 alcr RRE_RR "add logical with carry 32" z900 esa,zarch
 b999 slbr RRE_RR "subtract logical with borrow 32" z900 esa,zarch
 b99d esea RRE_R0 "extract and set extended authority" z900 zarch
 c000 larl RIL_RP "load address relative long" z900 esa,zarch
-e3000000000d dsg RXE_RRRD "divide single 64" z900 zarch
+e3000000000d dsg RXE_RERRD "divide single 64" z900 zarch
 e3000000000f lrvg RXE_RRRD "load reversed 64" z900 zarch
 e30000000016 llgf RXE_RRRD "load logical 64<32" z900 zarch
 e30000000017 llgt RXE_RRRD "load logical thirty one bits" z900 zarch
-e3000000001d dsgf RXE_RRRD "divide single 64<32" z900 zarch
+e3000000001d dsgf RXE_RERRD "divide single 64<32" z900 zarch
 e3000000001e lrv RXE_RRRD "load reversed 32" z900 esa,zarch
 e3000000001f lrvh RXE_RRRD "load reversed 16" z900 esa,zarch
 e3000000002f strvg RXE_RRRD "store reversed 64" z900 zarch
 e3000000003e strv RXE_RRRD "store reversed 32" z900 esa,zarch
 e3000000003f strvh RXE_RRRD "store reversed 64" z900 esa,zarch
-e30000000086 mlg RXE_RRRD "multiply logical 64" z900 zarch
-e30000000087 dlg RXE_RRRD "divide logical 64" z900 zarch
+e30000000086 mlg RXE_RERRD "multiply logical 64" z900 zarch
+e30000000087 dlg RXE_RERRD "divide logical 64" z900 zarch
 e30000000088 alcg RXE_RRRD "add logical with carry 64" z900 zarch
 e30000000089 slbg RXE_RRRD "subtract logical with borrow 64" z900 zarch
 e3000000008e stpq RXE_RRRD "store pair to quadword" z900 zarch
-e3000000008f lpq RXE_RRRD "load pair from quadword" z900 zarch
-e30000000096 ml RXE_RRRD "multiply logical 32" z900 esa,zarch
-e30000000097 dl RXE_RRRD "divide logical 32" z900 esa,zarch
+e3000000008f lpq RXE_RERRD "load pair from quadword" z900 zarch
+e30000000096 ml RXE_RERRD "multiply logical 32" z900 esa,zarch
+e30000000097 dl RXE_RERRD "divide logical 32" z900 esa,zarch
 e30000000098 alc RXE_RRRD "add logical with carry 32" z900 esa,zarch
 e30000000099 slb RXE_RRRD "subtract logical with borrow 32" z900 esa,zarch
 e30000000090 llgc RXE_RRRD "load logical character" z900 zarch
@@ -552,34 +552,34 @@ e30000000091 llgh RXE_RRRD "load logical halfword" z900 zarch
 eb000000001c rllg RSE_RRRD "rotate left single logical 64" z900 zarch
 eb000000001d rll RSE_RRRD "rotate left single logical 32" z900 esa,zarch
 b369 cxr RRE_FF "compare extended hfp" g5 esa,zarch
-b3b6 cxfr RRE_FR "convert from fixed 32 to extended hfp" g5 esa,zarch
+b3b6 cxfr RRE_FER "convert from fixed 32 to extended hfp" g5 esa,zarch
 b3b5 cdfr RRE_FR "convert from fixed 32 to long hfp" g5 esa,zarch
 b3b4 cefr RRE_FR "convert from fixed 32 to short hfp" g5 esa,zarch
-b3ba cfxr RRF_U0RF "convert to fixed extended hfp to 32" g5 esa,zarch
+b3ba cfxr RRF_U0RFE "convert to fixed extended hfp to 32" g5 esa,zarch
 b3b9 cfdr RRF_U0RF "convert to fixed long hfp to 32" g5 esa,zarch
 b3b8 cfer RRF_U0RF "convert to fixed short hfp to 32" g5 esa,zarch
-b362 ltxr RRE_FF "load and test extended hfp" g5 esa,zarch
-b363 lcxr RRE_FF "load complement extended hfp" g5 esa,zarch
-b367 fixr RRE_FF "load fp integer extended hfp" g5 esa,zarch
+b362 ltxr RRE_FEFE "load and test extended hfp" g5 esa,zarch
+b363 lcxr RRE_FEFE "load complement extended hfp" g5 esa,zarch
+b367 fixr RRE_FEFE "load fp integer extended hfp" g5 esa,zarch
 b37f fidr RRE_FF "load fp integer long hfp" g5 esa,zarch
 b377 fier RRE_FF "load fp integer short hfp" g5 esa,zarch
-b325 lxdr RRE_FF "load lengthened long to extended hfp" g5 esa,zarch
-ed0000000025 lxd RXE_FRRD "load lengthened long to extended hfp" g5 esa,zarch
-b326 lxer RRE_FF "load lengthened short to extended hfp" g5 esa,zarch
-ed0000000026 lxe RXE_FRRD "load lengthened short to extended hfp" g5 esa,zarch
+b325 lxdr RRE_FEF "load lengthened long to extended hfp" g5 esa,zarch
+ed0000000025 lxd RXE_FERRD "load lengthened long to extended hfp" g5 esa,zarch
+b326 lxer RRE_FEF "load lengthened short to extended hfp" g5 esa,zarch
+ed0000000026 lxe RXE_FERRD "load lengthened short to extended hfp" g5 esa,zarch
 b324 lder RRE_FF "load lengthened short to long hfp" g5 esa,zarch
 ed0000000024 lde RXE_FRRD "load lengthened short to long hfp" g5 esa,zarch
-b361 lnxr RRE_FF "load negative long hfp" g5 esa,zarch
-b360 lpxr RRE_FF "load positive long hfp" g5 esa,zarch
-b366 lexr RRE_FF "load rounded extended to short hfp" g5 esa,zarch
+b361 lnxr RRE_FEFE "load negative extended hfp" g5 esa,zarch
+b360 lpxr RRE_FEFE "load positive extended hfp" g5 esa,zarch
+b366 lexr RRE_FFE "load rounded extended to short hfp" g5 esa,zarch
 b337 meer RRE_FF "multiply short hfp" g5 esa,zarch
 ed0000000037 mee RXE_FRRD "multiply short hfp" g5 esa,zarch
-b336 sqxr RRE_FF "square root extended hfp" g5 esa,zarch
+b336 sqxr RRE_FEFE "square root extended hfp" g5 esa,zarch
 ed0000000034 sqe RXE_FRRD "square root short hfp" g5 esa,zarch
 ed0000000035 sqd RXE_FRRD "square root long hfp" g5 esa,zarch
 b263 cmpsc RRE_RR "compression call" g5 esa,zarch
 eb00000000c0 tp RSL_R0RD "test decimal" g5 esa,zarch
-b365 lxr RRE_FF "load extended fp" g5 esa,zarch
+b365 lxr RRE_FEFE "load extended fp" g5 esa,zarch
 b22e pgin RRE_RR "page in" g5 esa,zarch
 b22f pgout RRE_RR "page out" g5 esa,zarch
 b276 xsch S_00 "cancel subchannel" g5 esa,zarch
@@ -591,7 +591,7 @@ eb0000000054 niy SIY_URD "and immediate with long offset" z990 zarch
 e30000000054 ny RXY_RRRD "and with long offset" z990 zarch
 e30000000059 cy RXY_RRRD "compare with long offset" z990 zarch
 eb0000000014 csy RSY_RRRD "compare and swap with long offset" z990 zarch
-eb0000000031 cdsy RSY_RRRD "compare double and swap with long offset" z990 zarch
+eb0000000031 cdsy RSY_RERERD "compare double and swap with long offset" z990 zarch
 e30000000079 chy RXY_RRRD "compare halfword with long offset" z990 zarch
 e30000000055 cly RXY_RRRD "compare logical with long offset" z990 zarch
 eb0000000055 cliy SIY_URD "compare logical immediate with long offset" z990 zarch
@@ -637,7 +637,7 @@ e30000000009 sg RXY_RRRD "subtract with long offset 64" z990 zarch
 e3000000000a alg RXY_RRRD "add logical with long offset 64" z990 zarch
 e3000000000b slg RXY_RRRD "subtract logical with long offset 64" z990 zarch
 e3000000000c msg RXY_RRRD "multiply single with long offset 64" z990 zarch
-e3000000000d dsg RXY_RRRD "divide single 64" z990 zarch
+e3000000000d dsg RXY_RERRD "divide single 64" z990 zarch
 e3000000000e cvbg RXY_RRRD "convert to binary with long offset 64" z990 zarch
 e3000000000f lrvg RXY_RRRD "load reversed 64" z990 zarch
 e30000000014 lgf RXY_RRRD "load 64<32" z990 zarch
@@ -649,7 +649,7 @@ e30000000019 sgf RXY_RRRD "subtract with long offset 64<32" z990 zarch
 e3000000001a algf RXY_RRRD "add logical with long offset 64<32" z990 zarch
 e3000000001b slgf RXY_RRRD "subtract logical with long offset 64<32" z990 zarch
 e3000000001c msgf RXY_RRRD "multiply single with long offset 64<32" z990 zarch
-e3000000001d dsgf RXY_RRRD "divide single 64<32" z990 zarch
+e3000000001d dsgf RXY_RERRD "divide single 64<32" z990 zarch
 e3000000001e lrv RXY_RRRD "load reversed 32" z990 esa,zarch
 e3000000001f lrvh RXY_RRRD "load reversed 16" z990 esa,zarch
 e30000000020 cg RXY_RRRD "compare with long offset 64" z990 zarch
@@ -665,16 +665,16 @@ e30000000046 bctg RXY_RRRD "branch on count 64" z990 zarch
 e30000000080 ng RXY_RRRD "and with long offset 64" z990 zarch
 e30000000081 og RXY_RRRD "or with long offset 64" z990 zarch
 e30000000082 xg RXY_RRRD "exclusive or with long offset 64" z990 zarch
-e30000000086 mlg RXY_RRRD "multiply logical 64" z990 zarch
-e30000000087 dlg RXY_RRRD "divide logical 64" z990 zarch
+e30000000086 mlg RXY_RERRD "multiply logical 64" z990 zarch
+e30000000087 dlg RXY_RERRD "divide logical 64" z990 zarch
 e30000000088 alcg RXY_RRRD "add logical with carry 64" z990 zarch
 e30000000089 slbg RXY_RRRD "subtract logical with borrow 64" z990 zarch
 e3000000008e stpq RXY_RRRD "store pair to quadword" z990 zarch
-e3000000008f lpq RXY_RRRD "load pair from quadword" z990 zarch
+e3000000008f lpq RXY_RERRD "load pair from quadword" z990 zarch
 e30000000090 llgc RXY_RRRD "load logical character" z990 zarch
 e30000000091 llgh RXY_RRRD "load logical halfword" z990 zarch
-e30000000096 ml RXY_RRRD "multiply logical 32" z990 esa,zarch
-e30000000097 dl RXY_RRRD "divide logical 32" z990 esa,zarch
+e30000000096 ml RXY_RERRD "multiply logical 32" z990 esa,zarch
+e30000000097 dl RXY_RERRD "divide logical 32" z990 esa,zarch
 e30000000098 alc RXY_RRRD "add logical with carry 32" z990 esa,zarch
 e30000000099 slb RXY_RRRD "subtract logical with borrow 32" z990 esa,zarch
 eb0000000004 lmg RSY_RRRD "load multiple with long offset 64" z990 zarch
@@ -692,11 +692,11 @@ eb0000000026 stmh RSY_RRRD "store multiple high" z990 zarch
 eb000000002c stcmh RSY_RURD "store characters under mask high with long offset" z990 zarch
 eb000000002f lctlg RSY_CCRD "load control 64" z990 zarch
 eb0000000030 csg RSY_RRRD "compare and swap with long offset 64" z990 zarch
-eb000000003e cdsg RSY_RRRD "compare double and swap with long offset 64" z990 zarch
+eb000000003e cdsg RSY_RERERD "compare double and swap with long offset 64" z990 zarch
 eb0000000044 bxhg RSY_RRRD "branch on index high 64" z990 zarch
 eb0000000045 bxleg RSY_RRRD "branch on index low or equal 64" z990 zarch
 eb0000000080 icmh RSY_RURD "insert characters under mask high with long offset" z990 zarch
-eb000000008e mvclu RSY_RRRD "move long unicode" z990 esa,zarch
+eb000000008e mvclu RSY_RERERD "move long unicode" z990 esa,zarch
 eb000000008f clclu RSY_RRRD "compare logical long unicode with long offset" z990 esa,zarch
 eb0000000096 lmh RSY_RRRD "load multiple high" z990 zarch
 # new z990 instructions
@@ -763,26 +763,26 @@ b9aa lptea RRF_RURR "load page-table-entry address" z9-109 zarch
 # z9-109 conditional sske facility, sske instruction entered twice
 b22b sske RRF_M0RR "set storage key extended" z9-109 zarch
 # z9-109 etf2-enhancement facility, instructions entered twice
-b993 troo RRF_M0RR "translate one to one" z9-109 esa,zarch
-b992 trot RRF_M0RR "translate one to two" z9-109 esa,zarch
-b991 trto RRF_M0RR "translate two to one" z9-109 esa,zarch
-b990 trtt RRF_M0RR "translate two to two" z9-109 esa,zarch
+b993 troo RRF_M0RERE "translate one to one" z9-109 esa,zarch
+b992 trot RRF_M0RERE "translate one to two" z9-109 esa,zarch
+b991 trto RRF_M0RERE "translate two to one" z9-109 esa,zarch
+b990 trtt RRF_M0RERE "translate two to two" z9-109 esa,zarch
 # z9-109 etf3-enhancement facility, some instructions entered twice
-b9b1 cu24 RRF_M0RR "convert utf-16 to utf-32" z9-109 zarch
-b2a6 cu21 RRF_M0RR "convert utf-16 to utf-8" z9-109 zarch
-b2a6 cuutf RRF_M0RR "convert unicode to utf-8" z9-109 zarch
-b9b3 cu42 RRE_RR "convert utf-32 to utf-16" z9-109 zarch
-b9b2 cu41 RRE_RR "convert utf-32 to utf-8" z9-109 zarch
-b2a7 cu12 RRF_M0RR "convert utf-8 to utf-16" z9-109 zarch
-b2a7 cutfu RRF_M0RR "convert utf-8 to unicode" z9-109 zarch
-b9b0 cu14 RRF_M0RR "convert utf-8 to utf-32" z9-109 zarch
+b9b1 cu24 RRF_M0RERE "convert utf-16 to utf-32" z9-109 zarch
+b2a6 cu21 RRF_M0RERE "convert utf-16 to utf-8" z9-109 zarch
+b2a6 cuutf RRF_M0RERE "convert unicode to utf-8" z9-109 zarch
+b9b3 cu42 RRE_RERE "convert utf-32 to utf-16" z9-109 zarch
+b9b2 cu41 RRE_RERE "convert utf-32 to utf-8" z9-109 zarch
+b2a7 cu12 RRF_M0RERE "convert utf-8 to utf-16" z9-109 zarch
+b2a7 cutfu RRF_M0RERE "convert utf-8 to unicode" z9-109 zarch
+b9b0 cu14 RRF_M0RERE "convert utf-8 to utf-32" z9-109 zarch
 b9eb srstu RRE_RR "search string unicode" z9-109 zarch
 d0 trtr SS_L0RDRD "tranlate and test reverse" z9-109 zarch
 # z9-109 unnormalized hfp multiply & multiply and add
-b33b myr RRF_F0FF "multiply unnormalized long hfp" z9-109 zarch
+b33b myr RRF_FE0FF "multiply unnormalized long hfp" z9-109 zarch
 b33d myhr RRF_F0FF "multiply unnormalized long hfp high" z9-109 zarch
 b339 mylr RRF_F0FF "multiply unnormalized long hfp low" z9-109 zarch
-ed000000003b my RXF_FRRDF "multiply unnormalized long hfp" z9-109 zarch
+ed000000003b my RXF_FRRDFE "multiply unnormalized long hfp" z9-109 zarch
 ed000000003d myh RXF_FRRDF "multiply unnormalized long hfp high" z9-109 zarch
 ed0000000039 myl RXF_FRRDF "multiply unnormalized long hfp low" z9-109 zarch
 b33a mayr RRF_F0FF "multiply and add unnormalized long hfp" z9-109 zarch
@@ -798,62 +798,62 @@ b373 lcdfr RRE_FF "load complement no cc" z9-ec zarch
 b3c1 ldgr RRE_FR "load fpr from gr" z9-ec zarch
 b3cd lgdr RRE_RF "load gr from fpr" z9-ec zarch
 b3d2 adtr RRR_F0FF "add long dfp" z9-ec zarch
-b3da axtr RRR_F0FF "add extended dfp" z9-ec zarch
+b3da axtr RRR_FE0FEFE "add extended dfp" z9-ec zarch
 b3e4 cdtr RRE_FF "compare long dfp" z9-ec zarch
-b3ec cxtr RRE_FF "compare extended dfp" z9-ec zarch
+b3ec cxtr RRE_FEFE "compare extended dfp" z9-ec zarch
 b3e0 kdtr RRE_FF "compare and signal long dfp" z9-ec zarch
 b3e8 kxtr RRE_FF "compare and signal extended dfp" z9-ec zarch
 b3f4 cedtr RRE_FF "compare exponent long dfp" z9-ec zarch
-b3fc cextr RRE_FF "compare exponent extended dfp" z9-ec zarch
+b3fc cextr RRE_FEFE "compare exponent extended dfp" z9-ec zarch
 b3f1 cdgtr RRE_FR "convert from fixed long dfp" z9-ec zarch
-b3f9 cxgtr RRE_FR "convert from fixed extended dfp" z9-ec zarch
+b3f9 cxgtr RRE_FER "convert from fixed extended dfp" z9-ec zarch
 b3f3 cdstr RRE_FR "convert from signed bcd long dfp" z9-ec zarch
 b3fb cxstr RRE_FR "convert from signed bcd extended dfp" z9-ec zarch
 b3f2 cdutr RRE_FR "convert from unsigned bcd to long dfp" z9-ec zarch
-b3fa cxutr RRE_FR "convert from unsigned bcd to extended dfp" z9-ec zarch
+b3fa cxutr RRE_FER "convert from unsigned bcd to extended dfp" z9-ec zarch
 b3e1 cgdtr RRF_U0RF "convert from long dfp to fixed" z9-ec zarch
-b3e9 cgxtr RRF_U0RF "convert from extended dfp to fixed" z9-ec zarch
+b3e9 cgxtr RRF_U0RFE "convert from extended dfp to fixed" z9-ec zarch
 b3e3 csdtr RRE_RF "convert from long dfp to signed bcd" z9-ec zarch
-b3eb csxtr RRE_RF "convert from extended dfp to signed bcd" z9-ec zarch
+b3eb csxtr RRE_RFE "convert from extended dfp to signed bcd" z9-ec zarch
 b3e2 cudtr RRE_RF "convert from long dfp to unsigned bcd" z9-ec zarch
-b3ea cuxtr RRE_RF "convert from extended dfp to unsigned bcd" z9-ec zarch
+b3ea cuxtr RRE_RFE "convert from extended dfp to unsigned bcd" z9-ec zarch
 b3d1 ddtr RRR_F0FF "divide long dfp" z9-ec zarch
-b3d9 dxtr RRR_F0FF "divide extended dfp" z9-ec zarch
+b3d9 dxtr RRR_FE0FEFE "divide extended dfp" z9-ec zarch
 b3e5 eedtr RRE_RF "extract biased exponent from long dfp" z9-ec zarch
-b3ed eextr RRE_RF "extract biased exponent from extended dfp" z9-ec zarch
+b3ed eextr RRE_RFE "extract biased exponent from extended dfp" z9-ec zarch
 b3e7 esdtr RRE_RF "extract significance from long dfp" z9-ec zarch
-b3ef esxtr RRE_RF "extract significance from extended dfp" z9-ec zarch
+b3ef esxtr RRE_RFE "extract significance from extended dfp" z9-ec zarch
 b3f6 iedtr RRF_F0FR "insert biased exponent long dfp" z9-ec zarch
-b3fe iextr RRF_F0FR "insert biased exponent extended dfp" z9-ec zarch
+b3fe iextr RRF_FE0FER "insert biased exponent extended dfp" z9-ec zarch
 b3d6 ltdtr RRE_FF "load and test long dfp" z9-ec zarch
-b3de ltxtr RRE_FF "load and test extended dfp" z9-ec zarch
+b3de ltxtr RRE_FEFE "load and test extended dfp" z9-ec zarch
 b3d7 fidtr RRF_UUFF "load fp integer long dfp" z9-ec zarch
-b3df fixtr RRF_UUFF "load fp integer extended dfp" z9-ec zarch
+b3df fixtr RRF_UUFEFE "load fp integer extended dfp" z9-ec zarch
 b2bd lfas S_RD "load fpd and signal" z9-ec zarch
 b3d4 ldetr RRF_0UFF "load lengthened long dfp" z9-ec zarch
-b3dc lxdtr RRF_0UFF "load lengthened extended dfp" z9-ec zarch
+b3dc lxdtr RRF_0UFEF "load lengthened extended dfp" z9-ec zarch
 b3d5 ledtr RRF_UUFF "load rounded long dfp" z9-ec zarch
-b3dd ldxtr RRF_UUFF "load rounded extended dfp" z9-ec zarch
+b3dd ldxtr RRF_UUFFE "load rounded extended dfp" z9-ec zarch
 b3d0 mdtr RRR_F0FF "multiply long dfp" z9-ec zarch
-b3d8 mxtr RRR_F0FF "multiply extended dfp" z9-ec zarch
+b3d8 mxtr RRR_FE0FEFE "multiply extended dfp" z9-ec zarch
 b3f5 qadtr RRF_FUFF "Quantize long dfp" z9-ec zarch
-b3fd qaxtr RRF_FUFF "Quantize extended dfp" z9-ec zarch
+b3fd qaxtr RRF_FEUFEFE "Quantize extended dfp" z9-ec zarch
 b3f7 rrdtr RRF_FFRU "Reround long dfp" z9-ec zarch
-b3ff rrxtr RRF_FFRU "Reround extended dfp" z9-ec zarch
+b3ff rrxtr RRF_FEFERU "Reround extended dfp" z9-ec zarch
 b2b9 srnmt S_RD "set rounding mode dfp" z9-ec zarch
 b385 sfasr RRE_R0 "set fpc and signal" z9-ec zarch
 ed0000000040 sldt RXF_FRRDF "shift coefficient left long dfp" z9-ec zarch
-ed0000000048 slxt RXF_FRRDF "shift coefficient left extended dfp" z9-ec zarch
+ed0000000048 slxt RXF_FERRDFE "shift coefficient left extended dfp" z9-ec zarch
 ed0000000041 srdt RXF_FRRDF "shift coefficient right long dfp" z9-ec zarch
-ed0000000049 srxt RXF_FRRDF "shift coefficient right extended dfp" z9-ec zarch
+ed0000000049 srxt RXF_FERRDFE "shift coefficient right extended dfp" z9-ec zarch
 b3d3 sdtr RRR_F0FF "subtract long dfp" z9-ec zarch
-b3db sxtr RRR_F0FF "subtract extended dfp" z9-ec zarch
+b3db sxtr RRR_FE0FEFE "subtract extended dfp" z9-ec zarch
 ed0000000050 tdcet RXE_FRRD "test data class short dfp" z9-ec zarch
 ed0000000054 tdcdt RXE_FRRD "test data class long dfp" z9-ec zarch
-ed0000000058 tdcxt RXE_FRRD "test data class extended dfp" z9-ec zarch
+ed0000000058 tdcxt RXE_FERRD "test data class extended dfp" z9-ec zarch
 ed0000000051 tdget RXE_FRRD "test data group short dfp" z9-ec zarch
 ed0000000055 tdgdt RXE_FRRD "test data group long dfp" z9-ec zarch
-ed0000000059 tdgxt RXE_FRRD "test data group extended dfp" z9-ec zarch
+ed0000000059 tdgxt RXE_FERRD "test data group extended dfp" z9-ec zarch
 010a pfpo E "perform floating point operation" z9-ec zarch
 c801 ectg SSF_RRDRD "extract cpu time" z9-ec zarch
 c802 csst SSF_RRDRD "compare and swap and store" z9-ec zarch
@@ -941,7 +941,7 @@ c406 llghrl RIL_RP "load logical halfword relative long (64<16)" z10 zarch
 e544 mvhhi SIL_RDI "move (16<16)" z10 zarch
 e54c mvhi SIL_RDI "move (32<16)" z10 zarch
 e548 mvghi SIL_RDI "move (64<16)" z10 zarch
-e3000000005c mfy RXY_RRRD "multiply" z10 zarch
+e3000000005c mfy RXY_RERRD "multiply" z10 zarch
 e3000000007c mhy RXY_RRRD "multiply halfword" z10 zarch
 c201 msfi RIL_RI "multiply single immediate (32)" z10 zarch
 c200 msgfi RIL_RI "multiply single immediate (64)" z10 zarch
@@ -958,8 +958,8 @@ c600 exrl RIL_RP "execute relative long" z10 zarch
 af00 mc SI_URD "monitor call" z10 zarch
 b9a2 ptf RRE_R0 "perform topology function" z10 zarch
 b9af pfmf RRE_RR "perform frame management function" z10 zarch
-b9bf trte RRF_M0RR "translate and test extended" z10 zarch
-b9bd trtre RRF_M0RR "translate and test reverse extended" z10 zarch
+b9bf trte RRF_M0RER "translate and test extended" z10 zarch
+b9bd trtre RRF_M0RER "translate and test reverse extended" z10 zarch
 b9c8 ahhhr RRF_R0RR2 "add high high" z196 zarch
 b9d8 ahhlr RRF_R0RR2 "add high low" z196 zarch
 cc08 aih RIL_RI "add immediate high" z196 zarch
@@ -1000,8 +1000,8 @@ eb00000000f7 lax RSY_RRRD "load and exclusive or 32 bit" z196 zarch
 eb00000000e7 laxg RSY_RRRD "load and exclusive or 64 bit" z196 zarch
 eb00000000f6 lao RSY_RRRD "load and or 32 bit" z196 zarch
 eb00000000e6 laog RSY_RRRD "load and or 64 bit" z196 zarch
-c804 lpd SSF_RRDRD2 "load pair disjoint 32 bit" z196 zarch
-c805 lpdg SSF_RRDRD2 "load pair disjoint 64 bit" z196 zarch
+c804 lpd SSF_RERDRD2 "load pair disjoint 32 bit" z196 zarch
+c805 lpdg SSF_RERDRD2 "load pair disjoint 64 bit" z196 zarch
 b9f2 locr RRF_U0RR "load on condition 32 bit" z196 zarch
 b9f200000000 locr*16 RRF_00RR "load on condition 32 bit" z196 zarch
 b9e2 locgr RRF_U0RR "load on condition 64  bit" z196 zarch
@@ -1040,56 +1040,56 @@ b9e1 popcnt RRE_RR "population count" z196 zarch
 b9ae rrbm RRE_RR "reset reference bits multiple" z196 zarch
 b394 cefbra RRF_UUFR "convert from 32 bit fixed to short bfp with rounding mode" z196 zarch
 b395 cdfbra RRF_UUFR "convert from 32 bit fixed to long bfp with rounding mode" z196 zarch
-b396 cxfbra RRF_UUFR "convert from 32 bit fixed to extended bfp with rounding mode" z196 zarch
+b396 cxfbra RRF_UUFER "convert from 32 bit fixed to extended bfp with rounding mode" z196 zarch
 b3a4 cegbra RRF_UUFR "convert from 64 bit fixed to short bfp with rounding mode" z196 zarch
 b3a5 cdgbra RRF_UUFR "convert from 64 bit fixed to long bfp with rounding mode" z196 zarch
-b3a6 cxgbra RRF_UUFR "convert from 64 bit fixed to extended bfp with rounding mode" z196 zarch
+b3a6 cxgbra RRF_UUFER "convert from 64 bit fixed to extended bfp with rounding mode" z196 zarch
 b390 celfbr RRF_UUFR "convert from 32 bit logical fixed to short bfp with rounding mode" z196 zarch
 b391 cdlfbr RRF_UUFR "convert from 32 bit logical fixed to long bfp with rounding mode" z196 zarch
-b392 cxlfbr RRF_UUFR "convert from 32 bit logical fixed to extended bfp with rounding mode" z196 zarch
+b392 cxlfbr RRF_UUFER "convert from 32 bit logical fixed to extended bfp with rounding mode" z196 zarch
 b3a0 celgbr RRF_UUFR "convert from 64 bit logical fixed to short bfp with rounding mode" z196 zarch
 b3a1 cdlgbr RRF_UUFR "convert from 64 bit logical fixed to long bfp with rounding mode" z196 zarch
-b3a2 cxlgbr RRF_UUFR "convert from 64 bit logical fixed to extended bfp with rounding mode" z196 zarch
+b3a2 cxlgbr RRF_UUFER "convert from 64 bit logical fixed to extended bfp with rounding mode" z196 zarch
 b398 cfebra RRF_UURF "convert to 32 bit fixed from short bfp with rounding mode" z196 zarch
 b399 cfdbra RRF_UURF "convert to 32 bit fixed from long bfp with rounding mode" z196 zarch
-b39a cfxbra RRF_UURF "convert to 32 bit fixed from extended bfp with rounding mode" z196 zarch
+b39a cfxbra RRF_UURFE "convert to 32 bit fixed from extended bfp with rounding mode" z196 zarch
 b3a8 cgebra RRF_UURF "convert to 64 bit fixed from short bfp with rounding mode" z196 zarch
 b3a9 cgdbra RRF_UURF "convert to 64 bit fixed from long bfp with rounding mode" z196 zarch
-b3aa cgxbra RRF_UURF "convert to 64 bit fixed from extended bfp with rounding mode" z196 zarch
+b3aa cgxbra RRF_UURFE "convert to 64 bit fixed from extended bfp with rounding mode" z196 zarch
 b39c clfebr RRF_UURF "convert to 32 bit fixed logical from short bfp with rounding mode" z196 zarch
 b39d clfdbr RRF_UURF "convert to 32 bit fixed logical from long bfp with rounding mode" z196 zarch
-b39e clfxbr RRF_UURF "convert to 32 bit fixed logical from extended bfp with rounding mode" z196 zarch
+b39e clfxbr RRF_UURFE "convert to 32 bit fixed logical from extended bfp with rounding mode" z196 zarch
 b3ac clgebr RRF_UURF "convert to 64 bit fixed logical from short bfp with rounding mode" z196 zarch
 b3ad clgdbr RRF_UURF "convert to 64 bit fixed logical from long bfp with rounding mode" z196 zarch
-b3ae clgxbr RRF_UURF "convert to 64 bit fixed logical from extended bfp with rounding mode" z196 zarch
+b3ae clgxbr RRF_UURFE "convert to 64 bit fixed logical from extended bfp with rounding mode" z196 zarch
 b357 fiebra RRF_UUFF "load fp integer short bfp with rounding mode" z196 zarch
 b35f fidbra RRF_UUFF "load fp integer long bfp with rounding mode" z196 zarch
-b347 fixbra RRF_UUFF "load fp integer extended bfp with rounding mode" z196 zarch
+b347 fixbra RRF_UUFEFE "load fp integer extended bfp with rounding mode" z196 zarch
 b344 ledbra RRF_UUFF "load rounded short/long bfp to short/long bfp with rounding mode" z196 zarch
-b345 ldxbra RRF_UUFF "load rounded long/extended bfp to long/extended bfp with rounding mode" z196 zarch
-b346 lexbra RRF_UUFF "load rounded short/extended bfp to short/extended bfp with rounding mode" z196 zarch
+b345 ldxbra RRF_UUFEFE "load rounded long/extended bfp to long/extended bfp with rounding mode" z196 zarch
+b346 lexbra RRF_UUFEFE "load rounded short/extended bfp to short/extended bfp with rounding mode" z196 zarch
 b3d2 adtra RRF_FUFF2 "add long dfp with rounding mode" z196 zarch
-b3da axtra RRF_FUFF2 "add extended dfp with rounding mode" z196 zarch
+b3da axtra RRF_FEUFEFE2 "add extended dfp with rounding mode" z196 zarch
 b3f1 cdgtra RRF_UUFR "convert from fixed long dfp with rounding mode" z196 zarch
 b951 cdftr RRF_UUFR "convert from 32 bit fixed to long dfp with rounding mode" z196 zarch
-b959 cxftr RRF_UUFR "convert from 32 bit fixed to extended dfp with rounding mode" z196 zarch
-b3f9 cxgtra RRF_UUFR "convert from fixed extended dfp with rounding mode" z196 zarch
+b959 cxftr RRF_UUFER "convert from 32 bit fixed to extended dfp with rounding mode" z196 zarch
+b3f9 cxgtra RRF_UUFER "convert from fixed extended dfp with rounding mode" z196 zarch
 b952 cdlgtr RRF_UUFR "convert from 64 bit fixed logical to long dfp with rounding mode" z196 zarch
-b95a cxlgtr RRF_UUFR "convert from 64 bit fixed logical to extended dfp with rounding mode" z196 zarch
+b95a cxlgtr RRF_UUFER "convert from 64 bit fixed logical to extended dfp with rounding mode" z196 zarch
 b953 cdlftr RRF_UUFR "convert from 32 bit fixed logical to long dfp with rounding mode" z196 zarch
 b95b cxlftr RRF_UUFR "convert from 32 bit fixed logical to extended dfp with rounding mode" z196 zarch
 b3e1 cgdtra RRF_UURF "convert to 64 bit fixed from long dfp with rounding mode" z196 zarch
-b3e9 cgxtra RRF_UURF "convert to 64 bit fixed from extended dfp with rounding mode" z196 zarch
+b3e9 cgxtra RRF_UURFE "convert to 64 bit fixed from extended dfp with rounding mode" z196 zarch
 b941 cfdtr RRF_UURF "convert to 32 bit fixed from long dfp source with rounding mode" z196 zarch
 b949 cfxtr RRF_UURF "convert to 32 bit fixed from extended dfp source with rounding mode" z196 zarch
 b942 clgdtr RRF_UURF "convert to 64 bit fixed logical from long dfp with rounding mode" z196 zarch
-b94a clgxtr RRF_UURF "convert to 64 bit fixed logical from extended dfp with rounding mode" z196 zarch
+b94a clgxtr RRF_UURFE "convert to 64 bit fixed logical from extended dfp with rounding mode" z196 zarch
 b943 clfdtr RRF_UURF "convert to 32 bit fixed logical from long dfp with rounding mode" z196 zarch
-b94b clfxtr RRF_UURF "convert to 32 bit fixed logical from extended dfp with rounding mode" z196 zarch
+b94b clfxtr RRF_UURFE "convert to 32 bit fixed logical from extended dfp with rounding mode" z196 zarch
 b3d1 ddtra RRF_FUFF2 "divide long dfp with rounding mode" z196 zarch
-b3d9 dxtra RRF_FUFF2 "divide extended dfp with rounding mode" z196 zarch
+b3d9 dxtra RRF_FEUFEFE2 "divide extended dfp with rounding mode" z196 zarch
 b3d0 mdtra RRF_FUFF2 "multiply long dfp with rounding mode" z196 zarch
-b3d8 mxtra RRF_FUFF2 "multiply extended dfp with rounding mode" z196 zarch
+b3d8 mxtra RRF_FEUFEFE2 "multiply extended dfp with rounding mode" z196 zarch
 b3d3 sdtra RRF_FUFF2 "subtract long dfp with rounding mode" z196 zarch
-b3db sxtra RRF_FUFF2 "subtract extended dfp with rounding mode" z196 zarch
+b3db sxtra RRF_FEUFEFE2 "subtract extended dfp with rounding mode" z196 zarch
 b2b8 srnmb S_RD "set 3 bit bfp rounding mode" z196 zarch