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| author | Alexandre Oliva <aoliva@redhat.com> | 2001-12-04 10:06:50 +0000 |
|---|---|---|
| committer | Alexandre Oliva <aoliva@redhat.com> | 2001-12-04 10:06:50 +0000 |
| commit | 41852a32f7b4eb242d80ff3ab8efd70dc8bb95b1 (patch) | |
| tree | 0b201636bf2e503a42072d261f115cb4679a81ea /opcodes | |
| parent | 124ddbb22fd2037ebebe4a1835e537692b70d00f (diff) | |
| download | gdb-41852a32f7b4eb242d80ff3ab8efd70dc8bb95b1.zip gdb-41852a32f7b4eb242d80ff3ab8efd70dc8bb95b1.tar.gz gdb-41852a32f7b4eb242d80ff3ab8efd70dc8bb95b1.tar.bz2 | |
* d10v-opc.c (RSRC_NOSP): New macro.
(d10v_operands): Add it.
(d10v_opcodes): Use RSRC_NOSP in post-decrement "st" and "st2w".
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 6 | ||||
| -rw-r--r-- | opcodes/d10v-opc.c | 8 |
2 files changed, 11 insertions, 3 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index ce35c88..c710d32 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,9 @@ +2001-12-04 Alexandre Oliva <aoliva@redhat.com> + + * d10v-opc.c (RSRC_NOSP): New macro. + (d10v_operands): Add it. + (d10v_opcodes): Use RSRC_NOSP in post-decrement "st" and "st2w". + 2001-11-29 Alexandre Oliva <aoliva@redhat.com> * d10v-opc.c (d10v_predefined_registers): Mark `sp' as OPERAND_SP. diff --git a/opcodes/d10v-opc.c b/opcodes/d10v-opc.c index 683db06..d254f00 100644 --- a/opcodes/d10v-opc.c +++ b/opcodes/d10v-opc.c @@ -102,7 +102,9 @@ const struct d10v_operand d10v_operands[] = { 4, 1, OPERAND_GPR|OPERAND_REG }, #define RSRC_SP (RSRC + 1) { 4, 1, OPERAND_SP|OPERAND_GPR|OPERAND_REG }, -#define RDST (RSRC_SP + 1) +#define RSRC_NOSP (RSRC_SP + 1) + { 4, 1, OPERAND_NOSP|OPERAND_GPR|OPERAND_REG }, +#define RDST (RSRC_NOSP + 1) { 4, 5, OPERAND_DEST|OPERAND_GPR|OPERAND_REG }, #define ASRC (RDST + 1) { 1, 4, OPERAND_ACC0|OPERAND_ACC1|OPERAND_REG }, @@ -315,13 +317,13 @@ const struct d10v_opcode d10v_opcodes[] = { { "st", SHORT_2, 1, MU, PAR|WMEM, 0x6800, 0x7e01, { RSRC2, ATSIGN, RSRC } }, { "st", SHORT_2, 1, MU, PAR|WMEM, 0x6c1f, 0x7e1f, { RSRC2, ATMINUS, RSRC_SP } }, { "st", SHORT_2, 1, MU, PAR|WMEM, 0x6801, 0x7e01, { RSRC2, ATSIGN, RSRC, PLUS } }, - { "st", SHORT_2, 1, MU, PAR|WMEM, 0x6c01, 0x7e01, { RSRC2, ATSIGN, RSRC, MINUS } }, + { "st", SHORT_2, 1, MU, PAR|WMEM, 0x6c01, 0x7e01, { RSRC2, ATSIGN, RSRC_NOSP, MINUS } }, { "st", LONG_L, 1, MU, SEQ, 0x36010000, 0x3f0f0000, { RSRC2, ATSIGN, NUM16 } }, { "st2w", LONG_L, 1, MU, SEQ, 0x35000000, 0x3f100000, { RSRC2E, ATPAR, NUM16, RSRC } }, { "st2w", SHORT_2, 1, MU, PAR|WMEM, 0x6a00, 0x7e21, { RSRC2E, ATSIGN, RSRC } }, { "st2w", SHORT_2, 1, MU, PAR|WMEM, 0x6e1f, 0x7e3f, { RSRC2E, ATMINUS, RSRC_SP } }, { "st2w", SHORT_2, 1, MU, PAR|WMEM, 0x6a01, 0x7e21, { RSRC2E, ATSIGN, RSRC, PLUS } }, - { "st2w", SHORT_2, 1, MU, PAR|WMEM, 0x6e01, 0x7e21, { RSRC2E, ATSIGN, RSRC, MINUS } }, + { "st2w", SHORT_2, 1, MU, PAR|WMEM, 0x6e01, 0x7e21, { RSRC2E, ATSIGN, RSRC_NOSP, MINUS } }, { "st2w", LONG_L, 1, MU, SEQ, 0x37010000, 0x3f1f0000, { RSRC2E, ATSIGN, NUM16 } }, { "stb", LONG_L, 1, MU, SEQ, 0x3c000000, 0x3f000000, { RSRC2, ATPAR, NUM16, RSRC } }, { "stb", SHORT_2, 1, MU, PAR|WMEM, 0x7800, 0x7e01, { RSRC2, ATSIGN, RSRC } }, |