* fr30-opc.c: Regenerate.

Plus remove fr30 sanitization.

5 files changed, 131 insertions, 158 deletions

diff --git a/opcodes/.Sanitize b/opcodes/.Sanitize
index b167231..a51c122 100644
--- a/opcodes/.Sanitize
+++ b/opcodes/.Sanitize
@@ -23,14 +23,6 @@ else
 	lose_these_too="${cygnus_files} ${lose_these_too}"
 fi
 
-fr30_files="fr30-opc.h fr30-opc.c fr30-asm.c fr30-dis.c"
-
-if ( echo $* | grep keep\-fr30 > /dev/null ) ; then
-	keep_these_too="${fr30_files} ${keep_these_too}"
-else
-	lose_these_too="${fr30_files} ${lose_these_too}"
-fi
-
 tic80_files="tic80-opc.c tic80-dis.c"
 
 if ( echo $* | grep keep\-tic80 > /dev/null ) ; then
@@ -82,6 +74,10 @@ d30v-opc.c
 dep-in.sed
 dis-buf.c
 disassemble.c
+fr30-asm.c
+fr30-dis.c
+fr30-opc.c
+fr30-opc.h
 h8300-dis.c
 h8500-dis.c
 h8500-opc.h
@@ -433,34 +429,6 @@ else
 	done
 fi
 
-fr30_files="ChangeLog Makefile.in Makefile.am configure.in configure disassemble.c"
-if ( echo $* | grep keep\-fr30 > /dev/null ) ; then
-	for i in $fr30_files ; do
-		if test ! -d $i && (grep sanitize-fr30 $i > /dev/null) ; then
-			if [ -n "${verbose}" ] ; then
-				echo Keeping fr30 stuff in $i
-			fi
-		fi
-	done
-else
-	for i in $fr30_files ; do
-		if test ! -d $i && (grep sanitize-fr30 $i > /dev/null) ; then
-			if [ -n "${verbose}" ] ; then
-				echo Removing traces of \"fr30\" from $i...
-			fi
-			cp $i new
-			sed '/start\-sanitize\-fr30/,/end-\sanitize\-fr30/d' < $i > new
-			if [ -n "${safe}" -a ! -f .Recover/$i ] ; then
-				if [ -n "${verbose}" ] ; then
-					echo Caching $i in .Recover...
-				fi
-				mv $i .Recover
-			fi
-			mv new $i
-		fi
-	done
-fi
-
 coldfire_files="ChangeLog m68k-opc.c"
 if ( echo $* | grep keep\-coldfire > /dev/null ) ; then
 	for i in $coldfire_files ; do
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 5d79373..ded2242 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+1999-01-11  Doug Evans  <devans@casey.cygnus.com>
+
+	* fr30-opc.c: Regenerate.
+
 1999-01-06  Doug Evans  <devans@casey.cygnus.com>
 
 	* m32r-dis.c: Regenerate.
@@ -15,9 +19,7 @@ start-sanitize-cygnus
 	* cgen-asm.in (insert_normal): Use CGEN_BOOL_ATTR.
 	* cgen-asm.in (extract_normal): Ditto.
 end-sanitize-cygnus
-start-sanitize-fr30
 	* fr30-asm.c,fr30-dis.c,fr30-opc.h,fr30-opc.c: Regenerate.
-end-sanitize-fr30
 	* i960c-asm.c,i960c-dis.c,i960c-opc.h,i960c-opc.c: Regenerate.
 	* m32r-asm.c,m32r-dis.c,m32r-opc.h,m32r-opc.c: Regenerate.
 
@@ -29,19 +31,16 @@ end-sanitize-fr30
 
 	* mips16-opc.c: Mark branch insns with MIPS16_INSN_BRANCH.
 
-start-sanitize-fr30
 Wed Dec 16 16:17:49 1998  Dave Brolley  <brolley@cygnus.com>
 
 	* fr30-opc.c: Regenerated.
 
-end-sanitize-fr30
 start-sanitize-vr4xxx
 1998-12-16  Gavin Romig-Koch  <gavin@cygnus.com>
 
 	* mips-dis.c (set_mips_isa_type): Handle bfd_mach_mips4111.
 
 end-sanitize-vr4xxx
-start-sanitize-fr30
 1998-12-15  Dave Brolley  <brolley@cygnus.com>
 
 	* fr30-opc.c,fr30-opc.h: Regenerated.
@@ -50,7 +49,6 @@ start-sanitize-fr30
 
 	* fr30-opc.c,fr30-opc.h: Regenerated.
 
-end-sanitize-fr30
 start-sanitize-vr4xxx
 1998-12-13  Gavin Romig-Koch  <gavin@cygnus.com>
 
@@ -59,12 +57,10 @@ start-sanitize-vr4xxx
 	* mips-opc.c: Add vr4121.
 
 end-sanitize-vr4xxx
-start-sanitize-fr30
 Thu Dec 10 18:39:46 1998  Dave Brolley  <brolley@cygnus.com>
 
 	* fr30-opc.c,fr30-opc.h: Regenerated.
 
-end-sanitize-fr30
 Thu Dec 10 12:49:24 1998  Doug Evans  <devans@canuck.cygnus.com>
 
 	* m32r-opc.c: Regenerate.
@@ -104,12 +100,10 @@ Tue Dec  8 13:56:18 1998  David Taylor  <taylor@texas.cygnus.com>
 	* dis-buf.c (generic_strcat_address): reformat to GNU coding
 	conventions.  change sprintf call to an sprintf_vma call.
 
-start-sanitize-fr30
 Tue Dec  8 13:12:44 1998  Dave Brolley  <brolley@cygnus.com>
 
 	* fr30-asm.c,fr30-dis.c,fr30-opc.c,fr30-opc.h: Regenerated.
 
-end-sanitize-fr30
 Tue Dec  8 10:50:46 1998  David Taylor  <taylor@texas.cygnus.com>
 
 	The following changes were made by
@@ -160,12 +154,10 @@ end-sanitize-cygnus
 	* i960-dis.c (print_insn_i960): Rename to print_insn_i960_orig.
 	* i960c-asm.c, i960c-dis.c, i960c-opc.c, i960c-opc.h: New files.
 	
-start-sanitize-fr30
 Mon Dec  7 14:33:44 1998  Dave Brolley  <brolley@cygnus.com>
 
 	* fr30-asm.c,fr30-dis.c,fr30-opc.c,fr30-opc.h: Regenerated.
 
-end-sanitize-fr30
 Sun Dec  6 14:06:48 1998  Ian Lance Taylor  <ian@cygnus.com>
 
 	* mips-opc.c (mips_builtin_opcodes): Add dmfc2 and dmtc2.
@@ -173,7 +165,6 @@ Sun Dec  6 14:06:48 1998  Ian Lance Taylor  <ian@cygnus.com>
 	* ppc-opc.c (powerpc_opcodes): Add PowerPC403 GC[X] instructions.
 	From Saitoh Masanobu <msaitoh@spa.is.uec.ac.jp>.
 
-start-sanitize-fr30
 Fri Dec  4 17:45:51 1998  Doug Evans  <devans@canuck.cygnus.com>
 
 	* fr30-opc.c: Regenerate.
@@ -190,7 +181,6 @@ Thu Dec  3 00:09:17 1998  Doug Evans  <devans@canuck.cygnus.com>
 
 	* fr30-asm.c,fr30-dis.c,fr30-opc.c,fr30-opc.h: Regenerate.
 
-end-sanitize-fr30
 1998-11-30  Doug Evans  <devans@casey.cygnus.com>
 
 	* cgen-dis.c (hash_insn_array): CGEN_INSN_VALUE ->
@@ -207,9 +197,7 @@ start-sanitize-cygnus
 	* cgen-opc.in (FLD): Define.
 end-sanitize-cygnus
 	* m32r-opc.c,m32r-opc.h,m32r-asm.c,m32r-dis.c: Regenerate.
-start-sanitize-fr30
 	* fr30-opc.c,fr30-opc.h,fr30-asm.c,fr30-dis.c: Regenerate.
-end-sanitize-fr30
 
 start-sanitize-cygnus
 Mon Nov 30 11:52:44 1998  Doug Evans  <devans@canuck.cygnus.com>
@@ -218,7 +206,6 @@ Mon Nov 30 11:52:44 1998  Doug Evans  <devans@canuck.cygnus.com>
 	* Makefile.in: Rebuild.
 
 end-sanitize-cygnus
-start-sanitize-fr30
 Thu Nov 26 11:26:32 1998  Dave Brolley  <brolley@cygnus.com>
 
 	* fr30-asm.c,fr30-dis.c,fr30-opc.c: Regenerated.
@@ -242,12 +229,10 @@ Thu Nov 19 16:02:46 1998  Dave Brolley  <brolley@cygnus.com>
 	* fr30-dis.c: Regenerated.
 	* fr30-asm.c: Regenerated.
 
-end-sanitize-fr30
 Thu Nov 19 07:54:15 1998  Doug Evans  <devans@charmed.cygnus.com>
 
 	* mips-opc.c (sync.p,sync.l): Swap insn values.
 
-start-sanitize-fr30
 1998-11-19  Doug Evans  <devans@tobor.to.cygnus.com>
 
 	* fr30-opc.c: Regenerate.
@@ -257,7 +242,6 @@ Wed Nov 18 21:36:37 1998  Dave Brolley  <brolley@cygnus.com>
 	* fr30-opc.c: Regenerated.
 	* fr30-opc.h: Regenerated.
 
-end-sanitize-fr30
 1998-11-18  Doug Evans  <devans@casey.cygnus.com>
 
 start-sanitize-cygnus
@@ -277,11 +261,8 @@ start-sanitize-cygnus
 	(@arch@_cgen_lookup_insn): Rewrite ! CGEN_INT_INSN_P case.
 end-sanitize-cygnus
 	* m32r-asm.c,m32r-dis.c,m32r-opc.c: Rebuild.
-start-sanitize-fr30
 	* fr30-asm.c,fr30-dis.c,fr30-opc.c: Rebuild.
-end-sanitize-fr30
 
-start-sanitize-fr30
 Wed Nov 18 11:30:04 1998  Dave Brolley  <brolley@cygnus.com>
 
 	* fr30-opc.c: Regenerated.
@@ -305,7 +286,6 @@ Tue Nov 10 15:26:27 1998  Nick Clifton  <nickc@cygnus.com>
 
 	* disassemble.c (disassembler): Add support for FR30 target.
 	
-end-sanitize-fr30
 Tue Nov 10 11:00:04 1998  Doug Evans  <devans@canuck.cygnus.com>
 
 start-sanitize-cygnus
@@ -313,7 +293,6 @@ start-sanitize-cygnus
 	CGEN_OPERAND_SEM_ONLY.
 end-sanitize-cygnus
 	* m32r-dis.c,m32r-opc.c,m32r-opc.h: Rebuild.
-start-sanitize-fr30
 	* fr30-dis.c,fr30-opc.c,fr30-opc.h: Rebuild.
 
 Mon Nov  9 18:22:55 1998  Dave Brolley  <brolley@cygnus.com>
@@ -322,12 +301,11 @@ Mon Nov  9 18:22:55 1998  Dave Brolley  <brolley@cygnus.com>
 	* po/POTFILES.in: Regenerate.
 	* fr30-opc.c: Regenerate.
 	* fr30-opc.h: Regenerate.
-end-sanitize-fr30
+
 Fri Nov  6 17:21:38 1998  Doug Evans  <devans@canuck.cygnus.com>
 
 	* m32r-asm.c: Regenerate.
 
-start-sanitize-fr30
 Wed Nov  4 18:46:47 1998  Dave Brolley  <brolley@cygnus.com>
 
 	* configure.in: Added case for bfd_fr30_arch.
@@ -342,7 +320,6 @@ Wed Nov  4 18:46:47 1998  Dave Brolley  <brolley@cygnus.com>
 	* po/POTFILES.in: Regenerated
 	* po/opcodes.pot: Regenerated
 
-end-sanitize-fr30
 start-sanitize-m32rx
 Mon Nov  2 20:08:03 1998  Doug Evans  <devans@canuck.cygnus.com>
 
diff --git a/opcodes/Makefile.am b/opcodes/Makefile.am
index b63f011..c9b3304 100644
--- a/opcodes/Makefile.am
+++ b/opcodes/Makefile.am
@@ -37,16 +37,14 @@ CFILES = \
 	d30v-opc.c \
 	dis-buf.c \
 	disassemble.c \
-	$(start-sanitize-fr30) \
-	fr30-asm.c \
-	fr30-dis.c \
-	fr30-opc.c \
-	$(end-sanitize-fr30) \
 	h8300-dis.c \
 	h8500-dis.c \
 	hppa-dis.c \
 	i386-dis.c \
 	i960-dis.c \
+	i960c-asm.c \
+	i960c-dis.c \
+	i960c-opc.c \
 	m32r-asm.c \
 	m32r-dis.c \
 	m32r-opc.c \
@@ -86,16 +84,17 @@ ALL_MACHINES = \
 	d10v-opc.lo \
 	d30v-dis.lo \
 	d30v-opc.lo \
-	$(end-sanitize-fr30) \
 	fr30-asm.lo \
 	fr30-dis.lo \
 	fr30-opc.lo \
-	$(end-sanitize-fr30) \
 	h8300-dis.lo \
 	h8500-dis.lo \
 	hppa-dis.lo \
 	i386-dis.lo \
 	i960-dis.lo \
+	i960c-asm.lo \
+	i960c-dis.lo \
+	i960c-opc.lo \
 	m32r-asm.lo \
 	m32r-dis.lo \
 	m32r-opc.lo \
@@ -170,17 +169,17 @@ config.status: $(srcdir)/configure $(srcdir)/../bfd/configure.in
 
 CLEANFILES = libopcodes.a stamp-lib dep.sed .dep .dep1
 # start-sanitize-cygnus
-CLEANFILES = libopcodes.a stamp-lib dep.sed .dep .dep1 stamp-m32r
+CLEANFILES = libopcodes.a stamp-lib dep.sed .dep .dep1 \
+	stamp-m32r stamp-fr30 stamp-i960
 # end-sanitize-cygnus
-# start-sanitize-fr30
-CLEANFILES = libopcodes.a stamp-lib dep.sed .dep .dep1 stamp-m32r stamp-fr30
-# end-sanitize-fr30
 
-# start-sanitize-cygnus
+# start-sanitize-cygnus-never
 # CGEN support is sanitized out of FSF releases for now.
 # Sanitization must be split between assignments and rules because
 # automake splits them that way.
+# end-sanitize-cygnus-never
 
+# start-sanitize-cygnus
 CGENDIR = @cgendir@
 CGEN = @cgen@
 CGENFLAGS = -v
@@ -192,16 +191,19 @@ CGENFILES = $(CGENDIR)/cos.scm $(CGENDIR)/utils.scm \
 	$(CGENDIR)/model.scm $(CGENDIR)/hardware.scm \
 	$(CGENDIR)/ifield.scm $(CGENDIR)/iformat.scm \
 	$(CGENDIR)/operand.scm $(CGENDIR)/insn.scm $(CGENDIR)/minsn.scm \
-	$(CGENDIR)/opcodes.scm $(CGENDIR)/rtl.scm \
-	$(CGENDIR)/cgen-opc.scm cgen-opc.in cgen-asm.in cgen-dis.in
+	$(CGENDIR)/rtl.scm $(CGENDIR)/rtx-funcs.scm \
+	$(CGENDIR)/opcodes.scm $(CGENDIR)/cgen-opc.scm \
+	cgen-opc.in cgen-asm.in cgen-dis.in
 # The CGEN_MAINT conditional is put here so it ends up in Makefile.in
 # properly sanitized.
 if CGEN_MAINT
 M32R_DEPS = stamp-m32r
 FR30_DEPS = stamp-fr30
+I960_DEPS = stamp-i960
 else
 M32R_DEPS =
 FR30_DEPS =
+I960_DEPS =
 endif
 # The end marker is written this way to pass through automake unscathed.
 ENDSAN = end-sanitize-cygnus
@@ -217,13 +219,19 @@ m32r-opc.h m32r-opc.c m32r-asm.c m32r-dis.c: $(M32R_DEPS)
 	@true
 stamp-m32r: $(CGENFILES) $(CGENDIR)/m32r.cpu $(CGENDIR)/m32r.opc
 	$(MAKE) run-cgen arch=m32r prefix=m32r
-# end-sanitize-cygnus
-# start-sanitize-fr30
+
 fr30-opc.h fr30-opc.c fr30-asm.c fr30-dis.c: $(FR30_DEPS)
 	@true
 stamp-fr30: $(CGENFILES) $(CGENDIR)/fr30.cpu $(CGENDIR)/fr30.opc
 	$(MAKE) run-cgen arch=fr30 prefix=fr30
-# end-sanitize-fr30
+
+# Use a prefix of i960c, so that the existing i960-dis.c can remain for now.
+# When the cgen i960 disassembler support is complete, this `c' can go away.
+i960c-opc.h i960c-opc.c i960c-asm.c i960c-dis.c: $(I960_DEPS)
+	@true
+stamp-i960: $(CGENFILES) $(CGENDIR)/i960.cpu $(CGENDIR)/i960.opc
+	$(MAKE) run-cgen arch=i960 prefix=i960c
+# end-sanitize-cygnus
 
 # start-sanitize-tic80
 tic80-dis.lo: tic80-dis.c $(INCDIR)/dis-asm.h ../bfd/bfd.h \
@@ -240,18 +248,6 @@ mips-dis.lo: mips-dis.c
 	$(LIBTOOL) --mode=compile $(COMPILE) -c @archdefs@ $(srcdir)/mips-dis.c
 # end-sanitize-sky
 
-# start-sanitize-fr30
-fr30-asm.lo: fr30-asm.c sysdep.h config.h $(BFD_H) \
-  $(INCDIR)/symcat.h fr30-opc.h $(INCDIR)/opcode/cgen.h \
-  opintl.h
-fr30-dis.lo: fr30-dis.c sysdep.h config.h $(INCDIR)/dis-asm.h \
-  $(BFD_H) $(INCDIR)/symcat.h fr30-opc.h $(INCDIR)/opcode/cgen.h \
-  opintl.h
-fr30-opc.lo: fr30-opc.c sysdep.h config.h $(INCDIR)/libiberty.h \
-  $(BFD_H) $(INCDIR)/symcat.h fr30-opc.h $(INCDIR)/opcode/cgen.h \
-  opintl.h
-# end-sanitize-fr30
-
 # This dependency stuff is copied from BFD.
 
 .dep: dep.sed $(CFILES) $(HFILES) config.h
@@ -323,6 +319,15 @@ dis-buf.lo: dis-buf.c sysdep.h config.h $(INCDIR)/dis-asm.h \
   $(BFD_H) opintl.h
 disassemble.lo: disassemble.c $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H)
+fr30-asm.lo: fr30-asm.c sysdep.h config.h $(BFD_H) \
+  $(INCDIR)/symcat.h fr30-opc.h $(INCDIR)/opcode/cgen.h \
+  opintl.h
+fr30-dis.lo: fr30-dis.c sysdep.h config.h $(INCDIR)/dis-asm.h \
+  $(BFD_H) $(INCDIR)/symcat.h fr30-opc.h $(INCDIR)/opcode/cgen.h \
+  opintl.h
+fr30-opc.lo: fr30-opc.c sysdep.h config.h $(INCDIR)/libiberty.h \
+  $(BFD_H) $(INCDIR)/symcat.h fr30-opc.h $(INCDIR)/opcode/cgen.h \
+  opintl.h
 h8300-dis.lo: h8300-dis.c $(INCDIR)/opcode/h8300.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h opintl.h
 h8500-dis.lo: h8500-dis.c h8500-opc.h $(INCDIR)/dis-asm.h \
@@ -333,6 +338,15 @@ i386-dis.lo: i386-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
   $(INCDIR)/ansidecl.h sysdep.h config.h opintl.h
 i960-dis.lo: i960-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
   $(INCDIR)/ansidecl.h
+i960c-asm.lo: i960c-asm.c sysdep.h config.h $(BFD_H) \
+  $(INCDIR)/symcat.h i960c-opc.h $(INCDIR)/opcode/cgen.h \
+  opintl.h
+i960c-dis.lo: i960c-dis.c sysdep.h config.h $(INCDIR)/dis-asm.h \
+  $(BFD_H) $(INCDIR)/symcat.h i960c-opc.h $(INCDIR)/opcode/cgen.h \
+  opintl.h
+i960c-opc.lo: i960c-opc.c sysdep.h config.h $(INCDIR)/libiberty.h \
+  $(BFD_H) $(INCDIR)/symcat.h i960c-opc.h $(INCDIR)/opcode/cgen.h \
+  opintl.h
 m32r-asm.lo: m32r-asm.c sysdep.h config.h $(BFD_H) \
   $(INCDIR)/symcat.h m32r-opc.h $(INCDIR)/opcode/cgen.h \
   opintl.h
diff --git a/opcodes/Makefile.in b/opcodes/Makefile.in
index 6e79465..b9a6efa 100644
--- a/opcodes/Makefile.in
+++ b/opcodes/Makefile.in
@@ -143,16 +143,14 @@ CFILES = \
 	d30v-opc.c \
 	dis-buf.c \
 	disassemble.c \
-	$(start-sanitize-fr30) \
-	fr30-asm.c \
-	fr30-dis.c \
-	fr30-opc.c \
-	$(end-sanitize-fr30) \
 	h8300-dis.c \
 	h8500-dis.c \
 	hppa-dis.c \
 	i386-dis.c \
 	i960-dis.c \
+	i960c-asm.c \
+	i960c-dis.c \
+	i960c-opc.c \
 	m32r-asm.c \
 	m32r-dis.c \
 	m32r-opc.c \
@@ -192,16 +190,17 @@ ALL_MACHINES = \
 	d10v-opc.lo \
 	d30v-dis.lo \
 	d30v-opc.lo \
-	$(end-sanitize-fr30) \
 	fr30-asm.lo \
 	fr30-dis.lo \
 	fr30-opc.lo \
-	$(end-sanitize-fr30) \
 	h8300-dis.lo \
 	h8500-dis.lo \
 	hppa-dis.lo \
 	i386-dis.lo \
 	i960-dis.lo \
+	i960c-asm.lo \
+	i960c-dis.lo \
+	i960c-opc.lo \
 	m32r-asm.lo \
 	m32r-dis.lo \
 	m32r-opc.lo \
@@ -256,17 +255,17 @@ POTFILES = $(HFILES) $(CFILES)
 
 CLEANFILES = libopcodes.a stamp-lib dep.sed .dep .dep1
 # start-sanitize-cygnus
-CLEANFILES = libopcodes.a stamp-lib dep.sed .dep .dep1 stamp-m32r
+CLEANFILES = libopcodes.a stamp-lib dep.sed .dep .dep1 \
+	stamp-m32r stamp-fr30 stamp-i960
 # end-sanitize-cygnus
-# start-sanitize-fr30
-CLEANFILES = libopcodes.a stamp-lib dep.sed .dep .dep1 stamp-m32r stamp-fr30
-# end-sanitize-fr30
 
-# start-sanitize-cygnus
+# start-sanitize-cygnus-never
 # CGEN support is sanitized out of FSF releases for now.
 # Sanitization must be split between assignments and rules because
 # automake splits them that way.
+# end-sanitize-cygnus-never
 
+# start-sanitize-cygnus
 CGENDIR = @cgendir@
 CGEN = @cgen@
 CGENFLAGS = -v
@@ -278,14 +277,17 @@ CGENFILES = $(CGENDIR)/cos.scm $(CGENDIR)/utils.scm \
 	$(CGENDIR)/model.scm $(CGENDIR)/hardware.scm \
 	$(CGENDIR)/ifield.scm $(CGENDIR)/iformat.scm \
 	$(CGENDIR)/operand.scm $(CGENDIR)/insn.scm $(CGENDIR)/minsn.scm \
-	$(CGENDIR)/opcodes.scm $(CGENDIR)/rtl.scm \
-	$(CGENDIR)/cgen-opc.scm cgen-opc.in cgen-asm.in cgen-dis.in
+	$(CGENDIR)/rtl.scm $(CGENDIR)/rtx-funcs.scm \
+	$(CGENDIR)/opcodes.scm $(CGENDIR)/cgen-opc.scm \
+	cgen-opc.in cgen-asm.in cgen-dis.in
 # The CGEN_MAINT conditional is put here so it ends up in Makefile.in
 # properly sanitized.
 @CGEN_MAINT_TRUE@M32R_DEPS = stamp-m32r
 @CGEN_MAINT_TRUE@FR30_DEPS = stamp-fr30
+@CGEN_MAINT_TRUE@I960_DEPS = stamp-i960
 @CGEN_MAINT_FALSE@M32R_DEPS =
 @CGEN_MAINT_FALSE@FR30_DEPS =
+@CGEN_MAINT_FALSE@I960_DEPS =
 # The end marker is written this way to pass through automake unscathed.
 ENDSAN = end-sanitize-cygnus
 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
@@ -324,7 +326,7 @@ all: all-recursive-am all-am
 
 .SUFFIXES:
 .SUFFIXES: .S .c .lo .o .s
-$(srcdir)/Makefile.in: @MAINT@ Makefile.am $(top_srcdir)/configure.in $(ACLOCAL_M4)
+$(srcdir)/Makefile.in: @MAINT@Makefile.am $(top_srcdir)/configure.in $(ACLOCAL_M4)
 	cd $(top_srcdir) && $(AUTOMAKE) --cygnus Makefile
 
 Makefile: $(srcdir)/Makefile.in  $(top_builddir)/config.status
@@ -673,13 +675,19 @@ m32r-opc.h m32r-opc.c m32r-asm.c m32r-dis.c: $(M32R_DEPS)
 	@true
 stamp-m32r: $(CGENFILES) $(CGENDIR)/m32r.cpu $(CGENDIR)/m32r.opc
 	$(MAKE) run-cgen arch=m32r prefix=m32r
-# end-sanitize-cygnus
-# start-sanitize-fr30
+
 fr30-opc.h fr30-opc.c fr30-asm.c fr30-dis.c: $(FR30_DEPS)
 	@true
 stamp-fr30: $(CGENFILES) $(CGENDIR)/fr30.cpu $(CGENDIR)/fr30.opc
 	$(MAKE) run-cgen arch=fr30 prefix=fr30
-# end-sanitize-fr30
+
+# Use a prefix of i960c, so that the existing i960-dis.c can remain for now.
+# When the cgen i960 disassembler support is complete, this `c' can go away.
+i960c-opc.h i960c-opc.c i960c-asm.c i960c-dis.c: $(I960_DEPS)
+	@true
+stamp-i960: $(CGENFILES) $(CGENDIR)/i960.cpu $(CGENDIR)/i960.opc
+	$(MAKE) run-cgen arch=i960 prefix=i960c
+# end-sanitize-cygnus
 
 # start-sanitize-tic80
 tic80-dis.lo: tic80-dis.c $(INCDIR)/dis-asm.h ../bfd/bfd.h \
@@ -696,18 +704,6 @@ mips-dis.lo: mips-dis.c
 	$(LIBTOOL) --mode=compile $(COMPILE) -c @archdefs@ $(srcdir)/mips-dis.c
 # end-sanitize-sky
 
-# start-sanitize-fr30
-fr30-asm.lo: fr30-asm.c sysdep.h config.h $(BFD_H) \
-  $(INCDIR)/symcat.h fr30-opc.h $(INCDIR)/opcode/cgen.h \
-  opintl.h
-fr30-dis.lo: fr30-dis.c sysdep.h config.h $(INCDIR)/dis-asm.h \
-  $(BFD_H) $(INCDIR)/symcat.h fr30-opc.h $(INCDIR)/opcode/cgen.h \
-  opintl.h
-fr30-opc.lo: fr30-opc.c sysdep.h config.h $(INCDIR)/libiberty.h \
-  $(BFD_H) $(INCDIR)/symcat.h fr30-opc.h $(INCDIR)/opcode/cgen.h \
-  opintl.h
-# end-sanitize-fr30
-
 # This dependency stuff is copied from BFD.
 
 .dep: dep.sed $(CFILES) $(HFILES) config.h
@@ -779,6 +775,15 @@ dis-buf.lo: dis-buf.c sysdep.h config.h $(INCDIR)/dis-asm.h \
   $(BFD_H) opintl.h
 disassemble.lo: disassemble.c $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H)
+fr30-asm.lo: fr30-asm.c sysdep.h config.h $(BFD_H) \
+  $(INCDIR)/symcat.h fr30-opc.h $(INCDIR)/opcode/cgen.h \
+  opintl.h
+fr30-dis.lo: fr30-dis.c sysdep.h config.h $(INCDIR)/dis-asm.h \
+  $(BFD_H) $(INCDIR)/symcat.h fr30-opc.h $(INCDIR)/opcode/cgen.h \
+  opintl.h
+fr30-opc.lo: fr30-opc.c sysdep.h config.h $(INCDIR)/libiberty.h \
+  $(BFD_H) $(INCDIR)/symcat.h fr30-opc.h $(INCDIR)/opcode/cgen.h \
+  opintl.h
 h8300-dis.lo: h8300-dis.c $(INCDIR)/opcode/h8300.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h opintl.h
 h8500-dis.lo: h8500-dis.c h8500-opc.h $(INCDIR)/dis-asm.h \
@@ -789,6 +794,15 @@ i386-dis.lo: i386-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
   $(INCDIR)/ansidecl.h sysdep.h config.h opintl.h
 i960-dis.lo: i960-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
   $(INCDIR)/ansidecl.h
+i960c-asm.lo: i960c-asm.c sysdep.h config.h $(BFD_H) \
+  $(INCDIR)/symcat.h i960c-opc.h $(INCDIR)/opcode/cgen.h \
+  opintl.h
+i960c-dis.lo: i960c-dis.c sysdep.h config.h $(INCDIR)/dis-asm.h \
+  $(BFD_H) $(INCDIR)/symcat.h i960c-opc.h $(INCDIR)/opcode/cgen.h \
+  opintl.h
+i960c-opc.lo: i960c-opc.c sysdep.h config.h $(INCDIR)/libiberty.h \
+  $(BFD_H) $(INCDIR)/symcat.h i960c-opc.h $(INCDIR)/opcode/cgen.h \
+  opintl.h
 m32r-asm.lo: m32r-asm.c sysdep.h config.h $(BFD_H) \
   $(INCDIR)/symcat.h m32r-opc.h $(INCDIR)/opcode/cgen.h \
   opintl.h
diff --git a/opcodes/fr30-opc.c b/opcodes/fr30-opc.c
index 2c78e4a..c4efb99 100644
--- a/opcodes/fr30-opc.c
+++ b/opcodes/fr30-opc.c
@@ -621,7 +621,7 @@ const CGEN_OPERAND fr30_cgen_operand_table[MAX_OPERANDS] =
 /* scr: system condition bits */
   { "scr", & HW_ENT (HW_H_SCR), 0, 0,
     { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } }  },
-/* ilm: condition code bits */
+/* ilm: interrupt level mask */
   { "ilm", & HW_ENT (HW_H_ILM), 0, 0,
     { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } }  },
 };
@@ -1206,8 +1206,8 @@ static const CGEN_OPERAND_INSTANCE fmt_reti_ops[] = {
 };
 
 static const CGEN_OPERAND_INSTANCE fmt_brad_ops[] = {
-  { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
-  { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, 0 },
+  { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
   { 0 }
 };
 
@@ -2862,7 +2862,7 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     { { MNEM, ' ', OP (LABEL9), 0 } },
     & fmt_brad, { 0xf000 },
     (PTR) & fmt_brad_ops[0],
-    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
   },
 /* bra $label9 */
   {
@@ -2871,7 +2871,7 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     { { MNEM, ' ', OP (LABEL9), 0 } },
     & fmt_brad, { 0xe000 },
     (PTR) & fmt_brad_ops[0],
-    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
   },
 /* bno:d $label9 */
   {
@@ -2880,7 +2880,7 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     { { MNEM, ' ', OP (LABEL9), 0 } },
     & fmt_brad, { 0xf100 },
     (PTR) & fmt_brad_ops[0],
-    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
   },
 /* bno $label9 */
   {
@@ -2889,7 +2889,7 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     { { MNEM, ' ', OP (LABEL9), 0 } },
     & fmt_brad, { 0xe100 },
     (PTR) & fmt_brad_ops[0],
-    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
   },
 /* beq:d $label9 */
   {
@@ -2898,7 +2898,7 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     { { MNEM, ' ', OP (LABEL9), 0 } },
     & fmt_beqd, { 0xf200 },
     (PTR) & fmt_beqd_ops[0],
-    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
   },
 /* beq $label9 */
   {
@@ -2907,7 +2907,7 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     { { MNEM, ' ', OP (LABEL9), 0 } },
     & fmt_beqd, { 0xe200 },
     (PTR) & fmt_beqd_ops[0],
-    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
   },
 /* bne:d $label9 */
   {
@@ -2916,7 +2916,7 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     { { MNEM, ' ', OP (LABEL9), 0 } },
     & fmt_beqd, { 0xf300 },
     (PTR) & fmt_beqd_ops[0],
-    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
   },
 /* bne $label9 */
   {
@@ -2925,7 +2925,7 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     { { MNEM, ' ', OP (LABEL9), 0 } },
     & fmt_beqd, { 0xe300 },
     (PTR) & fmt_beqd_ops[0],
-    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
   },
 /* bc:d $label9 */
   {
@@ -2934,7 +2934,7 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     { { MNEM, ' ', OP (LABEL9), 0 } },
     & fmt_bcd, { 0xf400 },
     (PTR) & fmt_bcd_ops[0],
-    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
   },
 /* bc $label9 */
   {
@@ -2943,7 +2943,7 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     { { MNEM, ' ', OP (LABEL9), 0 } },
     & fmt_bcd, { 0xe400 },
     (PTR) & fmt_bcd_ops[0],
-    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
   },
 /* bnc:d $label9 */
   {
@@ -2952,7 +2952,7 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     { { MNEM, ' ', OP (LABEL9), 0 } },
     & fmt_bcd, { 0xf500 },
     (PTR) & fmt_bcd_ops[0],
-    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
   },
 /* bnc $label9 */
   {
@@ -2961,7 +2961,7 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     { { MNEM, ' ', OP (LABEL9), 0 } },
     & fmt_bcd, { 0xe500 },
     (PTR) & fmt_bcd_ops[0],
-    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
   },
 /* bn:d $label9 */
   {
@@ -2970,7 +2970,7 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     { { MNEM, ' ', OP (LABEL9), 0 } },
     & fmt_bnd, { 0xf600 },
     (PTR) & fmt_bnd_ops[0],
-    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
   },
 /* bn $label9 */
   {
@@ -2979,7 +2979,7 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     { { MNEM, ' ', OP (LABEL9), 0 } },
     & fmt_bnd, { 0xe600 },
     (PTR) & fmt_bnd_ops[0],
-    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
   },
 /* bp:d $label9 */
   {
@@ -2988,7 +2988,7 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     { { MNEM, ' ', OP (LABEL9), 0 } },
     & fmt_bnd, { 0xf700 },
     (PTR) & fmt_bnd_ops[0],
-    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
   },
 /* bp $label9 */
   {
@@ -2997,7 +2997,7 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     { { MNEM, ' ', OP (LABEL9), 0 } },
     & fmt_bnd, { 0xe700 },
     (PTR) & fmt_bnd_ops[0],
-    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
   },
 /* bv:d $label9 */
   {
@@ -3006,7 +3006,7 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     { { MNEM, ' ', OP (LABEL9), 0 } },
     & fmt_bvd, { 0xf800 },
     (PTR) & fmt_bvd_ops[0],
-    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
   },
 /* bv $label9 */
   {
@@ -3015,7 +3015,7 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     { { MNEM, ' ', OP (LABEL9), 0 } },
     & fmt_bvd, { 0xe800 },
     (PTR) & fmt_bvd_ops[0],
-    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
   },
 /* bnv:d $label9 */
   {
@@ -3024,7 +3024,7 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     { { MNEM, ' ', OP (LABEL9), 0 } },
     & fmt_bvd, { 0xf900 },
     (PTR) & fmt_bvd_ops[0],
-    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
   },
 /* bnv $label9 */
   {
@@ -3033,7 +3033,7 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     { { MNEM, ' ', OP (LABEL9), 0 } },
     & fmt_bvd, { 0xe900 },
     (PTR) & fmt_bvd_ops[0],
-    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
   },
 /* blt:d $label9 */
   {
@@ -3042,7 +3042,7 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     { { MNEM, ' ', OP (LABEL9), 0 } },
     & fmt_bltd, { 0xfa00 },
     (PTR) & fmt_bltd_ops[0],
-    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
   },
 /* blt $label9 */
   {
@@ -3051,7 +3051,7 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     { { MNEM, ' ', OP (LABEL9), 0 } },
     & fmt_bltd, { 0xea00 },
     (PTR) & fmt_bltd_ops[0],
-    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
   },
 /* bge:d $label9 */
   {
@@ -3060,7 +3060,7 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     { { MNEM, ' ', OP (LABEL9), 0 } },
     & fmt_bltd, { 0xfb00 },
     (PTR) & fmt_bltd_ops[0],
-    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
   },
 /* bge $label9 */
   {
@@ -3069,7 +3069,7 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     { { MNEM, ' ', OP (LABEL9), 0 } },
     & fmt_bltd, { 0xeb00 },
     (PTR) & fmt_bltd_ops[0],
-    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
   },
 /* ble:d $label9 */
   {
@@ -3078,7 +3078,7 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     { { MNEM, ' ', OP (LABEL9), 0 } },
     & fmt_bled, { 0xfc00 },
     (PTR) & fmt_bled_ops[0],
-    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
   },
 /* ble $label9 */
   {
@@ -3087,7 +3087,7 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     { { MNEM, ' ', OP (LABEL9), 0 } },
     & fmt_bled, { 0xec00 },
     (PTR) & fmt_bled_ops[0],
-    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
   },
 /* bgt:d $label9 */
   {
@@ -3096,7 +3096,7 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     { { MNEM, ' ', OP (LABEL9), 0 } },
     & fmt_bled, { 0xfd00 },
     (PTR) & fmt_bled_ops[0],
-    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
   },
 /* bgt $label9 */
   {
@@ -3105,7 +3105,7 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     { { MNEM, ' ', OP (LABEL9), 0 } },
     & fmt_bled, { 0xed00 },
     (PTR) & fmt_bled_ops[0],
-    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
   },
 /* bls:d $label9 */
   {
@@ -3114,7 +3114,7 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     { { MNEM, ' ', OP (LABEL9), 0 } },
     & fmt_blsd, { 0xfe00 },
     (PTR) & fmt_blsd_ops[0],
-    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
   },
 /* bls $label9 */
   {
@@ -3123,7 +3123,7 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     { { MNEM, ' ', OP (LABEL9), 0 } },
     & fmt_blsd, { 0xee00 },
     (PTR) & fmt_blsd_ops[0],
-    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
   },
 /* bhi:d $label9 */
   {
@@ -3132,7 +3132,7 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     { { MNEM, ' ', OP (LABEL9), 0 } },
     & fmt_blsd, { 0xff00 },
     (PTR) & fmt_blsd_ops[0],
-    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
   },
 /* bhi $label9 */
   {
@@ -3141,7 +3141,7 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     { { MNEM, ' ', OP (LABEL9), 0 } },
     & fmt_blsd, { 0xef00 },
     (PTR) & fmt_blsd_ops[0],
-    { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
+    { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
   },
 /* dmov $R13,@$dir10 */
   {