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| author | Nick Clifton <nickc@redhat.com> | 2017-09-27 16:21:36 +0100 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2017-09-27 16:21:36 +0100 |
| commit | 8e43602e34ba404d82f7c74f6629f01e40c740e0 (patch) | |
| tree | 6eff6a48f8a4cd5c54a4ea7f14ae251b1a06dfb7 /opcodes | |
| parent | f21b4d5c59136c38bb6d94eb6a29ad80d02043f4 (diff) | |
| download | gdb-8e43602e34ba404d82f7c74f6629f01e40c740e0.zip gdb-8e43602e34ba404d82f7c74f6629f01e40c740e0.tar.gz gdb-8e43602e34ba404d82f7c74f6629f01e40c740e0.tar.bz2 | |
Add support for the new names of the RISC-V fmv.x.s and fmv.s.x instructions, vis: fmv.x.w and fmv.w.x.
PR 22179
opcodes * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
names for the fmv.x.s and fmv.s.x instructions respectively.
gas * testsuite/gas/riscv/fmv.x.s: New file: Tests the support for the
renamed fmv.x.s and fmv.s.x instructions.
* testsuite/gas/riscv/fmv.x.d: New file: Test driver.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 6 | ||||
| -rw-r--r-- | opcodes/riscv-opc.c | 5 |
2 files changed, 11 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index e8061b3..9280b2c 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,9 @@ +2017-09-27 Nick Clifton <nickc@redhat.com> + + PR 22179 + * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new + names for the fmv.x.s and fmv.s.x instructions respectively. + 2017-09-26 do <do@nerilex.org> PR 22123 diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 70a3628..27b4b9f 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -435,8 +435,13 @@ const struct riscv_opcode riscv_opcodes[] = {"fsw", "32C", "CD,Ck(Cs)", MATCH_C_FSW, MASK_C_FSW, match_opcode, INSN_ALIAS }, {"fsw", "F", "T,q(s)", MATCH_FSW, MASK_FSW, match_opcode, 0 }, {"fsw", "F", "T,A,s", 0, (int) M_FSW, match_never, INSN_MACRO }, + +{"fmv.x.w", "F", "d,S", MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, 0 }, +{"fmv.w.x", "F", "D,s", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 }, + {"fmv.x.s", "F", "d,S", MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, 0 }, {"fmv.s.x", "F", "D,s", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 }, + {"fmv.s", "F", "D,U", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_rs1_eq_rs2, INSN_ALIAS }, {"fneg.s", "F", "D,U", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_rs1_eq_rs2, INSN_ALIAS }, {"fabs.s", "F", "D,U", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_rs1_eq_rs2, INSN_ALIAS }, |