[ARC] Object attributes.

gas/
2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>

	* testsuite/gas/arc/attr-arc600.d: New file.
	* testsuite/gas/arc/attr-arc600_mul32x16.d: Likewise.
	* testsuite/gas/arc/attr-arc600_norm.d: Likewise.
	* testsuite/gas/arc/attr-arc601.d: Likewise.
	* testsuite/gas/arc/attr-arc601_mul32x16.d: Likewise.
	* testsuite/gas/arc/attr-arc601_mul64.d: Likewise.
	* testsuite/gas/arc/attr-arc601_norm.d: Likewise.
	* testsuite/gas/arc/attr-arc700.d: Likewise.
	* testsuite/gas/arc/attr-arcem.d: Likewise.
	* testsuite/gas/arc/attr-archs.d: Likewise.
	* testsuite/gas/arc/attr-autodetect-1.d: Likewise.
	* testsuite/gas/arc/attr-autodetect-1.s: Likewise.
	* testsuite/gas/arc/attr-cpu-a601.d: Likewise.
	* testsuite/gas/arc/attr-cpu-a601.s: Likewise.
	* testsuite/gas/arc/attr-cpu-a700.d: Likewise.
	* testsuite/gas/arc/attr-cpu-a700.s: Likewise.
	* testsuite/gas/arc/attr-cpu-em.d: Likewise.
	* testsuite/gas/arc/attr-cpu-em.s: Likewise.
	* testsuite/gas/arc/attr-cpu-hs.d: Likewise.
	* testsuite/gas/arc/attr-cpu-hs.s: Likewise.
	* testsuite/gas/arc/attr-em.d: Likewise.
	* testsuite/gas/arc/attr-em4.d: Likewise.
	* testsuite/gas/arc/attr-em4_dmips.d: Likewise.
	* testsuite/gas/arc/attr-em4_fpuda.d: Likewise.
	* testsuite/gas/arc/attr-em4_fpus.d: Likewise.
	* testsuite/gas/arc/attr-hs.d: Likewise.
	* testsuite/gas/arc/attr-hs34.d: Likewise.
	* testsuite/gas/arc/attr-hs38.d: Likewise.
	* testsuite/gas/arc/attr-hs38_linux.d: Likewise.
	* testsuite/gas/arc/attr-mul64.d: Likewise.
	* testsuite/gas/arc/attr-name.d: Likewise.
	* testsuite/gas/arc/attr-name.s: Likewise.
	* testsuite/gas/arc/attr-nps400.d: Likewise.
	* testsuite/gas/arc/attr-override-mcpu.d: Likewise.
	* testsuite/gas/arc/attr-override-mcpu.s
	* testsuite/gas/arc/attr-quarkse_em.d: Likewise.
	* testsuite/gas/arc/blank.s: Likewise.
	* testsuite/gas/elf/section2.e-arc: Likewise.
	* testsuite/gas/arc/cpu-pseudop-1.d: Update test.
	* testsuite/gas/arc/cpu-pseudop-2.d: Likewise.
	* testsuite/gas/arc/nps400-0.d: Likewise.
	* testsuite/gas/elf/elf.exp: Set target_machine for ARC.
	* config/tc-arc.c (opcode/arc-attrs.h): Include.
	(ARC_GET_FLAG, ARC_SET_FLAG, streq): Define.
	(arc_attribute): Declare new function.
	(md_pseudo_table): Add arc_attribute.
	(cpu_types): Rename default cpu features.
	(selected_cpu): Set the default OSABI flag.
	(mpy_option): New variable.
	(pic_option): Likewise.
	(sda_option): Likewise.
	(tls_option): Likewise.
	(feature_type, feature_list): Remove.
	(arc_initial_eflag): Likewise.
	(attributes_set_explicitly): New variable.
	(arc_check_feature): Check also for the conflicting features.
	(arc_select_cpu): Refactor assignment of selected_cpu.eflags.
	(arc_option): Remove setting of private flags and architecture.
	(check_cpu_feature): Refactor feature names.
	(autodetect_attributes): New function.
	(assemble_tokens): Use above function.
	(md_parse_option): Refactor feature names.
	(arc_attribute): New function.
	(arc_set_attribute_int): Likewise.
	(arc_set_attribute_string): Likewise.
	(arc_stralloc): Likewise.
	(arc_set_public_attributes): Likewise.
	(arc_md_end): Likewise.
	(arc_copy_symbol_attributes): Likewise.
	(rc_convert_symbolic_attribute): Likewise.
	* config/tc-arc.h (md_end): Define.
	(CONVERT_SYMBOLIC_ATTRIBUTE): Likewise.
	(TC_COPY_SYMBOL_ATTRIBUTES): Likewise.
	* doc/c-arc.texi: Document ARC object attributes.

binutils/
2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>

	* readelf.c (decode_ARC_machine_flags): Recognize OSABI v4.
	(get_arc_section_type_name): New function.
	(get_section_type_name): Use the above function.
	(display_arc_attribute): New function.
	(process_arc_specific): Likewise.
	(process_arch_specific): Handle ARC specific information.
	* testsuite/binutils-all/strip-3.d: Consider ARC.attributes
	section.

include/
2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>

	* elf/arc.h (SHT_ARC_ATTRIBUTES): Define.
	(Tag_ARC_*): Define.
	(E_ARC_OSABI_V4): Define.
	(E_ARC_OSABI_CURRENT): Reassign it.
	(TAG_CPU_*): Define.
	* opcode/arc-attrs.h: New file.
	* opcode/arc.h (insn_subclass_t): Assign enum values.
	(insn_subclass_t): Update enum with QUARKSE1, QUARKSE2, and LL64.
	(ARC_EA, ARC_CD, ARC_LLOCK, ARC_ATOMIC, ARC_MPY, ARC_MULT)
	(ARC_NPS400, ARC_DPFP, ARC_SPFP, ARC_FPU, ARC_FPUDA, ARC_SWAP)
	(ARC_NORM, ARC_BSCAN, ARC_UIX, ARC_TSTAMP, ARC_VBFDW)
	(ARC_BARREL, ARC_DSPA, ARC_SHIFT, ARC_INTR, ARC_DIV, ARC_XMAC)
	(ARC_CRC): Delete.

bfd/
2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>

	* elf32-arc.c (FEATURE_LIST_NAME): Define.
	(CONFLICT_LIST): Likewise.
	(opcode/arc-attrs.h): Include.
	(arc_elf_print_private_bfd_data): Print OSABI v4 flag.
	(arc_extract_features): New file.
	(arc_stralloc): Likewise.
	(arc_elf_merge_attributes): Likewise.
	(arc_elf_merge_private_bfd_data): Use object attributes.
	(bfd_arc_get_mach_from_attributes): New function.
	(arc_elf_object_p): Use object attributes.
	(arc_elf_final_write_processing): Likewise.
	(elf32_arc_obj_attrs_arg_type): New function.
	(elf32_arc_obj_attrs_handle_unknown): Likewise.
	(elf32_arc_section_from_shdr): Likewise.
	(elf_backend_obj_attrs_vendor): Define.
	(elf_backend_obj_attrs_section): Likewise.
	(elf_backend_obj_attrs_arg_type): Likewise.
	(elf_backend_obj_attrs_section_type): Likewise.
	(elf_backend_obj_attrs_handle_unknown): Likewise.
	(elf_backend_section_from_shdr): Likewise.

ld/
2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>

	* testsuite/ld-arc/attr-merge-0.d: New file.
	* testsuite/ld-arc/attr-merge-0.s: Likewise.
	* testsuite/ld-arc/attr-merge-0e.s: Likewise.
	* testsuite/ld-arc/attr-merge-1.d: Likewise.
	* testsuite/ld-arc/attr-merge-1.s: Likewise.
	* testsuite/ld-arc/attr-merge-1e.s: Likewise.
	* testsuite/ld-arc/attr-merge-2.d: Likewise.
	* testsuite/ld-arc/attr-merge-2.s: Likewise.
	* testsuite/ld-arc/attr-merge-3.d: Likewise.
	* testsuite/ld-arc/attr-merge-3.s: Likewise.
	* testsuite/ld-arc/attr-merge-3e.s: Likewise.
	* testsuite/ld-arc/attr-merge-4.s: Likewise.
	* testsuite/ld-arc/attr-merge-5.d: Likewise.
	* testsuite/ld-arc/attr-merge-5a.s: Likewise.
	* testsuite/ld-arc/attr-merge-5b.s: Likewise.
	* testsuite/ld-arc/attr-merge-conflict-isa.d: Likewise.
	* testsuite/ld-arc/attr-merge-err-isa.d: Likewise.
	* testsuite/ld-arc/attr-merge-incompatible-cpu.d: Likewise.
	* testsuite/ld-arc/got-01.d: Update test.
	* testsuite/ld-arc/attr-merge-err-quarkse.d: New file.
	* testsuite/ld-arc/attr-quarkse.s: Likewise.
	* testsuite/ld-arc/attr-quarkse2.s: Likewise.

opcodes/
2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-dis.c (parse_option): Update quarkse_em option..
	* arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
	QUARKSE1.
	(dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.

4 files changed, 37 insertions, 29 deletions

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index ea0902f..542316a 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,10 @@
+2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>
+
+	* arc-dis.c (parse_option): Update quarkse_em option..
+	* arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
+	QUARKSE1.
+	(dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
+
 2017-05-03  Kito Cheng  <kito.cheng@gmail.com>
 
 	* riscv-dis.c (print_insn_args): Handle 'Co' operands.
diff --git a/opcodes/arc-dis.c b/opcodes/arc-dis.c
index 6fb030e..0cf4bff 100644
--- a/opcodes/arc-dis.c
+++ b/opcodes/arc-dis.c
@@ -748,7 +748,8 @@ parse_option (const char *option)
     {
       add_to_decodelist (FLOAT, DPX);
       add_to_decodelist (FLOAT, SPX);
-      add_to_decodelist (FLOAT, QUARKSE);
+      add_to_decodelist (FLOAT, QUARKSE1);
+      add_to_decodelist (FLOAT, QUARKSE2);
     }
 
   else if (CONST_STRNEQ (option, "fpuda"))
diff --git a/opcodes/arc-ext-tbl.h b/opcodes/arc-ext-tbl.h
index 422b93c..26a6683 100644
--- a/opcodes/arc-ext-tbl.h
+++ b/opcodes/arc-ext-tbl.h
@@ -116,12 +116,12 @@
       ARG_32BIT_ZALIMMLIMM, FLAGS_CCF },
 
 /* Extension instruction declarations.  */
-EXTINSN2OP ("dsp_fp_flt2i",  ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE, 7, 43)
-EXTINSN2OP ("dsp_fp_i2flt",  ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE, 7, 44)
-EXTINSN2OP ("dsp_fp_sqrt",   ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE, 7, 45)
+EXTINSN2OP ("dsp_fp_flt2i",  ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE1, 7, 43)
+EXTINSN2OP ("dsp_fp_i2flt",  ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE1, 7, 44)
+EXTINSN2OP ("dsp_fp_sqrt",   ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE2, 7, 45)
 
-EXTINSN3OP ("dsp_fp_div", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE, 7, 42)
-EXTINSN3OP ("dsp_fp_cmp", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE, 7, 43)
+EXTINSN3OP ("dsp_fp_div", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE2, 7, 42)
+EXTINSN3OP ("dsp_fp_cmp", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE1, 7, 43)
 
 /* Bitstream extensions.  */
 EXTINSN2OP ("bspeek", ARC_OPCODE_ARCv2EM, BITSTREAM, NONE, 0x05, 0x2E)
diff --git a/opcodes/arc-tbl.h b/opcodes/arc-tbl.h
index 826b2ce..79e6b89 100644
--- a/opcodes/arc-tbl.h
+++ b/opcodes/arc-tbl.h
@@ -8086,46 +8086,46 @@
 { "ldb_s", 0x0000CA00, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { R0_S, BRAKET, GP_S, SIMM9_7_S, BRAKETdup }, { C_ZZ_B }},
 
 /* ldd<.di><.aa> a,b 00010bbb000000000BBBDaa110AAAAAA.  */
-{ "ldd", 0x10000180, 0xF8FF81C0, ARC_OPCODE_ARCv2HS, LOAD, NONE, { RAD, BRAKET, RB, BRAKETdup }, { C_DI20, C_AA21, C_ZZ_D }},
+{ "ldd", 0x10000180, 0xF8FF81C0, ARC_OPCODE_ARCv2HS, LOAD, LL64, { RAD, BRAKET, RB, BRAKETdup }, { C_DI20, C_AA21, C_ZZ_D }},
 
 /* ldd<.di><.aa> a,b,c 00100bbbaa110110DBBBCCCCCCAAAAAA.  */
-{ "ldd", 0x20360000, 0xF83F0000, ARC_OPCODE_ARCv2HS, LOAD, NONE, { RAD, BRAKET, RB, RC, BRAKETdup }, { C_DI16, C_AA8, C_ZZ_D }},
+{ "ldd", 0x20360000, 0xF83F0000, ARC_OPCODE_ARCv2HS, LOAD, LL64, { RAD, BRAKET, RB, RC, BRAKETdup }, { C_DI16, C_AA8, C_ZZ_D }},
 
 /* ldd<.di><.aa> 0,b 00010bbb000000000BBBDaa110111110.  */
-{ "ldd", 0x100001BE, 0xF8FF81FF, ARC_OPCODE_ARCv2HS, LOAD, NONE, { ZA, BRAKET, RB, BRAKETdup }, { C_DI20, C_AA21, C_ZZ_D }},
+{ "ldd", 0x100001BE, 0xF8FF81FF, ARC_OPCODE_ARCv2HS, LOAD, LL64, { ZA, BRAKET, RB, BRAKETdup }, { C_DI20, C_AA21, C_ZZ_D }},
 
 /* ldd<.di><.aa> 0,b,c 00100bbbaa110110DBBBCCCCCC111110.  */
-{ "ldd", 0x2036003E, 0xF83F003F, ARC_OPCODE_ARCv2HS, LOAD, NONE, { ZA, BRAKET, RB, RC, BRAKETdup }, { C_DI16, C_AA8, C_ZZ_D }},
+{ "ldd", 0x2036003E, 0xF83F003F, ARC_OPCODE_ARCv2HS, LOAD, LL64, { ZA, BRAKET, RB, RC, BRAKETdup }, { C_DI16, C_AA8, C_ZZ_D }},
 
 /* ldd<.di><.aa> a,b,s9 00010bbbssssssssSBBBDaa110AAAAAA.  */
-{ "ldd", 0x10000180, 0xF80001C0, ARC_OPCODE_ARCv2HS, LOAD, NONE, { RAD, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_DI20, C_AA21, C_ZZ_D }},
+{ "ldd", 0x10000180, 0xF80001C0, ARC_OPCODE_ARCv2HS, LOAD, LL64, { RAD, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_DI20, C_AA21, C_ZZ_D }},
 
 /* ldd<.di><.aa> 0,b,s9 00010bbbssssssssSBBBDaa110111110.  */
-{ "ldd", 0x100001BE, 0xF80001FF, ARC_OPCODE_ARCv2HS, LOAD, NONE, { ZA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_DI20, C_AA21, C_ZZ_D }},
+{ "ldd", 0x100001BE, 0xF80001FF, ARC_OPCODE_ARCv2HS, LOAD, LL64, { ZA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_DI20, C_AA21, C_ZZ_D }},
 
 /* ldd<.di> a,limm 00010110000000000111DRR110AAAAAA.  */
-{ "ldd", 0x16007180, 0xFFFFF1C0, ARC_OPCODE_ARCv2HS, LOAD, NONE, { RAD, BRAKET, LIMM, BRAKETdup }, { C_DI20, C_ZZ_D }},
+{ "ldd", 0x16007180, 0xFFFFF1C0, ARC_OPCODE_ARCv2HS, LOAD, LL64, { RAD, BRAKET, LIMM, BRAKETdup }, { C_DI20, C_ZZ_D }},
 
 /* ldd<.di><.aa> a,b,limm 00100bbbaa110110DBBB111110AAAAAA.  */
-{ "ldd", 0x20360F80, 0xF83F0FC0, ARC_OPCODE_ARCv2HS, LOAD, NONE, { RAD, BRAKET, RB, LIMM, BRAKETdup }, { C_DI16, C_AA8, C_ZZ_D }},
+{ "ldd", 0x20360F80, 0xF83F0FC0, ARC_OPCODE_ARCv2HS, LOAD, LL64, { RAD, BRAKET, RB, LIMM, BRAKETdup }, { C_DI16, C_AA8, C_ZZ_D }},
 
 /* ldd<.di> a,limm,c 00100110RR110110D111CCCCCCAAAAAA.  */
-{ "ldd", 0x26367000, 0xFF3F7000, ARC_OPCODE_ARCv2HS, LOAD, NONE, { RAD, BRAKET, LIMM, RC, BRAKETdup }, { C_DI16, C_ZZ_D }},
+{ "ldd", 0x26367000, 0xFF3F7000, ARC_OPCODE_ARCv2HS, LOAD, LL64, { RAD, BRAKET, LIMM, RC, BRAKETdup }, { C_DI16, C_ZZ_D }},
 
 /* ldd<.di> 0,limm 00010110000000000111DRR110111110.  */
-{ "ldd", 0x160071BE, 0xFFFFF1FF, ARC_OPCODE_ARCv2HS, LOAD, NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { C_DI20, C_ZZ_D }},
+{ "ldd", 0x160071BE, 0xFFFFF1FF, ARC_OPCODE_ARCv2HS, LOAD, LL64, { ZA, BRAKET, LIMM, BRAKETdup }, { C_DI20, C_ZZ_D }},
 
 /* ldd<.di><.aa> 0,b,limm 00100bbbaa110110DBBB111110111110.  */
-{ "ldd", 0x20360FBE, 0xF83F0FFF, ARC_OPCODE_ARCv2HS, LOAD, NONE, { ZA, BRAKET, RB, LIMM, BRAKETdup }, { C_DI16, C_AA8, C_ZZ_D }},
+{ "ldd", 0x20360FBE, 0xF83F0FFF, ARC_OPCODE_ARCv2HS, LOAD, LL64, { ZA, BRAKET, RB, LIMM, BRAKETdup }, { C_DI16, C_AA8, C_ZZ_D }},
 
 /* ldd<.di> 0,limm,c 00100110RR110110D111CCCCCC111110.  */
-{ "ldd", 0x2636703E, 0xFF3F703F, ARC_OPCODE_ARCv2HS, LOAD, NONE, { ZA, BRAKET, LIMM, RC, BRAKETdup }, { C_DI16, C_ZZ_D }},
+{ "ldd", 0x2636703E, 0xFF3F703F, ARC_OPCODE_ARCv2HS, LOAD, LL64, { ZA, BRAKET, LIMM, RC, BRAKETdup }, { C_DI16, C_ZZ_D }},
 
 /* ldd<.di><.aa> a,limm,s9 00010110ssssssssS111Daa110AAAAAA.  */
-{ "ldd", 0x16007180, 0xFF0071C0, ARC_OPCODE_ARCv2HS, LOAD, NONE, { RAD, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_DI20, C_AA21, C_ZZ_D }},
+{ "ldd", 0x16007180, 0xFF0071C0, ARC_OPCODE_ARCv2HS, LOAD, LL64, { RAD, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_DI20, C_AA21, C_ZZ_D }},
 
 /* ldd<.di><.aa> 0,limm,s9 00010110ssssssssS111Daa110111110.  */
-{ "ldd", 0x160071BE, 0xFF0071FF, ARC_OPCODE_ARCv2HS, LOAD, NONE, { ZA, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_DI20, C_AA21, C_ZZ_D }},
+{ "ldd", 0x160071BE, 0xFF0071FF, ARC_OPCODE_ARCv2HS, LOAD, LL64, { ZA, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_DI20, C_AA21, C_ZZ_D }},
 
 /* ldh_s a,b,c 01100bbbccc10aaa.  */
 { "ldh_s", 0x00006010, 0x0000F818, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { RA_S, BRAKET, RB_S, RC_S, BRAKETdup }, { C_ZZ_H }},
@@ -14649,31 +14649,31 @@
 { "stb_s", 0x0000C060, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { RB_S, BRAKET, SP_S, UIMM7_A32_11_S, BRAKETdup }, { C_ZZ_B }},
 
 /* std<.di><.aa> c,b 00011bbb000000000BBBCCCCCCDaa110.  */
-{ "std", 0x18000006, 0xF8FF8007, ARC_OPCODE_ARCv2HS, STORE, NONE, { RCD, BRAKET, RB, BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }},
+{ "std", 0x18000006, 0xF8FF8007, ARC_OPCODE_ARCv2HS, STORE, LL64, { RCD, BRAKET, RB, BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }},
 
 /* std<.di><.aa> w6,b 00011bbb000000000BBBwwwwwwDaa111.  */
-{ "std", 0x18000007, 0xF8FF8007, ARC_OPCODE_ARCv2HS, STORE, NONE, { W6, BRAKET, RB, BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }},
+{ "std", 0x18000007, 0xF8FF8007, ARC_OPCODE_ARCv2HS, STORE, LL64, { W6, BRAKET, RB, BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }},
 
 /* std<.di><.aa> c,b,s9 00011bbbssssssssSBBBCCCCCCDaa110.  */
-{ "std", 0x18000006, 0xF8000007, ARC_OPCODE_ARCv2HS, STORE, NONE, { RCD, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }},
+{ "std", 0x18000006, 0xF8000007, ARC_OPCODE_ARCv2HS, STORE, LL64, { RCD, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }},
 
 /* std<.di><.aa> w6,b,s9 00011bbbssssssssSBBBwwwwwwDaa111.  */
-{ "std", 0x18000007, 0xF8000007, ARC_OPCODE_ARCv2HS, STORE, NONE, { W6, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }},
+{ "std", 0x18000007, 0xF8000007, ARC_OPCODE_ARCv2HS, STORE, LL64, { W6, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }},
 
 /* std<.di> c,limm 00011110000000000111CCCCCCDRR110.  */
-{ "std", 0x1E007006, 0xFFFFF007, ARC_OPCODE_ARCv2HS, STORE, NONE, { RCD, BRAKET, LIMM, BRAKETdup }, { C_DI26, C_ZZ_D }},
+{ "std", 0x1E007006, 0xFFFFF007, ARC_OPCODE_ARCv2HS, STORE, LL64, { RCD, BRAKET, LIMM, BRAKETdup }, { C_DI26, C_ZZ_D }},
 
 /* std<.di> w6,limm 00011110000000000111wwwwwwDRR111.  */
-{ "std", 0x1E007007, 0xFFFFF007, ARC_OPCODE_ARCv2HS, STORE, NONE, { W6, BRAKET, LIMM, BRAKETdup }, { C_DI26, C_ZZ_D }},
+{ "std", 0x1E007007, 0xFFFFF007, ARC_OPCODE_ARCv2HS, STORE, LL64, { W6, BRAKET, LIMM, BRAKETdup }, { C_DI26, C_ZZ_D }},
 
 /* std<.di><.aa> limm,b,s9 00011bbbssssssssSBBB111110Daa110.  */
-{ "std", 0x18000F86, 0xF8000FC7, ARC_OPCODE_ARCv2HS, STORE, NONE, { LIMM, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }},
+{ "std", 0x18000F86, 0xF8000FC7, ARC_OPCODE_ARCv2HS, STORE, LL64, { LIMM, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }},
 
 /* std<.di><.aa> w6,limm,s9 00011110ssssssssS111wwwwwwDaa111.  */
-{ "std", 0x1E007007, 0xFF007007, ARC_OPCODE_ARCv2HS, STORE, NONE, { W6, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }},
+{ "std", 0x1E007007, 0xFF007007, ARC_OPCODE_ARCv2HS, STORE, LL64, { W6, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }},
 
 /* std<.di><.aa> limm,limm,s9 00011110ssssssssS111111110Daa110.  */
-{ "std", 0x1E007F86, 0xFF007FC7, ARC_OPCODE_ARCv2HS, STORE, NONE, { LIMM, BRAKET, LIMMdup, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }},
+{ "std", 0x1E007F86, 0xFF007FC7, ARC_OPCODE_ARCv2HS, STORE, LL64, { LIMM, BRAKET, LIMMdup, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }},
 
 /* sth_s c,b,u6 10110bbbcccuuuuu.  */
 { "sth_s", 0x0000B000, 0x0000F800, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { C_ZZ_H }},