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| author | Matthew Gretton-Dann <matthew.gretton-dann@arm.com> | 2010-09-17 10:13:41 +0000 |
|---|---|---|
| committer | Matthew Gretton-Dann <matthew.gretton-dann@arm.com> | 2010-09-17 10:13:41 +0000 |
| commit | db472d6ff0f438a21b357249a9b48e4b74498076 (patch) | |
| tree | 89e4361f9af8995b4b1a3375bc119da4dd9ecb03 /opcodes | |
| parent | 8f8067050f5b34b2fb72d810d98206918281b67c (diff) | |
| download | gdb-db472d6ff0f438a21b357249a9b48e4b74498076.zip gdb-db472d6ff0f438a21b357249a9b48e4b74498076.tar.gz gdb-db472d6ff0f438a21b357249a9b48e4b74498076.tar.bz2 | |
2010-09-17 Tejas Belagod <tejas.belagod@arm.com>
* config/tc-arm.c (insns): Change MRC entry to accept APSR_RR instead
of just RR.
2010-09-17 Tejas Belagod <tejas.belagod@arm.com>
* gas/arm/copro.s: Add test for APSR_nzcv as a MRC operand.
* gas/arm/copro.d: Change pc in MRC to disassemble as APSR_nzcv. Also
add disassembly for test added in copro.s
2010-09-17 Tejas Belagod <tejas.belagod@arm.com>
* arm_dis.c (coprocessor_opcodes): Add MRC entry for APSR_nzcv.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 4 | ||||
| -rw-r--r-- | opcodes/arm-dis.c | 1 |
2 files changed, 5 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 992a740..f7d0f53 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,7 @@ +2010-09-17 Tejas Belagod <tejas.belagod@arm.com> + + * arm_dis.c (coprocessor_opcodes): Add MRC entry for APSR_nzcv. + 2010-09-14 Maciej W. Rozycki <macro@codesourcery.com> * mips-opc.c (mips_builtin_opcodes): Add "sync_acquire", diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index b16d50f..831b26c 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -474,6 +474,7 @@ static const struct opcode32 coprocessor_opcodes[] = {ARM_EXT_V5E, 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"}, {ARM_EXT_V5E, 0x0c500000, 0x0ff00000, "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"}, {ARM_EXT_V2, 0x0e000000, 0x0f000010, "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, + {ARM_EXT_V2, 0x0e10f010, 0x0f10f010, "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"}, {ARM_EXT_V2, 0x0e100010, 0x0f100010, "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, {ARM_EXT_V2, 0x0e000010, 0x0f100010, "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"}, {ARM_EXT_V2, 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"}, |