diff options
| author | Alexandre Oliva <aoliva@redhat.com> | 2004-01-16 03:16:00 +0000 |
|---|---|---|
| committer | Alexandre Oliva <aoliva@redhat.com> | 2004-01-16 03:16:00 +0000 |
| commit | d164ea7f0f0ced5cd9f00ae0e33340abac91ae4c (patch) | |
| tree | b667c89daafb0c9ea56bdf6c887d29701d413914 /opcodes | |
| parent | ceef1284d21fb3b522f300132e190abc6923f850 (diff) | |
| download | gdb-d164ea7f0f0ced5cd9f00ae0e33340abac91ae4c.zip gdb-d164ea7f0f0ced5cd9f00ae0e33340abac91ae4c.tar.gz gdb-d164ea7f0f0ced5cd9f00ae0e33340abac91ae4c.tar.bz2 | |
* m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
when loaded into XR registers.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/m10300-opc.c | 6 |
2 files changed, 8 insertions, 3 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index b972bfa..f099f04 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2004-01-16 Alexandre Oliva <aoliva@redhat.com> + + * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended + when loaded into XR registers. + 2004-01-14 Richard Sandiford <rsandifo@redhat.com> * frv-desc.h: Regenerate. diff --git a/opcodes/m10300-opc.c b/opcodes/m10300-opc.c index d1a2ea2..4082b29 100644 --- a/opcodes/m10300-opc.c +++ b/opcodes/m10300-opc.c @@ -1,5 +1,5 @@ /* Assemble Matsushita MN10300 instructions. - Copyright 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 1999, 2000, 2004 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -561,8 +561,8 @@ const struct mn10300_opcode mn10300_opcodes[] = { { "mov", 0xfb080000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, { "mov", 0xfd080000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}}, { "mov", 0xfe080000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, -{ "mov", 0xfbf80000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, XRN02}}, -{ "mov", 0xfdf80000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, XRN02}}, +{ "mov", 0xfbf80000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, XRN02}}, +{ "mov", 0xfdf80000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, XRN02}}, { "mov", 0xfef80000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, XRN02}}, { "mov", 0xfe0e0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM(IMM32_HIGH8_MEM), RN2}}, { "mov", 0xfe1e0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM(IMM32_HIGH8_MEM)}}, |