diff options
| author | Matthew Gretton-Dann <matthew.gretton-dann@arm.com> | 2012-08-24 08:12:45 +0000 |
|---|---|---|
| committer | Matthew Gretton-Dann <matthew.gretton-dann@arm.com> | 2012-08-24 08:12:45 +0000 |
| commit | 91ff78946d8fd0c1eb13a65225b72eea3f8b8c17 (patch) | |
| tree | f3b732407b979b7d519b721166931503170b436a /opcodes | |
| parent | c70a898785be75ec28614634bcea0f9220032dfb (diff) | |
| download | gdb-91ff78946d8fd0c1eb13a65225b72eea3f8b8c17.zip gdb-91ff78946d8fd0c1eb13a65225b72eea3f8b8c17.tar.gz gdb-91ff78946d8fd0c1eb13a65225b72eea3f8b8c17.tar.bz2 | |
* gas/config/tc-arm.c (NEON_ENC_TAB): Add aes entry.
(neon_type_mask): Add N_UNT.
(neon_check_type): Don't always decay typed to untyped sizes.
(do_crypto_2op_1): New function.
(do_aese): Likewise.
(do_aesd): Likewise.
(do_aesmc.8): Likewise.
(do_aesimc.8): Likewise.
(insns): Add AES instructions.
* gas/testsuite/gas/arm/armv8-a+crypto.d: New testcase.
* gas/testsuite/gas/arm/armv8-a+crypto.s: Likewise.
* opcodes/arm-dis.c (neon_opcodes): Add support for AES instructions.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 4 | ||||
| -rw-r--r-- | opcodes/arm-dis.c | 4 |
2 files changed, 8 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 7db883c..5f04b9d 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,9 @@ 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> + * arm-dis.c (neon_opcodes): Add support for AES instructions. + +2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> + * arm-dis.c (coprocessor_opcodes): Add support for HP/DP conversions. diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index c6deac9..ef5c752 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -586,6 +586,10 @@ static const struct opcode32 neon_opcodes[] = /* Two registers, miscellaneous. */ {FPU_NEON_EXT_ARMV8, 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32.f32\t%12-15,22R, %0-3,5R"}, {FPU_NEON_EXT_ARMV8, 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"}, + {FPU_CRYPTO_EXT_ARMV8, 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"}, + {FPU_CRYPTO_EXT_ARMV8, 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"}, + {FPU_CRYPTO_EXT_ARMV8, 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"}, + {FPU_CRYPTO_EXT_ARMV8, 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"}, {FPU_NEON_EXT_V1, 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"}, {FPU_NEON_EXT_V1, 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"}, {FPU_NEON_EXT_V1, 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"}, |