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authorDJ Delorie <dj@redhat.com>2009-06-24 01:44:53 +0000
committerDJ Delorie <dj@redhat.com>2009-06-24 01:44:53 +0000
commit378a0c07cab0852b72230e3a16a66d5d8108af51 (patch)
tree51e39c616fe2d3aa9b57678edf36cc6aa15bed8a /opcodes
parent3ef23cd420ae6184288546c48fba7bde9dccefed (diff)
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[cgen]
* cpu/mep.opc (mep_cgen_insn_supported_asm): New, skip the short version of BSR when assembling VLIW bundles. Use it in mep-asm.c [opcodes] * mep-asm.c: Regenerate. * mep-opc.c: Regenerate. * mep-opc.h: Regenerate.
Diffstat (limited to 'opcodes')
-rw-r--r--opcodes/ChangeLog6
-rw-r--r--opcodes/mep-asm.c1
-rw-r--r--opcodes/mep-opc.c12
-rw-r--r--opcodes/mep-opc.h1
4 files changed, 20 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 5f7c5aa..00d6d3b 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2009-06-23 DJ Delorie <dj@redhat.com>
+
+ * mep-asm.c: Regenerate.
+ * mep-opc.c: Regenerate.
+ * mep-opc.h: Regenerate.
+
2009-06-22 Nick Clifton <nickc@redhat.com>
* po/fi.po: Updated Finish translation.
diff --git a/opcodes/mep-asm.c b/opcodes/mep-asm.c
index 9843cf7..3a8b454 100644
--- a/opcodes/mep-asm.c
+++ b/opcodes/mep-asm.c
@@ -54,6 +54,7 @@ static const char * parse_insn_normal
#include "elf/mep.h"
#define CGEN_VALIDATE_INSN_SUPPORTED
+#define mep_cgen_insn_supported mep_cgen_insn_supported_asm
const char * parse_csrn (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *);
const char * parse_tpreg (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *);
diff --git a/opcodes/mep-opc.c b/opcodes/mep-opc.c
index a9b09a5..aa6c093 100644
--- a/opcodes/mep-opc.c
+++ b/opcodes/mep-opc.c
@@ -163,6 +163,18 @@ mep_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn)
return (ok1 && ok2 && ok3);
}
+
+int
+mep_cgen_insn_supported_asm (CGEN_CPU_DESC cd, const CGEN_INSN *insn)
+{
+ /* If we're assembling VLIW packets, ignore the 12-bit BSR as we
+ can't relax that. The 24-bit BSR is matched instead. */
+ if (insn->base->num == MEP_INSN_BSR12
+ && cgen_bitset_contains (cd->isas, ISA_EXT_COP1_64))
+ return 0;
+
+ return mep_cgen_insn_supported (cd, insn);
+}
/* The hash functions are recorded here to help keep assembler code out of
the disassembler and vice versa. */
diff --git a/opcodes/mep-opc.h b/opcodes/mep-opc.h
index 2795519..fe8db0f 100644
--- a/opcodes/mep-opc.h
+++ b/opcodes/mep-opc.h
@@ -96,6 +96,7 @@ extern CGEN_ATTR_VALUE_BITSET_TYPE mep_all_cop_isas_mask;
)
extern int mep_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *);
+extern int mep_cgen_insn_supported_asm (CGEN_CPU_DESC, const CGEN_INSN *);
/* -- asm.c */
/* Enum declaration for mep instruction types. */