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| author | Zack Weinberg <zackw@panix.com> | 2003-12-10 22:12:50 +0000 |
|---|---|---|
| committer | Zack Weinberg <zackw@panix.com> | 2003-12-10 22:12:50 +0000 |
| commit | 1f6c9eb08453736ce145144dbdd0b3727e2c5592 (patch) | |
| tree | f37591828f9f05c6d90404b1fd903a36bbf2125d /opcodes | |
| parent | 7ae4c3a566beba00e16dd10bb69414ffc214dcbb (diff) | |
| download | gdb-1f6c9eb08453736ce145144dbdd0b3727e2c5592.zip gdb-1f6c9eb08453736ce145144dbdd0b3727e2c5592.tar.gz gdb-1f6c9eb08453736ce145144dbdd0b3727e2c5592.tar.bz2 | |
opcodes:
* ppc-opc.c (MO): Make optional.
(RAO, RSO, SHO): New optional forms of RA, RS, SH operands.
(tlbwe): Accept for both PPC403 and BOOKE. Make all operands optional.
gas:
* tc-ppc.c (md_assemble): Rewrite comment about optional operands
to indicate that 'all or none' is also handled. Pluralize a
word in another comment.
gas/testsuite:
* gas/ppc/booke.s: Add two more forms of the mbar instruction
and three forms of the tlbwe instruction.
* gas/ppc/booke.d: Update to match.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 6 | ||||
| -rw-r--r-- | opcodes/ppc-opc.c | 23 |
2 files changed, 23 insertions, 6 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 1d181fd..046e268 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,9 @@ +2003-12-10 Zack Weinberg <zack@codesourcery.com> + + * ppc-opc.c (MO): Make optional. + (RAO, RSO, SHO): New optional forms of RA, RS, SH operands. + (tlbwe): Accept for both PPC403 and BOOKE. Make all operands optional. + 2003-12-05 Ricardo Anguiano <anguiano@codesourcery.com> Mark Mitchell <mark@codesourcery.com> Richard Earnshaw <rearnsha@arm.com> diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index 0da244c..d011edf 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -344,7 +344,7 @@ const struct powerpc_operand powerpc_operands[] = /* The MO field in an mbar instruction. */ #define MO MB6 + 1 - { 5, 21, 0, 0, 0 }, + { 5, 21, 0, 0, PPC_OPERAND_OPTIONAL }, /* The NB field in an X form instruction. The value 32 is stored as 0. */ @@ -384,8 +384,12 @@ const struct powerpc_operand powerpc_operands[] = #define RAS RAM + 1 { 5, 16, insert_ras, 0, PPC_OPERAND_GPR }, + /* The RA field of the tlbwe instruction, which is optional. */ +#define RAO RAS + 1 + { 5, 16, 0, 0, PPC_OPERAND_GPR|PPC_OPERAND_OPTIONAL }, + /* The RB field in an X, XO, M, or MDS form instruction. */ -#define RB RAS + 1 +#define RB RAO + 1 #define RB_MASK (0x1f << 11) { 5, 11, 0, 0, PPC_OPERAND_GPR }, @@ -413,8 +417,12 @@ const struct powerpc_operand powerpc_operands[] = #define RTQ RSQ + 1 { 5, 21, insert_rtq, 0, PPC_OPERAND_GPR }, + /* The RS field of the tlbwe instruction, which is optional. */ +#define RSO RTQ + 1 + { 5, 21, 0, 0, PPC_OPERAND_GPR|PPC_OPERAND_OPTIONAL }, + /* The SH field in an X or M form instruction. */ -#define SH RTQ + 1 +#define SH RSO + 1 #define SH_MASK (0x1f << 11) { 5, 11, 0, 0, 0 }, @@ -423,8 +431,12 @@ const struct powerpc_operand powerpc_operands[] = #define SH6_MASK ((0x1f << 11) | (1 << 1)) { 6, 1, insert_sh6, extract_sh6, 0 }, + /* The SH field of the tlbwe instruction, which is optional. */ +#define SHO SH6 + 1 + { 5, 11,0, 0, PPC_OPERAND_OPTIONAL }, + /* The SI field in a D form instruction. */ -#define SI SH6 + 1 +#define SI SHO + 1 { 16, 0, 0, 0, PPC_OPERAND_SIGNED }, /* The SI field in a D form instruction when we accept a wide range @@ -4256,8 +4268,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } }, { "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } }, -{ "tlbwe", X(31,978), X_MASK, BOOKE, { 0 } }, -{ "tlbwe", X(31,978), X_MASK, PPC403, { RS, RA, SH } }, +{ "tlbwe", X(31,978), X_MASK, PPC403|BOOKE, { RSO, RAO, SHO } }, { "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } }, { "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } }, |