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| author | Nick Clifton <nickc@redhat.com> | 2016-02-04 09:55:10 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2016-02-04 09:55:10 +0000 |
| commit | c1d9289fef41b82aa22f63f74aa8e730ec898d3c (patch) | |
| tree | e477a2b77b58e8d51a359f02cba511bc00f85873 /opcodes | |
| parent | 1b18aa1e79a0b343087d08075f117e821c33b930 (diff) | |
| download | gdb-c1d9289fef41b82aa22f63f74aa8e730ec898d3c.zip gdb-c1d9289fef41b82aa22f63f74aa8e730ec898d3c.tar.gz gdb-c1d9289fef41b82aa22f63f74aa8e730ec898d3c.tar.bz2 | |
Fix the encoding of the MSP430's RRUX instruction.
PR target/19561
opcdoe * msp430-dis.c (print_insn_msp430): Add a special case for
decoding an RRC instruction with the ZC bit set in the extension
word.
include * opcode/msp430.h (IGNORE_CARRY_BIT): New define.
(RRUX): Synthesise using case 2 rather than 7.
gas * config/tc-msp430.c (msp430_operands): Remove case 7. Use case 2
to handle encoding of RRUX instruction.
* testsuite/gas/msp430/msp430x.s: Add more tests of the extended
shift instructions.
* testsuite/gas/msp430/msp430x.d: Update expected disassembly.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 7 | ||||
| -rw-r--r-- | opcodes/msp430-dis.c | 9 |
2 files changed, 14 insertions, 2 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 83cbe6f..f706739 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,10 @@ +2016-02-04 Nick Clifton <nickc@redhat.com> + + PR target/19561 + * msp430-dis.c (print_insn_msp430): Add a special case for + decoding an RRC instruction with the ZC bit set in the extension + word. + 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com> * cgen-ibld.in (insert_normal): Rework calculation of shift. diff --git a/opcodes/msp430-dis.c b/opcodes/msp430-dis.c index d7e8d8a..676a2d8 100644 --- a/opcodes/msp430-dis.c +++ b/opcodes/msp430-dis.c @@ -1102,7 +1102,7 @@ print_insn_msp430 (bfd_vma addr, disassemble_info *info) } else if (extension_word) { - if (extension_word & (1 << 6)) + if (extension_word & BYTE_OPERATION) bc = ".w"; else { @@ -1181,7 +1181,12 @@ print_insn_msp430 (bfd_vma addr, disassemble_info *info) prin (stream, "rpt #%d { ", (extension_word & 0xf) + 1); } - if (extension_word && opcode->name[strlen (opcode->name) - 1] != 'x') + /* Special case: RRC with an extension word and the ZC bit set is actually RRU. */ + if (extension_word + && (extension_word & IGNORE_CARRY_BIT) + && strcmp (opcode->name, "rrc") == 0) + (*prin) (stream, "rrux%s", bc); + else if (extension_word && opcode->name[strlen (opcode->name) - 1] != 'x') (*prin) (stream, "%sx%s", opcode->name, bc); else (*prin) (stream, "%s%s", opcode->name, bc); |