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| author | H.J. Lu <hjl.tools@gmail.com> | 2010-07-05 17:14:22 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2010-07-05 17:14:22 +0000 |
| commit | d7d9a9f820395ecfe06c80fa12bf9cf60f455482 (patch) | |
| tree | 8dc34892e58fd2825ff51c53390e7a2e88f03b1a /opcodes | |
| parent | 77321f536016efc2e18fbef88016b1fbad25afd1 (diff) | |
| download | gdb-d7d9a9f820395ecfe06c80fa12bf9cf60f455482.zip gdb-d7d9a9f820395ecfe06c80fa12bf9cf60f455482.tar.gz gdb-d7d9a9f820395ecfe06c80fa12bf9cf60f455482.tar.bz2 | |
Replace rdrnd with rdrand.
gas/testsuite/
2010-07-05 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (June, 2010)
* gas/i386/rdrnd.s: Replace rdrnd with rdrand.
* gas/i386/rdrnd-intel.d: Likewise.
* gas/i386/rdrnd.d: Likewise.
* gas/i386/x86-64-rdrnd-intel.d: Likewise.
* gas/i386/x86-64-rdrnd.d: Likewise.
* gas/i386/x86-64-rdrnd.s: Likewise.
opcodes/
2010-07-05 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (June, 2010)
* i386-dis.c (mod_table): Replace rdrnd with rdrand.
* i386-opc.tbl: Likewise.
* i386-tbl.h: Regenerated.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 7 | ||||
| -rw-r--r-- | opcodes/i386-dis.c | 2 | ||||
| -rw-r--r-- | opcodes/i386-opc.tbl | 2 | ||||
| -rw-r--r-- | opcodes/i386-tbl.h | 2 |
4 files changed, 10 insertions, 3 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 96fffad..6b3b56c 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,12 @@ 2010-07-05 H.J. Lu <hongjiu.lu@intel.com> + AVX Programming Reference (June, 2010) + * i386-dis.c (mod_table): Replace rdrnd with rdrand. + * i386-opc.tbl: Likewise. + * i386-tbl.h: Regenerated. + +2010-07-05 H.J. Lu <hongjiu.lu@intel.com> + * i386-opc.h (CpuFSGSBase): Fix a typo in comments. 2010-07-03 Andreas Schwab <schwab@linux-m68k.org> diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index 224540e..1f9d01d 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -10450,7 +10450,7 @@ static const struct dis386 mod_table[][2] = { { /* MOD_0FC7_REG_6 */ { PREFIX_TABLE (PREFIX_0FC7_REG_6) }, - { "rdrnd", { Ev } }, + { "rdrand", { Ev } }, }, { /* MOD_0FC7_REG_7 */ diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index ef48720..010a632 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -2394,7 +2394,7 @@ vpclmulhqhqdq, 3, 0x6644, 0x11, 1, CpuAVX|CpuPCLMUL, Modrm|Vex|VexOpcode=2|VexVV rdfsbase, 1, 0xf30fae, 0x0, 2, CpuFSGSBase, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64 } rdgsbase, 1, 0xf30fae, 0x1, 2, CpuFSGSBase, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64 } -rdrnd, 1, 0xfc7, 0x6, 2, CpuRdRnd, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Reg64 } +rdrand, 1, 0xfc7, 0x6, 2, CpuRdRnd, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Reg64 } wrfsbase, 1, 0xf30fae, 0x2, 2, CpuFSGSBase, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64 } wrgsbase, 1, 0xf30fae, 0x3, 2, CpuFSGSBase, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64 } vcvtph2ps, 2, 0x6613, None, 1, CpuF16C, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h index 1bc2e53..806ad6e 100644 --- a/opcodes/i386-tbl.h +++ b/opcodes/i386-tbl.h @@ -27311,7 +27311,7 @@ const insn_template i386_optab[] = { { { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "rdrnd", 1, 0xfc7, 0x6, 2, + { "rdrand", 1, 0xfc7, 0x6, 2, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }, |