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| author | Ken Raeburn <raeburn@cygnus> | 1997-10-28 23:03:12 +0000 |
|---|---|---|
| committer | Ken Raeburn <raeburn@cygnus> | 1997-10-28 23:03:12 +0000 |
| commit | a0539c6102cfebe84a82a5f21c4899e92b4e1adb (patch) | |
| tree | 8d71847f1625cf5863502157792fa7827f164ee6 /opcodes | |
| parent | 8357d96073d237043a0509895384c543afaa64d6 (diff) | |
| download | gdb-a0539c6102cfebe84a82a5f21c4899e92b4e1adb.zip gdb-a0539c6102cfebe84a82a5f21c4899e92b4e1adb.tar.gz gdb-a0539c6102cfebe84a82a5f21c4899e92b4e1adb.tar.bz2 | |
* mips-opc.c (ffc, ffs): Fix mask.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 4 | ||||
| -rw-r--r-- | opcodes/mips-opc.c | 4 |
2 files changed, 6 insertions, 2 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 67cdb3c..665d1d1 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,7 @@ +Tue Oct 28 17:59:32 1997 Ken Raeburn <raeburn@cygnus.com> + + * mips-opc.c (ffc, ffs): Fix mask. + start-sanitize-d30v Tue Oct 28 16:34:54 1997 Michael Meissner <meissner@cygnus.com> diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index a838426..03305a8 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -555,7 +555,7 @@ const struct mips_opcode mips_builtin_opcodes[] = { /* start-sanitize-r5900 */ {"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, T5 }, /* end-sanitize-r5900 */ -{"ffc", "d,v", 0x0000000b, 0xfc0007ff, WR_d|RD_s,L1 }, +{"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_d|RD_s,L1 }, {"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I4 }, {"movn.s", "D,S,t", 0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, I4 }, {"movt", "d,s,N", 0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC, I4 }, @@ -565,7 +565,7 @@ const struct mips_opcode mips_builtin_opcodes[] = { /* start-sanitize-r5900 */ {"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, T5 }, /* end-sanitize-r5900 */ -{"ffs", "d,v", 0x0000000a, 0xfc0007ff, WR_d|RD_s,L1 }, +{"ffs", "d,v", 0x0000000a, 0xfc1f07ff, WR_d|RD_s,L1 }, {"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I4 }, {"movz.s", "D,S,t", 0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, I4 }, /* start-sanitize-vr5400 */ |