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authorGeoffrey Keating <geoffk@geoffk.org>2001-12-08 03:46:03 +0000
committerGeoffrey Keating <geoffk@geoffk.org>2001-12-08 03:46:03 +0000
commit93fbbb04b887de8b1e56bf3de66581082d2b0e8b (patch)
treeb4692062975e5a14495c81b43fcaa78b02d859fb /opcodes
parent4b2c32f8e9216d637ef7f5a39e2f4afe0aae41af (diff)
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Index: bfd/ChangeLog
2001-12-07 Geoffrey Keating <geoffk@redhat.com> Richard Henderson <rth@redhat.com> Corinna Vinschen <vinschen@redhat.com> * Makefile.am: Add support for xstormy16. * archures.c: Add support for xstormy16. * config.bfd: Add support for xstormy16. * configure.in: Add support for xstormy16. * reloc.c: Add support for xstormy16. * targets.c: Add support for xstormy16. * cpu-xstormy16.c: New file. * elf32-xstormy16.c: New file. * Makefile.in: Regenerated. * bfd-in2.h: Regenerated. * configure: Regenerated. * libbfd.h: Regenerated. Index: binutils/ChangeLog 2001-12-07 Geoffrey Keating <geoffk@redhat.com> * readelf.c (guess_is_rela): Add support for stormy16. (dump_relocations): Likewise. (get_machine_name): Likewise. Index: gas/ChangeLog 2001-12-07 Geoffrey Keating <geoffk@redhat.com> Richard Henderson <rth@redhat.com> * configure.in: Add support for xstormy16. * configure: Regenerated. * Makefile.am: Add support for xstormy16. * Makefile.in: Regenerated. * config/tc-xstormy16.c: New file. * config/tc-xstormy16.h: New file. Index: gas/testsuite/ChangeLog 2001-12-07 Geoffrey Keating <geoffk@redhat.com> matthew green <mrg@redhat.com> * gas/xstormy16/allinsn.d: New file. * gas/xstormy16/allinsn.exp: New file. * gas/xstormy16/allinsn.s: New file. * gas/xstormy16/allinsn.sh: New file. * gas/xstormy16/gcc.d: New file. * gas/xstormy16/gcc.s: New file. * gas/xstormy16/gcc.sh: New file. * gas/xstormy16/reloc-1.d: New file. * gas/xstormy16/reloc-1.s: New file. * gas/xstormy16/reloc-2.d: New file. * gas/xstormy16/reloc-2.s: New file. Index: ld/ChangeLog 2001-12-07 Geoffrey Keating <geoffk@redhat.com> Richard Henderson <rth@redhat.com> * Makefile.am: Add support for xstormy16. * configure.tgt: Add support for xstormy16. * Makefile.in: Regenerate. * emulparams/elf32xstormy16.sh: New file. * scripttempl/xstormy16.sc: New file. Index: opcodes/ChangeLog 2001-12-07 Geoffrey Keating <geoffk@redhat.com> * Makefile.am: Add support for xstormy16. * Makefile.in: Regenerate. * configure.in: Add support for xstormy16. * configure: Regenerate. * disassemble.c: Add support for xstormy16. * xstormy16-asm.c: New generated file. * xstormy16-desc.c: New generated file. * xstormy16-desc.h: New generated file. * xstormy16-dis.c: New generated file. * xstormy16-ibld.c: New generated file. * xstormy16-opc.c: New generated file. * xstormy16-opc.h: New generated file. Index: include/ChangeLog 2001-12-07 Geoffrey Keating <geoffk@redhat.com> * dis-asm.h (print_insn_xstormy16): Declare. Index: include/elf/ChangeLog 2001-12-07 Geoffrey Keating <geoffk@redhat.com> Richard Henderson <rth@redhat.com> * common.h (EM_XSTORMY16): Define. * xstormy16.h: New file.
Diffstat (limited to 'opcodes')
-rw-r--r--opcodes/ChangeLog15
-rw-r--r--opcodes/Makefile.am19
-rw-r--r--opcodes/Makefile.in25
-rwxr-xr-xopcodes/configure373
-rw-r--r--opcodes/configure.in1
-rw-r--r--opcodes/disassemble.c6
-rw-r--r--opcodes/xstormy16-asm.c659
-rw-r--r--opcodes/xstormy16-desc.c1399
-rw-r--r--opcodes/xstormy16-desc.h289
-rw-r--r--opcodes/xstormy16-dis.c565
-rw-r--r--opcodes/xstormy16-ibld.c1246
-rw-r--r--opcodes/xstormy16-opc.c1171
-rw-r--r--opcodes/xstormy16-opc.h136
13 files changed, 5714 insertions, 190 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index da7497f..383e52a 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,18 @@
+2001-12-07 Geoffrey Keating <geoffk@redhat.com>
+
+ * Makefile.am: Add support for xstormy16.
+ * Makefile.in: Regenerate.
+ * configure.in: Add support for xstormy16.
+ * configure: Regenerate.
+ * disassemble.c: Add support for xstormy16.
+ * xstormy16-asm.c: New generated file.
+ * xstormy16-desc.c: New generated file.
+ * xstormy16-desc.h: New generated file.
+ * xstormy16-dis.c: New generated file.
+ * xstormy16-ibld.c: New generated file.
+ * xstormy16-opc.c: New generated file.
+ * xstormy16-opc.h: New generated file.
+
2001-12-06 Richard Henderson <rth@redhat.com>
* alpha-opc.c (alpha_opcodes): Add wh64en.
diff --git a/opcodes/Makefile.am b/opcodes/Makefile.am
index e42c41d..ee7b19f 100644
--- a/opcodes/Makefile.am
+++ b/opcodes/Makefile.am
@@ -32,6 +32,7 @@ HFILES = \
ia64-asmtab.h \
ia64-opc.h \
w65-opc.h \
+ xstormy16-desc.h xstormy16-opc.h \
z8k-opc.h
# C source files that correspond to .o's.
@@ -126,6 +127,11 @@ CFILES = \
v850-opc.c \
vax-dis.c \
w65-dis.c \
+ xstormy16-asm.c \
+ xstormy16-desc.c \
+ xstormy16-dis.c \
+ xstormy16-ibld.c \
+ xstormy16-opc.c \
z8k-dis.c \
z8kgen.c
@@ -209,6 +215,11 @@ ALL_MACHINES = \
v850-opc.lo \
vax-dis.lo \
w65-dis.lo \
+ xstormy16-asm.lo \
+ xstormy16-desc.lo \
+ xstormy16-dis.lo \
+ xstormy16-ibld.lo \
+ xstormy16-opc.lo \
z8k-dis.lo
OFILES = @BFD_MACHINES@
@@ -253,6 +264,7 @@ config.status: $(srcdir)/configure $(srcdir)/../bfd/configure.in
CLEANFILES = \
stamp-m32r stamp-fr30 stamp-openrisc \
+ stamp-xstormy16 \
libopcodes.a stamp-lib dep.sed DEP DEPA DEP1 DEP2
@@ -272,10 +284,12 @@ if CGEN_MAINT
M32R_DEPS = stamp-m32r
FR30_DEPS = stamp-fr30
OPENRISC_DEPS = stamp-openrisc
+XSTORMY16_DEPS = stamp-xstormy16
else
M32R_DEPS =
FR30_DEPS =
OPENRISC_DEPS =
+XSTORMY16_DEPS =
endif
run-cgen:
@@ -301,6 +315,11 @@ $(srcdir)/openrisc-desc.h $(srcdir)/openrisc-desc.c $(srcdir)/openrisc-opc.h $(s
stamp-openrisc: $(CGENDEPS) $(CPUDIR)/openrisc.cpu $(CPUDIR)/openrisc.opc
$(MAKE) run-cgen arch=openrisc prefix=openrisc options= extrafiles=
+$(srcdir)/xstormy16-desc.h $(srcdir)/xstormy16-desc.c $(srcdir)/xstormy16-opc.h $(srcdir)/xstormy16-opc.c $(srcdir)/xstormy16-ibld.c $(srcdir)/xstormy16-asm.c $(srcdir)/xstormy16-dis.c: $(XSTORMY16_DEPS)
+ @true
+stamp-xstormy16: $(CGENDEPS) $(CPUDIR)/xstormy16.cpu $(CPUDIR)/xstormy16.opc
+ $(MAKE) run-cgen arch=xstormy16 prefix=xstormy16 options= extrafiles=
+
ia64-gen: ia64-gen.o
$(LINK) ia64-gen.o $(LIBIBERTY)
diff --git a/opcodes/Makefile.in b/opcodes/Makefile.in
index c79ebe2..aeeb9e5 100644
--- a/opcodes/Makefile.in
+++ b/opcodes/Makefile.in
@@ -1,6 +1,6 @@
-# Makefile.in generated automatically by automake 1.4-p5 from Makefile.am
+# Makefile.in generated automatically by automake 1.4 from Makefile.am
-# Copyright (C) 1994, 1995-8, 1999, 2001 Free Software Foundation, Inc.
+# Copyright (C) 1994, 1995-8, 1999 Free Software Foundation, Inc.
# This Makefile.in is free software; the Free Software Foundation
# gives unlimited permission to copy and/or distribute it,
# with or without modifications, as long as this notice is preserved.
@@ -142,6 +142,7 @@ HFILES = \
ia64-asmtab.h \
ia64-opc.h \
w65-opc.h \
+ xstormy16-desc.h xstormy16-opc.h \
z8k-opc.h
@@ -237,6 +238,11 @@ CFILES = \
v850-opc.c \
vax-dis.c \
w65-dis.c \
+ xstormy16-asm.c \
+ xstormy16-desc.c \
+ xstormy16-dis.c \
+ xstormy16-ibld.c \
+ xstormy16-opc.c \
z8k-dis.c \
z8kgen.c
@@ -321,6 +327,11 @@ ALL_MACHINES = \
v850-opc.lo \
vax-dis.lo \
w65-dis.lo \
+ xstormy16-asm.lo \
+ xstormy16-desc.lo \
+ xstormy16-dis.lo \
+ xstormy16-ibld.lo \
+ xstormy16-opc.lo \
z8k-dis.lo
@@ -344,6 +355,7 @@ POTFILES = $(HFILES) $(CFILES)
CLEANFILES = \
stamp-m32r stamp-fr30 stamp-openrisc \
+ stamp-xstormy16 \
libopcodes.a stamp-lib dep.sed DEP DEPA DEP1 DEP2
@@ -365,6 +377,8 @@ CGENDEPS = ../cgen/stamp-cgen \
@CGEN_MAINT_FALSE@FR30_DEPS =
@CGEN_MAINT_TRUE@OPENRISC_DEPS = @CGEN_MAINT_TRUE@stamp-openrisc
@CGEN_MAINT_FALSE@OPENRISC_DEPS =
+@CGEN_MAINT_TRUE@XSTORMY16_DEPS = @CGEN_MAINT_TRUE@stamp-xstormy16
+@CGEN_MAINT_FALSE@XSTORMY16_DEPS =
ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
mkinstalldirs = $(SHELL) $(top_srcdir)/../mkinstalldirs
CONFIG_HEADER = config.h
@@ -558,7 +572,7 @@ maintainer-clean-recursive:
dot_seen=no; \
rev=''; list='$(SUBDIRS)'; for subdir in $$list; do \
rev="$$subdir $$rev"; \
- test "$$subdir" != "." || dot_seen=yes; \
+ test "$$subdir" = "." && dot_seen=yes; \
done; \
test "$$dot_seen" = "no" && rev=". $$rev"; \
target=`echo $@ | sed s/-recursive//`; \
@@ -812,6 +826,11 @@ $(srcdir)/openrisc-desc.h $(srcdir)/openrisc-desc.c $(srcdir)/openrisc-opc.h $(s
stamp-openrisc: $(CGENDEPS) $(CPUDIR)/openrisc.cpu $(CPUDIR)/openrisc.opc
$(MAKE) run-cgen arch=openrisc prefix=openrisc options= extrafiles=
+$(srcdir)/xstormy16-desc.h $(srcdir)/xstormy16-desc.c $(srcdir)/xstormy16-opc.h $(srcdir)/xstormy16-opc.c $(srcdir)/xstormy16-ibld.c $(srcdir)/xstormy16-asm.c $(srcdir)/xstormy16-dis.c: $(XSTORMY16_DEPS)
+ @true
+stamp-xstormy16: $(CGENDEPS) $(CPUDIR)/xstormy16.cpu $(CPUDIR)/xstormy16.opc
+ $(MAKE) run-cgen arch=xstormy16 prefix=xstormy16 options= extrafiles=
+
ia64-gen: ia64-gen.o
$(LINK) ia64-gen.o $(LIBIBERTY)
diff --git a/opcodes/configure b/opcodes/configure
index e06aaba..cc7fc7c 100755
--- a/opcodes/configure
+++ b/opcodes/configure
@@ -55,6 +55,7 @@ program_suffix=NONE
program_transform_name=s,x,x,
silent=
site=
+sitefile=
srcdir=
target=NONE
verbose=
@@ -169,6 +170,7 @@ Configuration:
--help print this message
--no-create do not create output files
--quiet, --silent do not print \`checking...' messages
+ --site-file=FILE use FILE as the site file
--version print the version of autoconf that created configure
Directory and file names:
--prefix=PREFIX install architecture-independent files in PREFIX
@@ -339,6 +341,11 @@ EOF
-site=* | --site=* | --sit=*)
site="$ac_optarg" ;;
+ -site-file | --site-file | --site-fil | --site-fi | --site-f)
+ ac_prev=sitefile ;;
+ -site-file=* | --site-file=* | --site-fil=* | --site-fi=* | --site-f=*)
+ sitefile="$ac_optarg" ;;
+
-srcdir | --srcdir | --srcdi | --srcd | --src | --sr)
ac_prev=srcdir ;;
-srcdir=* | --srcdir=* | --srcdi=* | --srcd=* | --src=* | --sr=*)
@@ -504,12 +511,16 @@ fi
srcdir=`echo "${srcdir}" | sed 's%\([^/]\)/*$%\1%'`
# Prefer explicitly selected file to automatically selected ones.
-if test -z "$CONFIG_SITE"; then
- if test "x$prefix" != xNONE; then
- CONFIG_SITE="$prefix/share/config.site $prefix/etc/config.site"
- else
- CONFIG_SITE="$ac_default_prefix/share/config.site $ac_default_prefix/etc/config.site"
+if test -z "$sitefile"; then
+ if test -z "$CONFIG_SITE"; then
+ if test "x$prefix" != xNONE; then
+ CONFIG_SITE="$prefix/share/config.site $prefix/etc/config.site"
+ else
+ CONFIG_SITE="$ac_default_prefix/share/config.site $ac_default_prefix/etc/config.site"
+ fi
fi
+else
+ CONFIG_SITE="$sitefile"
fi
for ac_site_file in $CONFIG_SITE; do
if test -r "$ac_site_file"; then
@@ -548,12 +559,12 @@ else
fi
echo $ac_n "checking for Cygwin environment""... $ac_c" 1>&6
-echo "configure:552: checking for Cygwin environment" >&5
+echo "configure:563: checking for Cygwin environment" >&5
if eval "test \"`echo '$''{'ac_cv_cygwin'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
-#line 557 "configure"
+#line 568 "configure"
#include "confdefs.h"
int main() {
@@ -564,7 +575,7 @@ int main() {
return __CYGWIN__;
; return 0; }
EOF
-if { (eval echo configure:568: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+if { (eval echo configure:579: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
rm -rf conftest*
ac_cv_cygwin=yes
else
@@ -581,19 +592,19 @@ echo "$ac_t""$ac_cv_cygwin" 1>&6
CYGWIN=
test "$ac_cv_cygwin" = yes && CYGWIN=yes
echo $ac_n "checking for mingw32 environment""... $ac_c" 1>&6
-echo "configure:585: checking for mingw32 environment" >&5
+echo "configure:596: checking for mingw32 environment" >&5
if eval "test \"`echo '$''{'ac_cv_mingw32'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
-#line 590 "configure"
+#line 601 "configure"
#include "confdefs.h"
int main() {
return __MINGW32__;
; return 0; }
EOF
-if { (eval echo configure:597: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+if { (eval echo configure:608: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
rm -rf conftest*
ac_cv_mingw32=yes
else
@@ -658,7 +669,7 @@ else { echo "configure: error: can not run $ac_config_sub" 1>&2; exit 1; }
fi
echo $ac_n "checking host system type""... $ac_c" 1>&6
-echo "configure:662: checking host system type" >&5
+echo "configure:673: checking host system type" >&5
host_alias=$host
case "$host_alias" in
@@ -679,7 +690,7 @@ host_os=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'`
echo "$ac_t""$host" 1>&6
echo $ac_n "checking target system type""... $ac_c" 1>&6
-echo "configure:683: checking target system type" >&5
+echo "configure:694: checking target system type" >&5
target_alias=$target
case "$target_alias" in
@@ -697,7 +708,7 @@ target_os=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'`
echo "$ac_t""$target" 1>&6
echo $ac_n "checking build system type""... $ac_c" 1>&6
-echo "configure:701: checking build system type" >&5
+echo "configure:712: checking build system type" >&5
build_alias=$build
case "$build_alias" in
@@ -721,7 +732,7 @@ test "$host_alias" != "$target_alias" &&
echo $ac_n "checking for strerror in -lcposix""... $ac_c" 1>&6
-echo "configure:725: checking for strerror in -lcposix" >&5
+echo "configure:736: checking for strerror in -lcposix" >&5
ac_lib_var=`echo cposix'_'strerror | sed 'y%./+-%__p_%'`
if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
@@ -729,7 +740,7 @@ else
ac_save_LIBS="$LIBS"
LIBS="-lcposix $LIBS"
cat > conftest.$ac_ext <<EOF
-#line 733 "configure"
+#line 744 "configure"
#include "confdefs.h"
/* Override any gcc2 internal prototype to avoid an error. */
/* We use char because int might match the return type of a gcc2
@@ -740,7 +751,7 @@ int main() {
strerror()
; return 0; }
EOF
-if { (eval echo configure:744: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:755: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
rm -rf conftest*
eval "ac_cv_lib_$ac_lib_var=yes"
else
@@ -780,7 +791,7 @@ BFD_VERSION=`sed -n -e 's/^.._INIT_AUTOMAKE.*,[ ]*\([^ ]*\)[ ]*).*/\1/p' < ${
# SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff"
# ./install, which can be erroneously created by make from ./install.sh.
echo $ac_n "checking for a BSD compatible install""... $ac_c" 1>&6
-echo "configure:784: checking for a BSD compatible install" >&5
+echo "configure:795: checking for a BSD compatible install" >&5
if test -z "$INSTALL"; then
if eval "test \"`echo '$''{'ac_cv_path_install'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
@@ -833,7 +844,7 @@ test -z "$INSTALL_SCRIPT" && INSTALL_SCRIPT='${INSTALL_PROGRAM}'
test -z "$INSTALL_DATA" && INSTALL_DATA='${INSTALL} -m 644'
echo $ac_n "checking whether build environment is sane""... $ac_c" 1>&6
-echo "configure:837: checking whether build environment is sane" >&5
+echo "configure:848: checking whether build environment is sane" >&5
# Just in case
sleep 1
echo timestamp > conftestfile
@@ -890,7 +901,7 @@ test "$program_suffix" != NONE &&
test "$program_transform_name" = "" && program_transform_name="s,x,x,"
echo $ac_n "checking whether ${MAKE-make} sets \${MAKE}""... $ac_c" 1>&6
-echo "configure:894: checking whether ${MAKE-make} sets \${MAKE}" >&5
+echo "configure:905: checking whether ${MAKE-make} sets \${MAKE}" >&5
set dummy ${MAKE-make}; ac_make=`echo "$2" | sed 'y%./+-%__p_%'`
if eval "test \"`echo '$''{'ac_cv_prog_make_${ac_make}_set'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
@@ -936,7 +947,7 @@ EOF
missing_dir=`cd $ac_aux_dir && pwd`
echo $ac_n "checking for working aclocal""... $ac_c" 1>&6
-echo "configure:940: checking for working aclocal" >&5
+echo "configure:951: checking for working aclocal" >&5
# Run test in a subshell; some versions of sh will print an error if
# an executable is not found, even if stderr is redirected.
# Redirect stdin to placate older versions of autoconf. Sigh.
@@ -949,7 +960,7 @@ else
fi
echo $ac_n "checking for working autoconf""... $ac_c" 1>&6
-echo "configure:953: checking for working autoconf" >&5
+echo "configure:964: checking for working autoconf" >&5
# Run test in a subshell; some versions of sh will print an error if
# an executable is not found, even if stderr is redirected.
# Redirect stdin to placate older versions of autoconf. Sigh.
@@ -962,7 +973,7 @@ else
fi
echo $ac_n "checking for working automake""... $ac_c" 1>&6
-echo "configure:966: checking for working automake" >&5
+echo "configure:977: checking for working automake" >&5
# Run test in a subshell; some versions of sh will print an error if
# an executable is not found, even if stderr is redirected.
# Redirect stdin to placate older versions of autoconf. Sigh.
@@ -975,7 +986,7 @@ else
fi
echo $ac_n "checking for working autoheader""... $ac_c" 1>&6
-echo "configure:979: checking for working autoheader" >&5
+echo "configure:990: checking for working autoheader" >&5
# Run test in a subshell; some versions of sh will print an error if
# an executable is not found, even if stderr is redirected.
# Redirect stdin to placate older versions of autoconf. Sigh.
@@ -988,7 +999,7 @@ else
fi
echo $ac_n "checking for working makeinfo""... $ac_c" 1>&6
-echo "configure:992: checking for working makeinfo" >&5
+echo "configure:1003: checking for working makeinfo" >&5
# Run test in a subshell; some versions of sh will print an error if
# an executable is not found, even if stderr is redirected.
# Redirect stdin to placate older versions of autoconf. Sigh.
@@ -1011,7 +1022,7 @@ fi
# Extract the first word of "${ac_tool_prefix}ar", so it can be a program name with args.
set dummy ${ac_tool_prefix}ar; ac_word=$2
echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1015: checking for $ac_word" >&5
+echo "configure:1026: checking for $ac_word" >&5
if eval "test \"`echo '$''{'ac_cv_prog_AR'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
@@ -1043,7 +1054,7 @@ fi
# Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args.
set dummy ${ac_tool_prefix}ranlib; ac_word=$2
echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1047: checking for $ac_word" >&5
+echo "configure:1058: checking for $ac_word" >&5
if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
@@ -1075,7 +1086,7 @@ if test -n "$ac_tool_prefix"; then
# Extract the first word of "ranlib", so it can be a program name with args.
set dummy ranlib; ac_word=$2
echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1079: checking for $ac_word" >&5
+echo "configure:1090: checking for $ac_word" >&5
if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
@@ -1181,7 +1192,7 @@ fi
# Extract the first word of "gcc", so it can be a program name with args.
set dummy gcc; ac_word=$2
echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1185: checking for $ac_word" >&5
+echo "configure:1196: checking for $ac_word" >&5
if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
@@ -1211,7 +1222,7 @@ if test -z "$CC"; then
# Extract the first word of "cc", so it can be a program name with args.
set dummy cc; ac_word=$2
echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1215: checking for $ac_word" >&5
+echo "configure:1226: checking for $ac_word" >&5
if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
@@ -1262,7 +1273,7 @@ fi
# Extract the first word of "cl", so it can be a program name with args.
set dummy cl; ac_word=$2
echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1266: checking for $ac_word" >&5
+echo "configure:1277: checking for $ac_word" >&5
if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
@@ -1294,7 +1305,7 @@ fi
fi
echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works""... $ac_c" 1>&6
-echo "configure:1298: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5
+echo "configure:1309: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5
ac_ext=c
# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options.
@@ -1305,12 +1316,12 @@ cross_compiling=$ac_cv_prog_cc_cross
cat > conftest.$ac_ext << EOF
-#line 1309 "configure"
+#line 1320 "configure"
#include "confdefs.h"
main(){return(0);}
EOF
-if { (eval echo configure:1314: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:1325: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
ac_cv_prog_cc_works=yes
# If we can't run a trivial program, we are probably using a cross compiler.
if (./conftest; exit) 2>/dev/null; then
@@ -1336,12 +1347,12 @@ if test $ac_cv_prog_cc_works = no; then
{ echo "configure: error: installation or configuration problem: C compiler cannot create executables." 1>&2; exit 1; }
fi
echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler""... $ac_c" 1>&6
-echo "configure:1340: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5
+echo "configure:1351: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5
echo "$ac_t""$ac_cv_prog_cc_cross" 1>&6
cross_compiling=$ac_cv_prog_cc_cross
echo $ac_n "checking whether we are using GNU C""... $ac_c" 1>&6
-echo "configure:1345: checking whether we are using GNU C" >&5
+echo "configure:1356: checking whether we are using GNU C" >&5
if eval "test \"`echo '$''{'ac_cv_prog_gcc'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
@@ -1350,7 +1361,7 @@ else
yes;
#endif
EOF
-if { ac_try='${CC-cc} -E conftest.c'; { (eval echo configure:1354: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then
+if { ac_try='${CC-cc} -E conftest.c'; { (eval echo configure:1365: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then
ac_cv_prog_gcc=yes
else
ac_cv_prog_gcc=no
@@ -1369,7 +1380,7 @@ ac_test_CFLAGS="${CFLAGS+set}"
ac_save_CFLAGS="$CFLAGS"
CFLAGS=
echo $ac_n "checking whether ${CC-cc} accepts -g""... $ac_c" 1>&6
-echo "configure:1373: checking whether ${CC-cc} accepts -g" >&5
+echo "configure:1384: checking whether ${CC-cc} accepts -g" >&5
if eval "test \"`echo '$''{'ac_cv_prog_cc_g'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
@@ -1412,7 +1423,7 @@ ac_prog=ld
if test "$GCC" = yes; then
# Check if gcc -print-prog-name=ld gives a path.
echo $ac_n "checking for ld used by GCC""... $ac_c" 1>&6
-echo "configure:1416: checking for ld used by GCC" >&5
+echo "configure:1427: checking for ld used by GCC" >&5
case $host in
*-*-mingw*)
# gcc leaves a trailing carriage return which upsets mingw
@@ -1442,10 +1453,10 @@ echo "configure:1416: checking for ld used by GCC" >&5
esac
elif test "$with_gnu_ld" = yes; then
echo $ac_n "checking for GNU ld""... $ac_c" 1>&6
-echo "configure:1446: checking for GNU ld" >&5
+echo "configure:1457: checking for GNU ld" >&5
else
echo $ac_n "checking for non-GNU ld""... $ac_c" 1>&6
-echo "configure:1449: checking for non-GNU ld" >&5
+echo "configure:1460: checking for non-GNU ld" >&5
fi
if eval "test \"`echo '$''{'lt_cv_path_LD'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
@@ -1480,7 +1491,7 @@ else
fi
test -z "$LD" && { echo "configure: error: no acceptable ld found in \$PATH" 1>&2; exit 1; }
echo $ac_n "checking if the linker ($LD) is GNU ld""... $ac_c" 1>&6
-echo "configure:1484: checking if the linker ($LD) is GNU ld" >&5
+echo "configure:1495: checking if the linker ($LD) is GNU ld" >&5
if eval "test \"`echo '$''{'lt_cv_prog_gnu_ld'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
@@ -1497,7 +1508,7 @@ with_gnu_ld=$lt_cv_prog_gnu_ld
echo $ac_n "checking for $LD option to reload object files""... $ac_c" 1>&6
-echo "configure:1501: checking for $LD option to reload object files" >&5
+echo "configure:1512: checking for $LD option to reload object files" >&5
if eval "test \"`echo '$''{'lt_cv_ld_reload_flag'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
@@ -1509,7 +1520,7 @@ reload_flag=$lt_cv_ld_reload_flag
test -n "$reload_flag" && reload_flag=" $reload_flag"
echo $ac_n "checking for BSD-compatible nm""... $ac_c" 1>&6
-echo "configure:1513: checking for BSD-compatible nm" >&5
+echo "configure:1524: checking for BSD-compatible nm" >&5
if eval "test \"`echo '$''{'lt_cv_path_NM'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
@@ -1547,7 +1558,7 @@ NM="$lt_cv_path_NM"
echo "$ac_t""$NM" 1>&6
echo $ac_n "checking whether ln -s works""... $ac_c" 1>&6
-echo "configure:1551: checking whether ln -s works" >&5
+echo "configure:1562: checking whether ln -s works" >&5
if eval "test \"`echo '$''{'ac_cv_prog_LN_S'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
@@ -1568,7 +1579,7 @@ else
fi
echo $ac_n "checking how to recognise dependant libraries""... $ac_c" 1>&6
-echo "configure:1572: checking how to recognise dependant libraries" >&5
+echo "configure:1583: checking how to recognise dependant libraries" >&5
if eval "test \"`echo '$''{'lt_cv_deplibs_check_method'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
@@ -1732,13 +1743,13 @@ file_magic_cmd=$lt_cv_file_magic_cmd
deplibs_check_method=$lt_cv_deplibs_check_method
echo $ac_n "checking for object suffix""... $ac_c" 1>&6
-echo "configure:1736: checking for object suffix" >&5
+echo "configure:1747: checking for object suffix" >&5
if eval "test \"`echo '$''{'ac_cv_objext'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
rm -f conftest*
echo 'int i = 1;' > conftest.$ac_ext
-if { (eval echo configure:1742: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+if { (eval echo configure:1753: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
for ac_file in conftest.*; do
case $ac_file in
*.c) ;;
@@ -1758,7 +1769,7 @@ ac_objext=$ac_cv_objext
echo $ac_n "checking for executable suffix""... $ac_c" 1>&6
-echo "configure:1762: checking for executable suffix" >&5
+echo "configure:1773: checking for executable suffix" >&5
if eval "test \"`echo '$''{'ac_cv_exeext'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
@@ -1768,10 +1779,10 @@ else
rm -f conftest*
echo 'int main () { return 0; }' > conftest.$ac_ext
ac_cv_exeext=
- if { (eval echo configure:1772: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; }; then
+ if { (eval echo configure:1783: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; }; then
for file in conftest.*; do
case $file in
- *.c | *.o | *.obj) ;;
+ *.c | *.o | *.obj | *.ilk | *.pdb) ;;
*) ac_cv_exeext=`echo $file | sed -e s/conftest//` ;;
esac
done
@@ -1795,7 +1806,7 @@ case $deplibs_check_method in
file_magic*)
if test "$file_magic_cmd" = '$MAGIC_CMD'; then
echo $ac_n "checking for ${ac_tool_prefix}file""... $ac_c" 1>&6
-echo "configure:1799: checking for ${ac_tool_prefix}file" >&5
+echo "configure:1810: checking for ${ac_tool_prefix}file" >&5
if eval "test \"`echo '$''{'lt_cv_path_MAGIC_CMD'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
@@ -1857,7 +1868,7 @@ fi
if test -z "$lt_cv_path_MAGIC_CMD"; then
if test -n "$ac_tool_prefix"; then
echo $ac_n "checking for file""... $ac_c" 1>&6
-echo "configure:1861: checking for file" >&5
+echo "configure:1872: checking for file" >&5
if eval "test \"`echo '$''{'lt_cv_path_MAGIC_CMD'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
@@ -1928,7 +1939,7 @@ esac
# Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args.
set dummy ${ac_tool_prefix}ranlib; ac_word=$2
echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1932: checking for $ac_word" >&5
+echo "configure:1943: checking for $ac_word" >&5
if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
@@ -1960,7 +1971,7 @@ if test -n "$ac_tool_prefix"; then
# Extract the first word of "ranlib", so it can be a program name with args.
set dummy ranlib; ac_word=$2
echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1964: checking for $ac_word" >&5
+echo "configure:1975: checking for $ac_word" >&5
if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
@@ -1995,7 +2006,7 @@ fi
# Extract the first word of "${ac_tool_prefix}strip", so it can be a program name with args.
set dummy ${ac_tool_prefix}strip; ac_word=$2
echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1999: checking for $ac_word" >&5
+echo "configure:2010: checking for $ac_word" >&5
if eval "test \"`echo '$''{'ac_cv_prog_STRIP'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
@@ -2027,7 +2038,7 @@ if test -n "$ac_tool_prefix"; then
# Extract the first word of "strip", so it can be a program name with args.
set dummy strip; ac_word=$2
echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:2031: checking for $ac_word" >&5
+echo "configure:2042: checking for $ac_word" >&5
if eval "test \"`echo '$''{'ac_cv_prog_STRIP'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
@@ -2094,8 +2105,8 @@ test x"$pic_mode" = xno && libtool_flags="$libtool_flags --prefer-non-pic"
case $host in
*-*-irix6*)
# Find out which ABI we are using.
- echo '#line 2098 "configure"' > conftest.$ac_ext
- if { (eval echo configure:2099: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+ echo '#line 2109 "configure"' > conftest.$ac_ext
+ if { (eval echo configure:2110: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
case `/usr/bin/file conftest.$ac_objext` in
*32-bit*)
LD="${LD-ld} -32"
@@ -2116,7 +2127,7 @@ case $host in
SAVE_CFLAGS="$CFLAGS"
CFLAGS="$CFLAGS -belf"
echo $ac_n "checking whether the C compiler needs -belf""... $ac_c" 1>&6
-echo "configure:2120: checking whether the C compiler needs -belf" >&5
+echo "configure:2131: checking whether the C compiler needs -belf" >&5
if eval "test \"`echo '$''{'lt_cv_cc_needs_belf'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
@@ -2129,14 +2140,14 @@ ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$a
cross_compiling=$ac_cv_prog_cc_cross
cat > conftest.$ac_ext <<EOF
-#line 2133 "configure"
+#line 2144 "configure"
#include "confdefs.h"
int main() {
; return 0; }
EOF
-if { (eval echo configure:2140: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:2151: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
rm -rf conftest*
lt_cv_cc_needs_belf=yes
else
@@ -2304,7 +2315,7 @@ if test -z "$target" ; then
fi
echo $ac_n "checking whether to enable maintainer-specific portions of Makefiles""... $ac_c" 1>&6
-echo "configure:2308: checking whether to enable maintainer-specific portions of Makefiles" >&5
+echo "configure:2319: checking whether to enable maintainer-specific portions of Makefiles" >&5
# Check whether --enable-maintainer-mode or --disable-maintainer-mode was given.
if test "${enable_maintainer_mode+set}" = set; then
enableval="$enable_maintainer_mode"
@@ -2329,7 +2340,7 @@ fi
echo $ac_n "checking for executable suffix""... $ac_c" 1>&6
-echo "configure:2333: checking for executable suffix" >&5
+echo "configure:2344: checking for executable suffix" >&5
if eval "test \"`echo '$''{'ac_cv_exeext'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
@@ -2339,10 +2350,10 @@ else
rm -f conftest*
echo 'int main () { return 0; }' > conftest.$ac_ext
ac_cv_exeext=
- if { (eval echo configure:2343: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; }; then
+ if { (eval echo configure:2354: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; }; then
for file in conftest.*; do
case $file in
- *.c | *.o | *.obj) ;;
+ *.c | *.o | *.obj | *.ilk | *.pdb) ;;
*) ac_cv_exeext=`echo $file | sed -e s/conftest//` ;;
esac
done
@@ -2365,7 +2376,7 @@ ac_exeext=$EXEEXT
# Extract the first word of "gcc", so it can be a program name with args.
set dummy gcc; ac_word=$2
echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:2369: checking for $ac_word" >&5
+echo "configure:2380: checking for $ac_word" >&5
if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
@@ -2395,7 +2406,7 @@ if test -z "$CC"; then
# Extract the first word of "cc", so it can be a program name with args.
set dummy cc; ac_word=$2
echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:2399: checking for $ac_word" >&5
+echo "configure:2410: checking for $ac_word" >&5
if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
@@ -2446,7 +2457,7 @@ fi
# Extract the first word of "cl", so it can be a program name with args.
set dummy cl; ac_word=$2
echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:2450: checking for $ac_word" >&5
+echo "configure:2461: checking for $ac_word" >&5
if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
@@ -2478,7 +2489,7 @@ fi
fi
echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works""... $ac_c" 1>&6
-echo "configure:2482: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5
+echo "configure:2493: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5
ac_ext=c
# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options.
@@ -2489,12 +2500,12 @@ cross_compiling=$ac_cv_prog_cc_cross
cat > conftest.$ac_ext << EOF
-#line 2493 "configure"
+#line 2504 "configure"
#include "confdefs.h"
main(){return(0);}
EOF
-if { (eval echo configure:2498: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:2509: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
ac_cv_prog_cc_works=yes
# If we can't run a trivial program, we are probably using a cross compiler.
if (./conftest; exit) 2>/dev/null; then
@@ -2520,12 +2531,12 @@ if test $ac_cv_prog_cc_works = no; then
{ echo "configure: error: installation or configuration problem: C compiler cannot create executables." 1>&2; exit 1; }
fi
echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler""... $ac_c" 1>&6
-echo "configure:2524: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5
+echo "configure:2535: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5
echo "$ac_t""$ac_cv_prog_cc_cross" 1>&6
cross_compiling=$ac_cv_prog_cc_cross
echo $ac_n "checking whether we are using GNU C""... $ac_c" 1>&6
-echo "configure:2529: checking whether we are using GNU C" >&5
+echo "configure:2540: checking whether we are using GNU C" >&5
if eval "test \"`echo '$''{'ac_cv_prog_gcc'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
@@ -2534,7 +2545,7 @@ else
yes;
#endif
EOF
-if { ac_try='${CC-cc} -E conftest.c'; { (eval echo configure:2538: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then
+if { ac_try='${CC-cc} -E conftest.c'; { (eval echo configure:2549: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then
ac_cv_prog_gcc=yes
else
ac_cv_prog_gcc=no
@@ -2553,7 +2564,7 @@ ac_test_CFLAGS="${CFLAGS+set}"
ac_save_CFLAGS="$CFLAGS"
CFLAGS=
echo $ac_n "checking whether ${CC-cc} accepts -g""... $ac_c" 1>&6
-echo "configure:2557: checking whether ${CC-cc} accepts -g" >&5
+echo "configure:2568: checking whether ${CC-cc} accepts -g" >&5
if eval "test \"`echo '$''{'ac_cv_prog_cc_g'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
@@ -2587,7 +2598,7 @@ fi
ALL_LINGUAS="fr sv tr"
echo $ac_n "checking how to run the C preprocessor""... $ac_c" 1>&6
-echo "configure:2591: checking how to run the C preprocessor" >&5
+echo "configure:2602: checking how to run the C preprocessor" >&5
# On Suns, sometimes $CPP names a directory.
if test -n "$CPP" && test -d "$CPP"; then
CPP=
@@ -2602,13 +2613,13 @@ else
# On the NeXT, cc -E runs the code through the compiler's parser,
# not just through cpp.
cat > conftest.$ac_ext <<EOF
-#line 2606 "configure"
+#line 2617 "configure"
#include "confdefs.h"
#include <assert.h>
Syntax Error
EOF
ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:2612: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+{ (eval echo configure:2623: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
if test -z "$ac_err"; then
:
@@ -2619,13 +2630,13 @@ else
rm -rf conftest*
CPP="${CC-cc} -E -traditional-cpp"
cat > conftest.$ac_ext <<EOF
-#line 2623 "configure"
+#line 2634 "configure"
#include "confdefs.h"
#include <assert.h>
Syntax Error
EOF
ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:2629: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+{ (eval echo configure:2640: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
if test -z "$ac_err"; then
:
@@ -2636,13 +2647,13 @@ else
rm -rf conftest*
CPP="${CC-cc} -nologo -E"
cat > conftest.$ac_ext <<EOF
-#line 2640 "configure"
+#line 2651 "configure"
#include "confdefs.h"
#include <assert.h>
Syntax Error
EOF
ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:2646: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+{ (eval echo configure:2657: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
if test -z "$ac_err"; then
:
@@ -2669,7 +2680,7 @@ echo "$ac_t""$CPP" 1>&6
# Extract the first word of "ranlib", so it can be a program name with args.
set dummy ranlib; ac_word=$2
echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:2673: checking for $ac_word" >&5
+echo "configure:2684: checking for $ac_word" >&5
if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
@@ -2697,12 +2708,12 @@ else
fi
echo $ac_n "checking for ANSI C header files""... $ac_c" 1>&6
-echo "configure:2701: checking for ANSI C header files" >&5
+echo "configure:2712: checking for ANSI C header files" >&5
if eval "test \"`echo '$''{'ac_cv_header_stdc'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
-#line 2706 "configure"
+#line 2717 "configure"
#include "confdefs.h"
#include <stdlib.h>
#include <stdarg.h>
@@ -2710,7 +2721,7 @@ else
#include <float.h>
EOF
ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:2714: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+{ (eval echo configure:2725: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
if test -z "$ac_err"; then
rm -rf conftest*
@@ -2727,7 +2738,7 @@ rm -f conftest*
if test $ac_cv_header_stdc = yes; then
# SunOS 4.x string.h does not declare mem*, contrary to ANSI.
cat > conftest.$ac_ext <<EOF
-#line 2731 "configure"
+#line 2742 "configure"
#include "confdefs.h"
#include <string.h>
EOF
@@ -2745,7 +2756,7 @@ fi
if test $ac_cv_header_stdc = yes; then
# ISC 2.0.2 stdlib.h does not declare free, contrary to ANSI.
cat > conftest.$ac_ext <<EOF
-#line 2749 "configure"
+#line 2760 "configure"
#include "confdefs.h"
#include <stdlib.h>
EOF
@@ -2766,7 +2777,7 @@ if test "$cross_compiling" = yes; then
:
else
cat > conftest.$ac_ext <<EOF
-#line 2770 "configure"
+#line 2781 "configure"
#include "confdefs.h"
#include <ctype.h>
#define ISLOWER(c) ('a' <= (c) && (c) <= 'z')
@@ -2777,7 +2788,7 @@ if (XOR (islower (i), ISLOWER (i)) || toupper (i) != TOUPPER (i)) exit(2);
exit (0); }
EOF
-if { (eval echo configure:2781: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
+if { (eval echo configure:2792: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
then
:
else
@@ -2801,12 +2812,12 @@ EOF
fi
echo $ac_n "checking for working const""... $ac_c" 1>&6
-echo "configure:2805: checking for working const" >&5
+echo "configure:2816: checking for working const" >&5
if eval "test \"`echo '$''{'ac_cv_c_const'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
-#line 2810 "configure"
+#line 2821 "configure"
#include "confdefs.h"
int main() {
@@ -2855,7 +2866,7 @@ ccp = (char const *const *) p;
; return 0; }
EOF
-if { (eval echo configure:2859: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+if { (eval echo configure:2870: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
rm -rf conftest*
ac_cv_c_const=yes
else
@@ -2876,21 +2887,21 @@ EOF
fi
echo $ac_n "checking for inline""... $ac_c" 1>&6
-echo "configure:2880: checking for inline" >&5
+echo "configure:2891: checking for inline" >&5
if eval "test \"`echo '$''{'ac_cv_c_inline'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
ac_cv_c_inline=no
for ac_kw in inline __inline__ __inline; do
cat > conftest.$ac_ext <<EOF
-#line 2887 "configure"
+#line 2898 "configure"
#include "confdefs.h"
int main() {
} $ac_kw foo() {
; return 0; }
EOF
-if { (eval echo configure:2894: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+if { (eval echo configure:2905: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
rm -rf conftest*
ac_cv_c_inline=$ac_kw; break
else
@@ -2916,12 +2927,12 @@ EOF
esac
echo $ac_n "checking for off_t""... $ac_c" 1>&6
-echo "configure:2920: checking for off_t" >&5
+echo "configure:2931: checking for off_t" >&5
if eval "test \"`echo '$''{'ac_cv_type_off_t'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
-#line 2925 "configure"
+#line 2936 "configure"
#include "confdefs.h"
#include <sys/types.h>
#if STDC_HEADERS
@@ -2949,12 +2960,12 @@ EOF
fi
echo $ac_n "checking for size_t""... $ac_c" 1>&6
-echo "configure:2953: checking for size_t" >&5
+echo "configure:2964: checking for size_t" >&5
if eval "test \"`echo '$''{'ac_cv_type_size_t'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
-#line 2958 "configure"
+#line 2969 "configure"
#include "confdefs.h"
#include <sys/types.h>
#if STDC_HEADERS
@@ -2984,19 +2995,19 @@ fi
# The Ultrix 4.2 mips builtin alloca declared by alloca.h only works
# for constant arguments. Useless!
echo $ac_n "checking for working alloca.h""... $ac_c" 1>&6
-echo "configure:2988: checking for working alloca.h" >&5
+echo "configure:2999: checking for working alloca.h" >&5
if eval "test \"`echo '$''{'ac_cv_header_alloca_h'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
-#line 2993 "configure"
+#line 3004 "configure"
#include "confdefs.h"
#include <alloca.h>
int main() {
char *p = alloca(2 * sizeof(int));
; return 0; }
EOF
-if { (eval echo configure:3000: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:3011: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
rm -rf conftest*
ac_cv_header_alloca_h=yes
else
@@ -3017,12 +3028,12 @@ EOF
fi
echo $ac_n "checking for alloca""... $ac_c" 1>&6
-echo "configure:3021: checking for alloca" >&5
+echo "configure:3032: checking for alloca" >&5
if eval "test \"`echo '$''{'ac_cv_func_alloca_works'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
-#line 3026 "configure"
+#line 3037 "configure"
#include "confdefs.h"
#ifdef __GNUC__
@@ -3050,7 +3061,7 @@ int main() {
char *p = (char *) alloca(1);
; return 0; }
EOF
-if { (eval echo configure:3054: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:3065: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
rm -rf conftest*
ac_cv_func_alloca_works=yes
else
@@ -3082,12 +3093,12 @@ EOF
echo $ac_n "checking whether alloca needs Cray hooks""... $ac_c" 1>&6
-echo "configure:3086: checking whether alloca needs Cray hooks" >&5
+echo "configure:3097: checking whether alloca needs Cray hooks" >&5
if eval "test \"`echo '$''{'ac_cv_os_cray'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
-#line 3091 "configure"
+#line 3102 "configure"
#include "confdefs.h"
#if defined(CRAY) && ! defined(CRAY2)
webecray
@@ -3112,12 +3123,12 @@ echo "$ac_t""$ac_cv_os_cray" 1>&6
if test $ac_cv_os_cray = yes; then
for ac_func in _getb67 GETB67 getb67; do
echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
-echo "configure:3116: checking for $ac_func" >&5
+echo "configure:3127: checking for $ac_func" >&5
if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
-#line 3121 "configure"
+#line 3132 "configure"
#include "confdefs.h"
/* System header to define __stub macros and hopefully few prototypes,
which can conflict with char $ac_func(); below. */
@@ -3140,7 +3151,7 @@ $ac_func();
; return 0; }
EOF
-if { (eval echo configure:3144: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:3155: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
rm -rf conftest*
eval "ac_cv_func_$ac_func=yes"
else
@@ -3167,7 +3178,7 @@ done
fi
echo $ac_n "checking stack direction for C alloca""... $ac_c" 1>&6
-echo "configure:3171: checking stack direction for C alloca" >&5
+echo "configure:3182: checking stack direction for C alloca" >&5
if eval "test \"`echo '$''{'ac_cv_c_stack_direction'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
@@ -3175,7 +3186,7 @@ else
ac_cv_c_stack_direction=0
else
cat > conftest.$ac_ext <<EOF
-#line 3179 "configure"
+#line 3190 "configure"
#include "confdefs.h"
find_stack_direction ()
{
@@ -3194,7 +3205,7 @@ main ()
exit (find_stack_direction() < 0);
}
EOF
-if { (eval echo configure:3198: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
+if { (eval echo configure:3209: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
then
ac_cv_c_stack_direction=1
else
@@ -3215,21 +3226,21 @@ EOF
fi
-for ac_hdr in stdlib.h unistd.h sys/stat.h sys/types.h
+for ac_hdr in unistd.h
do
ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
-echo "configure:3223: checking for $ac_hdr" >&5
+echo "configure:3234: checking for $ac_hdr" >&5
if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
-#line 3228 "configure"
+#line 3239 "configure"
#include "confdefs.h"
#include <$ac_hdr>
EOF
ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:3233: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+{ (eval echo configure:3244: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
if test -z "$ac_err"; then
rm -rf conftest*
@@ -3258,12 +3269,12 @@ done
for ac_func in getpagesize
do
echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
-echo "configure:3262: checking for $ac_func" >&5
+echo "configure:3273: checking for $ac_func" >&5
if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
-#line 3267 "configure"
+#line 3278 "configure"
#include "confdefs.h"
/* System header to define __stub macros and hopefully few prototypes,
which can conflict with char $ac_func(); below. */
@@ -3286,7 +3297,7 @@ $ac_func();
; return 0; }
EOF
-if { (eval echo configure:3290: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:3301: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
rm -rf conftest*
eval "ac_cv_func_$ac_func=yes"
else
@@ -3311,7 +3322,7 @@ fi
done
echo $ac_n "checking for working mmap""... $ac_c" 1>&6
-echo "configure:3315: checking for working mmap" >&5
+echo "configure:3326: checking for working mmap" >&5
if eval "test \"`echo '$''{'ac_cv_func_mmap_fixed_mapped'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
@@ -3319,7 +3330,7 @@ else
ac_cv_func_mmap_fixed_mapped=no
else
cat > conftest.$ac_ext <<EOF
-#line 3323 "configure"
+#line 3334 "configure"
#include "confdefs.h"
/* Thanks to Mike Haertel and Jim Avera for this test.
@@ -3347,24 +3358,11 @@ else
#include <fcntl.h>
#include <sys/mman.h>
-#if HAVE_SYS_TYPES_H
-# include <sys/types.h>
-#endif
-
-#if HAVE_STDLIB_H
-# include <stdlib.h>
-#endif
-
-#if HAVE_SYS_STAT_H
-# include <sys/stat.h>
-#endif
-
-#if HAVE_UNISTD_H
-# include <unistd.h>
-#endif
-
/* This mess was copied from the GNU getpagesize.h. */
#ifndef HAVE_GETPAGESIZE
+# ifdef HAVE_UNISTD_H
+# include <unistd.h>
+# endif
/* Assume that all systems that can run configure have sys/param.h. */
# ifndef HAVE_SYS_PARAM_H
@@ -3472,7 +3470,7 @@ main()
}
EOF
-if { (eval echo configure:3476: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
+if { (eval echo configure:3474: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
then
ac_cv_func_mmap_fixed_mapped=yes
else
@@ -3500,17 +3498,17 @@ unistd.h values.h sys/param.h
do
ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
-echo "configure:3504: checking for $ac_hdr" >&5
+echo "configure:3502: checking for $ac_hdr" >&5
if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
-#line 3509 "configure"
+#line 3507 "configure"
#include "confdefs.h"
#include <$ac_hdr>
EOF
ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:3514: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+{ (eval echo configure:3512: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
if test -z "$ac_err"; then
rm -rf conftest*
@@ -3540,12 +3538,12 @@ done
__argz_count __argz_stringify __argz_next
do
echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
-echo "configure:3544: checking for $ac_func" >&5
+echo "configure:3542: checking for $ac_func" >&5
if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
-#line 3549 "configure"
+#line 3547 "configure"
#include "confdefs.h"
/* System header to define __stub macros and hopefully few prototypes,
which can conflict with char $ac_func(); below. */
@@ -3568,7 +3566,7 @@ $ac_func();
; return 0; }
EOF
-if { (eval echo configure:3572: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:3570: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
rm -rf conftest*
eval "ac_cv_func_$ac_func=yes"
else
@@ -3597,12 +3595,12 @@ done
for ac_func in stpcpy
do
echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
-echo "configure:3601: checking for $ac_func" >&5
+echo "configure:3599: checking for $ac_func" >&5
if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
-#line 3606 "configure"
+#line 3604 "configure"
#include "confdefs.h"
/* System header to define __stub macros and hopefully few prototypes,
which can conflict with char $ac_func(); below. */
@@ -3625,7 +3623,7 @@ $ac_func();
; return 0; }
EOF
-if { (eval echo configure:3629: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:3627: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
rm -rf conftest*
eval "ac_cv_func_$ac_func=yes"
else
@@ -3659,19 +3657,19 @@ EOF
if test $ac_cv_header_locale_h = yes; then
echo $ac_n "checking for LC_MESSAGES""... $ac_c" 1>&6
-echo "configure:3663: checking for LC_MESSAGES" >&5
+echo "configure:3661: checking for LC_MESSAGES" >&5
if eval "test \"`echo '$''{'am_cv_val_LC_MESSAGES'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
-#line 3668 "configure"
+#line 3666 "configure"
#include "confdefs.h"
#include <locale.h>
int main() {
return LC_MESSAGES
; return 0; }
EOF
-if { (eval echo configure:3675: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:3673: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
rm -rf conftest*
am_cv_val_LC_MESSAGES=yes
else
@@ -3692,7 +3690,7 @@ EOF
fi
fi
echo $ac_n "checking whether NLS is requested""... $ac_c" 1>&6
-echo "configure:3696: checking whether NLS is requested" >&5
+echo "configure:3694: checking whether NLS is requested" >&5
# Check whether --enable-nls or --disable-nls was given.
if test "${enable_nls+set}" = set; then
enableval="$enable_nls"
@@ -3712,7 +3710,7 @@ fi
EOF
echo $ac_n "checking whether included gettext is requested""... $ac_c" 1>&6
-echo "configure:3716: checking whether included gettext is requested" >&5
+echo "configure:3714: checking whether included gettext is requested" >&5
# Check whether --with-included-gettext or --without-included-gettext was given.
if test "${with_included_gettext+set}" = set; then
withval="$with_included_gettext"
@@ -3731,17 +3729,17 @@ fi
ac_safe=`echo "libintl.h" | sed 'y%./+-%__p_%'`
echo $ac_n "checking for libintl.h""... $ac_c" 1>&6
-echo "configure:3735: checking for libintl.h" >&5
+echo "configure:3733: checking for libintl.h" >&5
if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
-#line 3740 "configure"
+#line 3738 "configure"
#include "confdefs.h"
#include <libintl.h>
EOF
ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:3745: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+{ (eval echo configure:3743: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
if test -z "$ac_err"; then
rm -rf conftest*
@@ -3758,19 +3756,19 @@ fi
if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then
echo "$ac_t""yes" 1>&6
echo $ac_n "checking for gettext in libc""... $ac_c" 1>&6
-echo "configure:3762: checking for gettext in libc" >&5
+echo "configure:3760: checking for gettext in libc" >&5
if eval "test \"`echo '$''{'gt_cv_func_gettext_libc'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
-#line 3767 "configure"
+#line 3765 "configure"
#include "confdefs.h"
#include <libintl.h>
int main() {
return (int) gettext ("")
; return 0; }
EOF
-if { (eval echo configure:3774: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:3772: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
rm -rf conftest*
gt_cv_func_gettext_libc=yes
else
@@ -3786,7 +3784,7 @@ echo "$ac_t""$gt_cv_func_gettext_libc" 1>&6
if test "$gt_cv_func_gettext_libc" != "yes"; then
echo $ac_n "checking for bindtextdomain in -lintl""... $ac_c" 1>&6
-echo "configure:3790: checking for bindtextdomain in -lintl" >&5
+echo "configure:3788: checking for bindtextdomain in -lintl" >&5
ac_lib_var=`echo intl'_'bindtextdomain | sed 'y%./+-%__p_%'`
if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
@@ -3794,7 +3792,7 @@ else
ac_save_LIBS="$LIBS"
LIBS="-lintl $LIBS"
cat > conftest.$ac_ext <<EOF
-#line 3798 "configure"
+#line 3796 "configure"
#include "confdefs.h"
/* Override any gcc2 internal prototype to avoid an error. */
/* We use char because int might match the return type of a gcc2
@@ -3805,7 +3803,7 @@ int main() {
bindtextdomain()
; return 0; }
EOF
-if { (eval echo configure:3809: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:3807: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
rm -rf conftest*
eval "ac_cv_lib_$ac_lib_var=yes"
else
@@ -3821,19 +3819,19 @@ fi
if eval "test \"`echo '$ac_cv_lib_'$ac_lib_var`\" = yes"; then
echo "$ac_t""yes" 1>&6
echo $ac_n "checking for gettext in libintl""... $ac_c" 1>&6
-echo "configure:3825: checking for gettext in libintl" >&5
+echo "configure:3823: checking for gettext in libintl" >&5
if eval "test \"`echo '$''{'gt_cv_func_gettext_libintl'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
-#line 3830 "configure"
+#line 3828 "configure"
#include "confdefs.h"
int main() {
return (int) gettext ("")
; return 0; }
EOF
-if { (eval echo configure:3837: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:3835: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
rm -rf conftest*
gt_cv_func_gettext_libintl=yes
else
@@ -3861,7 +3859,7 @@ EOF
# Extract the first word of "msgfmt", so it can be a program name with args.
set dummy msgfmt; ac_word=$2
echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:3865: checking for $ac_word" >&5
+echo "configure:3863: checking for $ac_word" >&5
if eval "test \"`echo '$''{'ac_cv_path_MSGFMT'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
@@ -3895,12 +3893,12 @@ fi
for ac_func in dcgettext
do
echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
-echo "configure:3899: checking for $ac_func" >&5
+echo "configure:3897: checking for $ac_func" >&5
if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
-#line 3904 "configure"
+#line 3902 "configure"
#include "confdefs.h"
/* System header to define __stub macros and hopefully few prototypes,
which can conflict with char $ac_func(); below. */
@@ -3923,7 +3921,7 @@ $ac_func();
; return 0; }
EOF
-if { (eval echo configure:3927: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:3925: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
rm -rf conftest*
eval "ac_cv_func_$ac_func=yes"
else
@@ -3950,7 +3948,7 @@ done
# Extract the first word of "gmsgfmt", so it can be a program name with args.
set dummy gmsgfmt; ac_word=$2
echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:3954: checking for $ac_word" >&5
+echo "configure:3952: checking for $ac_word" >&5
if eval "test \"`echo '$''{'ac_cv_path_GMSGFMT'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
@@ -3986,7 +3984,7 @@ fi
# Extract the first word of "xgettext", so it can be a program name with args.
set dummy xgettext; ac_word=$2
echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:3990: checking for $ac_word" >&5
+echo "configure:3988: checking for $ac_word" >&5
if eval "test \"`echo '$''{'ac_cv_path_XGETTEXT'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
@@ -4018,7 +4016,7 @@ else
fi
cat > conftest.$ac_ext <<EOF
-#line 4022 "configure"
+#line 4020 "configure"
#include "confdefs.h"
int main() {
@@ -4026,7 +4024,7 @@ extern int _nl_msg_cat_cntr;
return _nl_msg_cat_cntr
; return 0; }
EOF
-if { (eval echo configure:4030: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:4028: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
rm -rf conftest*
CATOBJEXT=.gmo
DATADIRNAME=share
@@ -4058,7 +4056,7 @@ fi
# Extract the first word of "msgfmt", so it can be a program name with args.
set dummy msgfmt; ac_word=$2
echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:4062: checking for $ac_word" >&5
+echo "configure:4060: checking for $ac_word" >&5
if eval "test \"`echo '$''{'ac_cv_path_MSGFMT'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
@@ -4092,7 +4090,7 @@ fi
# Extract the first word of "gmsgfmt", so it can be a program name with args.
set dummy gmsgfmt; ac_word=$2
echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:4096: checking for $ac_word" >&5
+echo "configure:4094: checking for $ac_word" >&5
if eval "test \"`echo '$''{'ac_cv_path_GMSGFMT'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
@@ -4128,7 +4126,7 @@ fi
# Extract the first word of "xgettext", so it can be a program name with args.
set dummy xgettext; ac_word=$2
echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:4132: checking for $ac_word" >&5
+echo "configure:4130: checking for $ac_word" >&5
if eval "test \"`echo '$''{'ac_cv_path_XGETTEXT'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
@@ -4218,7 +4216,7 @@ fi
LINGUAS=
else
echo $ac_n "checking for catalogs to be installed""... $ac_c" 1>&6
-echo "configure:4222: checking for catalogs to be installed" >&5
+echo "configure:4220: checking for catalogs to be installed" >&5
NEW_LINGUAS=
for lang in ${LINGUAS=$ALL_LINGUAS}; do
case "$ALL_LINGUAS" in
@@ -4246,17 +4244,17 @@ echo "configure:4222: checking for catalogs to be installed" >&5
if test "$CATOBJEXT" = ".cat"; then
ac_safe=`echo "linux/version.h" | sed 'y%./+-%__p_%'`
echo $ac_n "checking for linux/version.h""... $ac_c" 1>&6
-echo "configure:4250: checking for linux/version.h" >&5
+echo "configure:4248: checking for linux/version.h" >&5
if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
-#line 4255 "configure"
+#line 4253 "configure"
#include "confdefs.h"
#include <linux/version.h>
EOF
ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:4260: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+{ (eval echo configure:4258: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
if test -z "$ac_err"; then
rm -rf conftest*
@@ -4334,7 +4332,7 @@ if test "x$cross_compiling" = "xno"; then
EXEEXT_FOR_BUILD='$(EXEEXT)'
else
echo $ac_n "checking for build system executable suffix""... $ac_c" 1>&6
-echo "configure:4338: checking for build system executable suffix" >&5
+echo "configure:4336: checking for build system executable suffix" >&5
if eval "test \"`echo '$''{'bfd_cv_build_exeext'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
@@ -4371,7 +4369,7 @@ fi
# SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff"
# ./install, which can be erroneously created by make from ./install.sh.
echo $ac_n "checking for a BSD compatible install""... $ac_c" 1>&6
-echo "configure:4375: checking for a BSD compatible install" >&5
+echo "configure:4373: checking for a BSD compatible install" >&5
if test -z "$INSTALL"; then
if eval "test \"`echo '$''{'ac_cv_path_install'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
@@ -4428,17 +4426,17 @@ for ac_hdr in string.h strings.h stdlib.h
do
ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
-echo "configure:4432: checking for $ac_hdr" >&5
+echo "configure:4430: checking for $ac_hdr" >&5
if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
-#line 4437 "configure"
+#line 4435 "configure"
#include "confdefs.h"
#include <$ac_hdr>
EOF
ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:4442: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+{ (eval echo configure:4440: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
if test -z "$ac_err"; then
rm -rf conftest*
@@ -4606,6 +4604,7 @@ if test x${all_targets} = xfalse ; then
bfd_vax_arch) ta="$ta vax-dis.lo" ;;
bfd_w65_arch) ta="$ta w65-dis.lo" ;;
bfd_we32k_arch) ;;
+ bfd_xstormy16_arch) ta="$ta xstormy16-asm.lo xstormy16-desc.lo xstormy16-dis.lo xstormy16-ibld.lo xstormy16-opc.lo" using_cgen=yes ;;
bfd_z8k_arch) ta="$ta z8k-dis.lo" ;;
"") ;;
diff --git a/opcodes/configure.in b/opcodes/configure.in
index 77e048c..bef461d 100644
--- a/opcodes/configure.in
+++ b/opcodes/configure.in
@@ -220,6 +220,7 @@ if test x${all_targets} = xfalse ; then
bfd_vax_arch) ta="$ta vax-dis.lo" ;;
bfd_w65_arch) ta="$ta w65-dis.lo" ;;
bfd_we32k_arch) ;;
+ bfd_xstormy16_arch) ta="$ta xstormy16-asm.lo xstormy16-desc.lo xstormy16-dis.lo xstormy16-ibld.lo xstormy16-opc.lo" using_cgen=yes ;;
bfd_z8k_arch) ta="$ta z8k-dis.lo" ;;
"") ;;
diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c
index 3a978d4..ab23635 100644
--- a/opcodes/disassemble.c
+++ b/opcodes/disassemble.c
@@ -62,6 +62,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#define ARCH_v850
#define ARCH_vax
#define ARCH_w65
+#define ARCH_xstormy16
#define ARCH_z8k
#endif
@@ -303,6 +304,11 @@ disassembler (abfd)
disassemble = print_insn_w65;
break;
#endif
+#ifdef ARCH_xstormy16
+ case bfd_arch_xstormy16:
+ disassemble = print_insn_xstormy16;
+ break;
+#endif
#ifdef ARCH_z8k
case bfd_arch_z8k:
if (bfd_get_mach(abfd) == bfd_mach_z8001)
diff --git a/opcodes/xstormy16-asm.c b/opcodes/xstormy16-asm.c
new file mode 100644
index 0000000..5cb3921
--- /dev/null
+++ b/opcodes/xstormy16-asm.c
@@ -0,0 +1,659 @@
+/* Assembler interface for targets using CGEN. -*- C -*-
+ CGEN: Cpu tools GENerator
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+- the resultant file is machine generated, cgen-asm.in isn't
+
+Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+/* ??? Eventually more and more of this stuff can go to cpu-independent files.
+ Keep that in mind. */
+
+#include "sysdep.h"
+#include <stdio.h>
+#include "ansidecl.h"
+#include "bfd.h"
+#include "symcat.h"
+#include "xstormy16-desc.h"
+#include "xstormy16-opc.h"
+#include "opintl.h"
+#include "xregex.h"
+#include "libiberty.h"
+#include "safe-ctype.h"
+
+#undef min
+#define min(a,b) ((a) < (b) ? (a) : (b))
+#undef max
+#define max(a,b) ((a) > (b) ? (a) : (b))
+
+static const char * parse_insn_normal
+ PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *));
+
+/* -- assembler routines inserted here. */
+
+/* -- asm.c */
+static const char * parse_mem8
+ PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
+static const char * parse_small_immediate
+ PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
+
+/* The machine-independent code doesn't know how to disambiguate
+ mov (foo),r3
+ and
+ mov (r2),r3
+ where 'foo' is a label. This helps it out. */
+
+static const char *
+parse_mem8 (cd, strp, opindex, valuep)
+ CGEN_CPU_DESC cd;
+ const char **strp;
+ int opindex;
+ unsigned long *valuep;
+{
+ if (**strp == '(')
+ {
+ const char *s = *strp;
+
+ if (s[1] == '-' && s[2] == '-')
+ return _("Bad register in preincrement");
+
+ while (isalnum (*++s))
+ ;
+ if (s[0] == '+' && s[1] == '+' && (s[2] == ')' || s[2] == ','))
+ return _("Bad register in postincrement");
+ if (s[0] == ',' || s[0] == ')')
+ return _("Bad register name");
+ }
+ else if (cgen_parse_keyword (cd, strp, & xstormy16_cgen_opval_gr_names,
+ valuep) == NULL)
+ return _("Label conflicts with register name");
+ else if (strncasecmp (*strp, "rx,", 3) == 0
+ || strncasecmp (*strp, "rxl,", 3) == 0
+ || strncasecmp (*strp, "rxh,", 3) == 0)
+ return _("Label conflicts with `Rx'");
+ else if (**strp == '#')
+ return _("Bad immediate expression");
+
+ return cgen_parse_unsigned_integer (cd, strp, opindex, valuep);
+}
+
+/* For the add and subtract instructions, there are two immediate forms,
+ one for small operands and one for large ones. We want to use
+ the small one when possible, but we do not want to generate relocs
+ of the small size. This is somewhat tricky. */
+
+static const char *
+parse_small_immediate (cd, strp, opindex, valuep)
+ CGEN_CPU_DESC cd;
+ const char **strp;
+ int opindex;
+ unsigned long *valuep;
+{
+ bfd_vma value;
+ enum cgen_parse_operand_result result;
+ const char *errmsg;
+
+ errmsg = (* cd->parse_operand_fn)
+ (cd, CGEN_PARSE_OPERAND_INTEGER, strp, opindex, BFD_RELOC_NONE,
+ &result, &value);
+
+ if (errmsg)
+ return errmsg;
+
+ if (result != CGEN_PARSE_OPERAND_RESULT_NUMBER)
+ return _("Small operand was not an immediate number");
+
+ *valuep = value;
+ return NULL;
+}
+/* -- */
+
+const char * xstormy16_cgen_parse_operand
+ PARAMS ((CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *));
+
+/* Main entry point for operand parsing.
+
+ This function is basically just a big switch statement. Earlier versions
+ used tables to look up the function to use, but
+ - if the table contains both assembler and disassembler functions then
+ the disassembler contains much of the assembler and vice-versa,
+ - there's a lot of inlining possibilities as things grow,
+ - using a switch statement avoids the function call overhead.
+
+ This function could be moved into `parse_insn_normal', but keeping it
+ separate makes clear the interface between `parse_insn_normal' and each of
+ the handlers. */
+
+const char *
+xstormy16_cgen_parse_operand (cd, opindex, strp, fields)
+ CGEN_CPU_DESC cd;
+ int opindex;
+ const char ** strp;
+ CGEN_FIELDS * fields;
+{
+ const char * errmsg = NULL;
+ /* Used by scalar operands that still need to be parsed. */
+ long junk ATTRIBUTE_UNUSED;
+
+ switch (opindex)
+ {
+ case XSTORMY16_OPERAND_RB :
+ errmsg = cgen_parse_keyword (cd, strp, & xstormy16_cgen_opval_gr_names, & fields->f_Rb);
+ break;
+ case XSTORMY16_OPERAND_RBJ :
+ errmsg = cgen_parse_keyword (cd, strp, & xstormy16_cgen_opval_gr_Rbj_names, & fields->f_Rbj);
+ break;
+ case XSTORMY16_OPERAND_RD :
+ errmsg = cgen_parse_keyword (cd, strp, & xstormy16_cgen_opval_gr_names, & fields->f_Rd);
+ break;
+ case XSTORMY16_OPERAND_RDM :
+ errmsg = cgen_parse_keyword (cd, strp, & xstormy16_cgen_opval_gr_names, & fields->f_Rdm);
+ break;
+ case XSTORMY16_OPERAND_RM :
+ errmsg = cgen_parse_keyword (cd, strp, & xstormy16_cgen_opval_gr_names, & fields->f_Rm);
+ break;
+ case XSTORMY16_OPERAND_RS :
+ errmsg = cgen_parse_keyword (cd, strp, & xstormy16_cgen_opval_gr_names, & fields->f_Rs);
+ break;
+ case XSTORMY16_OPERAND_ABS24 :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, XSTORMY16_OPERAND_ABS24, &fields->f_abs24);
+ break;
+ case XSTORMY16_OPERAND_BCOND2 :
+ errmsg = cgen_parse_keyword (cd, strp, & xstormy16_cgen_opval_h_branchcond, & fields->f_op2);
+ break;
+ case XSTORMY16_OPERAND_BCOND5 :
+ errmsg = cgen_parse_keyword (cd, strp, & xstormy16_cgen_opval_h_branchcond, & fields->f_op5);
+ break;
+ case XSTORMY16_OPERAND_HMEM8 :
+ errmsg = parse_mem8 (cd, strp, XSTORMY16_OPERAND_HMEM8, &fields->f_hmem8);
+ break;
+ case XSTORMY16_OPERAND_IMM12 :
+ errmsg = cgen_parse_signed_integer (cd, strp, XSTORMY16_OPERAND_IMM12, &fields->f_imm12);
+ break;
+ case XSTORMY16_OPERAND_IMM16 :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, XSTORMY16_OPERAND_IMM16, &fields->f_imm16);
+ break;
+ case XSTORMY16_OPERAND_IMM2 :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, XSTORMY16_OPERAND_IMM2, &fields->f_imm2);
+ break;
+ case XSTORMY16_OPERAND_IMM3 :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, XSTORMY16_OPERAND_IMM3, &fields->f_imm3);
+ break;
+ case XSTORMY16_OPERAND_IMM3B :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, XSTORMY16_OPERAND_IMM3B, &fields->f_imm3b);
+ break;
+ case XSTORMY16_OPERAND_IMM4 :
+ errmsg = parse_small_immediate (cd, strp, XSTORMY16_OPERAND_IMM4, &fields->f_imm4);
+ break;
+ case XSTORMY16_OPERAND_IMM8 :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, XSTORMY16_OPERAND_IMM8, &fields->f_imm8);
+ break;
+ case XSTORMY16_OPERAND_IMM8SMALL :
+ errmsg = parse_small_immediate (cd, strp, XSTORMY16_OPERAND_IMM8SMALL, &fields->f_imm8);
+ break;
+ case XSTORMY16_OPERAND_LMEM8 :
+ errmsg = parse_mem8 (cd, strp, XSTORMY16_OPERAND_LMEM8, &fields->f_lmem8);
+ break;
+ case XSTORMY16_OPERAND_REL12 :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, XSTORMY16_OPERAND_REL12, &fields->f_rel12);
+ break;
+ case XSTORMY16_OPERAND_REL12A :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, XSTORMY16_OPERAND_REL12A, &fields->f_rel12a);
+ break;
+ case XSTORMY16_OPERAND_REL8_2 :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, XSTORMY16_OPERAND_REL8_2, &fields->f_rel8_2);
+ break;
+ case XSTORMY16_OPERAND_REL8_4 :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, XSTORMY16_OPERAND_REL8_4, &fields->f_rel8_4);
+ break;
+ case XSTORMY16_OPERAND_WS2 :
+ errmsg = cgen_parse_keyword (cd, strp, & xstormy16_cgen_opval_h_wordsize, & fields->f_op2m);
+ break;
+
+ default :
+ /* xgettext:c-format */
+ fprintf (stderr, _("Unrecognized field %d while parsing.\n"), opindex);
+ abort ();
+ }
+
+ return errmsg;
+}
+
+cgen_parse_fn * const xstormy16_cgen_parse_handlers[] =
+{
+ parse_insn_normal,
+};
+
+void
+xstormy16_cgen_init_asm (cd)
+ CGEN_CPU_DESC cd;
+{
+ xstormy16_cgen_init_opcode_table (cd);
+ xstormy16_cgen_init_ibld_table (cd);
+ cd->parse_handlers = & xstormy16_cgen_parse_handlers[0];
+ cd->parse_operand = xstormy16_cgen_parse_operand;
+}
+
+
+
+/* Regex construction routine.
+
+ This translates an opcode syntax string into a regex string,
+ by replacing any non-character syntax element (such as an
+ opcode) with the pattern '.*'
+
+ It then compiles the regex and stores it in the opcode, for
+ later use by xstormy16_cgen_assemble_insn
+
+ Returns NULL for success, an error message for failure. */
+
+char *
+xstormy16_cgen_build_insn_regex (insn)
+ CGEN_INSN *insn;
+{
+ CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
+ const char *mnem = CGEN_INSN_MNEMONIC (insn);
+ char rxbuf[CGEN_MAX_RX_ELEMENTS];
+ char *rx = rxbuf;
+ const CGEN_SYNTAX_CHAR_TYPE *syn;
+ int reg_err;
+
+ syn = CGEN_SYNTAX_STRING (CGEN_OPCODE_SYNTAX (opc));
+
+ /* Mnemonics come first in the syntax string. */
+ if (! CGEN_SYNTAX_MNEMONIC_P (* syn))
+ return _("missing mnemonic in syntax string");
+ ++syn;
+
+ /* Generate a case sensitive regular expression that emulates case
+ insensitive matching in the "C" locale. We cannot generate a case
+ insensitive regular expression because in Turkish locales, 'i' and 'I'
+ are not equal modulo case conversion. */
+
+ /* Copy the literal mnemonic out of the insn. */
+ for (; *mnem; mnem++)
+ {
+ char c = *mnem;
+
+ if (ISALPHA (c))
+ {
+ *rx++ = '[';
+ *rx++ = TOLOWER (c);
+ *rx++ = TOUPPER (c);
+ *rx++ = ']';
+ }
+ else
+ *rx++ = c;
+ }
+
+ /* Copy any remaining literals from the syntax string into the rx. */
+ for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn)
+ {
+ if (CGEN_SYNTAX_CHAR_P (* syn))
+ {
+ char c = CGEN_SYNTAX_CHAR (* syn);
+
+ switch (c)
+ {
+ /* Escape any regex metacharacters in the syntax. */
+ case '.': case '[': case '\\':
+ case '*': case '^': case '$':
+
+#ifdef CGEN_ESCAPE_EXTENDED_REGEX
+ case '?': case '{': case '}':
+ case '(': case ')': case '*':
+ case '|': case '+': case ']':
+#endif
+ *rx++ = '\\';
+ *rx++ = c;
+ break;
+
+ default:
+ if (ISALPHA (c))
+ {
+ *rx++ = '[';
+ *rx++ = TOLOWER (c);
+ *rx++ = TOUPPER (c);
+ *rx++ = ']';
+ }
+ else
+ *rx++ = c;
+ break;
+ }
+ }
+ else
+ {
+ /* Replace non-syntax fields with globs. */
+ *rx++ = '.';
+ *rx++ = '*';
+ }
+ }
+
+ /* Trailing whitespace ok. */
+ * rx++ = '[';
+ * rx++ = ' ';
+ * rx++ = '\t';
+ * rx++ = ']';
+ * rx++ = '*';
+
+ /* But anchor it after that. */
+ * rx++ = '$';
+ * rx = '\0';
+
+ CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t));
+ reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB);
+
+ if (reg_err == 0)
+ return NULL;
+ else
+ {
+ static char msg[80];
+
+ regerror (reg_err, (regex_t *) CGEN_INSN_RX (insn), msg, 80);
+ regfree ((regex_t *) CGEN_INSN_RX (insn));
+ free (CGEN_INSN_RX (insn));
+ (CGEN_INSN_RX (insn)) = NULL;
+ return msg;
+ }
+}
+
+
+/* Default insn parser.
+
+ The syntax string is scanned and operands are parsed and stored in FIELDS.
+ Relocs are queued as we go via other callbacks.
+
+ ??? Note that this is currently an all-or-nothing parser. If we fail to
+ parse the instruction, we return 0 and the caller will start over from
+ the beginning. Backtracking will be necessary in parsing subexpressions,
+ but that can be handled there. Not handling backtracking here may get
+ expensive in the case of the m68k. Deal with later.
+
+ Returns NULL for success, an error message for failure. */
+
+static const char *
+parse_insn_normal (cd, insn, strp, fields)
+ CGEN_CPU_DESC cd;
+ const CGEN_INSN *insn;
+ const char **strp;
+ CGEN_FIELDS *fields;
+{
+ /* ??? Runtime added insns not handled yet. */
+ const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
+ const char *str = *strp;
+ const char *errmsg;
+ const char *p;
+ const CGEN_SYNTAX_CHAR_TYPE * syn;
+#ifdef CGEN_MNEMONIC_OPERANDS
+ /* FIXME: wip */
+ int past_opcode_p;
+#endif
+
+ /* For now we assume the mnemonic is first (there are no leading operands).
+ We can parse it without needing to set up operand parsing.
+ GAS's input scrubber will ensure mnemonics are lowercase, but we may
+ not be called from GAS. */
+ p = CGEN_INSN_MNEMONIC (insn);
+ while (*p && TOLOWER (*p) == TOLOWER (*str))
+ ++p, ++str;
+
+ if (* p)
+ return _("unrecognized instruction");
+
+#ifndef CGEN_MNEMONIC_OPERANDS
+ if (* str && ! ISSPACE (* str))
+ return _("unrecognized instruction");
+#endif
+
+ CGEN_INIT_PARSE (cd);
+ cgen_init_parse_operand (cd);
+#ifdef CGEN_MNEMONIC_OPERANDS
+ past_opcode_p = 0;
+#endif
+
+ /* We don't check for (*str != '\0') here because we want to parse
+ any trailing fake arguments in the syntax string. */
+ syn = CGEN_SYNTAX_STRING (syntax);
+
+ /* Mnemonics come first for now, ensure valid string. */
+ if (! CGEN_SYNTAX_MNEMONIC_P (* syn))
+ abort ();
+
+ ++syn;
+
+ while (* syn != 0)
+ {
+ /* Non operand chars must match exactly. */
+ if (CGEN_SYNTAX_CHAR_P (* syn))
+ {
+ /* FIXME: While we allow for non-GAS callers above, we assume the
+ first char after the mnemonic part is a space. */
+ /* FIXME: We also take inappropriate advantage of the fact that
+ GAS's input scrubber will remove extraneous blanks. */
+ if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn)))
+ {
+#ifdef CGEN_MNEMONIC_OPERANDS
+ if (CGEN_SYNTAX_CHAR(* syn) == ' ')
+ past_opcode_p = 1;
+#endif
+ ++ syn;
+ ++ str;
+ }
+ else if (*str)
+ {
+ /* Syntax char didn't match. Can't be this insn. */
+ static char msg [80];
+
+ /* xgettext:c-format */
+ sprintf (msg, _("syntax error (expected char `%c', found `%c')"),
+ CGEN_SYNTAX_CHAR(*syn), *str);
+ return msg;
+ }
+ else
+ {
+ /* Ran out of input. */
+ static char msg [80];
+
+ /* xgettext:c-format */
+ sprintf (msg, _("syntax error (expected char `%c', found end of instruction)"),
+ CGEN_SYNTAX_CHAR(*syn));
+ return msg;
+ }
+ continue;
+ }
+
+ /* We have an operand of some sort. */
+ errmsg = xstormy16_cgen_parse_operand (cd, CGEN_SYNTAX_FIELD (*syn),
+ &str, fields);
+ if (errmsg)
+ return errmsg;
+
+ /* Done with this operand, continue with next one. */
+ ++ syn;
+ }
+
+ /* If we're at the end of the syntax string, we're done. */
+ if (* syn == 0)
+ {
+ /* FIXME: For the moment we assume a valid `str' can only contain
+ blanks now. IE: We needn't try again with a longer version of
+ the insn and it is assumed that longer versions of insns appear
+ before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */
+ while (ISSPACE (* str))
+ ++ str;
+
+ if (* str != '\0')
+ return _("junk at end of line"); /* FIXME: would like to include `str' */
+
+ return NULL;
+ }
+
+ /* We couldn't parse it. */
+ return _("unrecognized instruction");
+}
+
+/* Main entry point.
+ This routine is called for each instruction to be assembled.
+ STR points to the insn to be assembled.
+ We assume all necessary tables have been initialized.
+ The assembled instruction, less any fixups, is stored in BUF.
+ Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value
+ still needs to be converted to target byte order, otherwise BUF is an array
+ of bytes in target byte order.
+ The result is a pointer to the insn's entry in the opcode table,
+ or NULL if an error occured (an error message will have already been
+ printed).
+
+ Note that when processing (non-alias) macro-insns,
+ this function recurses.
+
+ ??? It's possible to make this cpu-independent.
+ One would have to deal with a few minor things.
+ At this point in time doing so would be more of a curiosity than useful
+ [for example this file isn't _that_ big], but keeping the possibility in
+ mind helps keep the design clean. */
+
+const CGEN_INSN *
+xstormy16_cgen_assemble_insn (cd, str, fields, buf, errmsg)
+ CGEN_CPU_DESC cd;
+ const char *str;
+ CGEN_FIELDS *fields;
+ CGEN_INSN_BYTES_PTR buf;
+ char **errmsg;
+{
+ const char *start;
+ CGEN_INSN_LIST *ilist;
+ const char *parse_errmsg = NULL;
+ const char *insert_errmsg = NULL;
+ int recognized_mnemonic = 0;
+
+ /* Skip leading white space. */
+ while (ISSPACE (* str))
+ ++ str;
+
+ /* The instructions are stored in hashed lists.
+ Get the first in the list. */
+ ilist = CGEN_ASM_LOOKUP_INSN (cd, str);
+
+ /* Keep looking until we find a match. */
+ start = str;
+ for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist))
+ {
+ const CGEN_INSN *insn = ilist->insn;
+ recognized_mnemonic = 1;
+
+#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+ /* Not usually needed as unsupported opcodes
+ shouldn't be in the hash lists. */
+ /* Is this insn supported by the selected cpu? */
+ if (! xstormy16_cgen_insn_supported (cd, insn))
+ continue;
+#endif
+ /* If the RELAX attribute is set, this is an insn that shouldn't be
+ chosen immediately. Instead, it is used during assembler/linker
+ relaxation if possible. */
+ if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAX) != 0)
+ continue;
+
+ str = start;
+
+ /* Skip this insn if str doesn't look right lexically. */
+ if (CGEN_INSN_RX (insn) != NULL &&
+ regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH)
+ continue;
+
+ /* Allow parse/insert handlers to obtain length of insn. */
+ CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
+
+ parse_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields);
+ if (parse_errmsg != NULL)
+ continue;
+
+ /* ??? 0 is passed for `pc'. */
+ insert_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf,
+ (bfd_vma) 0);
+ if (insert_errmsg != NULL)
+ continue;
+
+ /* It is up to the caller to actually output the insn and any
+ queued relocs. */
+ return insn;
+ }
+
+ {
+ static char errbuf[150];
+#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS
+ const char *tmp_errmsg;
+
+ /* If requesting verbose error messages, use insert_errmsg.
+ Failing that, use parse_errmsg. */
+ tmp_errmsg = (insert_errmsg ? insert_errmsg :
+ parse_errmsg ? parse_errmsg :
+ recognized_mnemonic ?
+ _("unrecognized form of instruction") :
+ _("unrecognized instruction"));
+
+ if (strlen (start) > 50)
+ /* xgettext:c-format */
+ sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start);
+ else
+ /* xgettext:c-format */
+ sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start);
+#else
+ if (strlen (start) > 50)
+ /* xgettext:c-format */
+ sprintf (errbuf, _("bad instruction `%.50s...'"), start);
+ else
+ /* xgettext:c-format */
+ sprintf (errbuf, _("bad instruction `%.50s'"), start);
+#endif
+
+ *errmsg = errbuf;
+ return NULL;
+ }
+}
+
+#if 0 /* This calls back to GAS which we can't do without care. */
+
+/* Record each member of OPVALS in the assembler's symbol table.
+ This lets GAS parse registers for us.
+ ??? Interesting idea but not currently used. */
+
+/* Record each member of OPVALS in the assembler's symbol table.
+ FIXME: Not currently used. */
+
+void
+xstormy16_cgen_asm_hash_keywords (cd, opvals)
+ CGEN_CPU_DESC cd;
+ CGEN_KEYWORD *opvals;
+{
+ CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL);
+ const CGEN_KEYWORD_ENTRY * ke;
+
+ while ((ke = cgen_keyword_search_next (& search)) != NULL)
+ {
+#if 0 /* Unnecessary, should be done in the search routine. */
+ if (! xstormy16_cgen_opval_supported (ke))
+ continue;
+#endif
+ cgen_asm_record_register (cd, ke->name, ke->value);
+ }
+}
+
+#endif /* 0 */
diff --git a/opcodes/xstormy16-desc.c b/opcodes/xstormy16-desc.c
new file mode 100644
index 0000000..5d22acd
--- /dev/null
+++ b/opcodes/xstormy16-desc.c
@@ -0,0 +1,1399 @@
+/* CPU data for xstormy16.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#include "sysdep.h"
+#include <stdio.h>
+#include <stdarg.h>
+#include "ansidecl.h"
+#include "bfd.h"
+#include "symcat.h"
+#include "xstormy16-desc.h"
+#include "xstormy16-opc.h"
+#include "opintl.h"
+#include "libiberty.h"
+
+/* Attributes. */
+
+static const CGEN_ATTR_ENTRY bool_attr[] =
+{
+ { "#f", 0 },
+ { "#t", 1 },
+ { 0, 0 }
+};
+
+static const CGEN_ATTR_ENTRY MACH_attr[] =
+{
+ { "base", MACH_BASE },
+ { "xstormy16", MACH_XSTORMY16 },
+ { "max", MACH_MAX },
+ { 0, 0 }
+};
+
+static const CGEN_ATTR_ENTRY ISA_attr[] =
+{
+ { "xstormy16", ISA_XSTORMY16 },
+ { "max", ISA_MAX },
+ { 0, 0 }
+};
+
+const CGEN_ATTR_TABLE xstormy16_cgen_ifield_attr_table[] =
+{
+ { "MACH", & MACH_attr[0], & MACH_attr[0] },
+ { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+ { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
+ { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
+ { "RESERVED", &bool_attr[0], &bool_attr[0] },
+ { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
+ { "SIGNED", &bool_attr[0], &bool_attr[0] },
+ { 0, 0, 0 }
+};
+
+const CGEN_ATTR_TABLE xstormy16_cgen_hardware_attr_table[] =
+{
+ { "MACH", & MACH_attr[0], & MACH_attr[0] },
+ { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+ { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
+ { "PC", &bool_attr[0], &bool_attr[0] },
+ { "PROFILE", &bool_attr[0], &bool_attr[0] },
+ { 0, 0, 0 }
+};
+
+const CGEN_ATTR_TABLE xstormy16_cgen_operand_attr_table[] =
+{
+ { "MACH", & MACH_attr[0], & MACH_attr[0] },
+ { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+ { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
+ { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
+ { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
+ { "SIGNED", &bool_attr[0], &bool_attr[0] },
+ { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
+ { "RELAX", &bool_attr[0], &bool_attr[0] },
+ { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
+ { 0, 0, 0 }
+};
+
+const CGEN_ATTR_TABLE xstormy16_cgen_insn_attr_table[] =
+{
+ { "MACH", & MACH_attr[0], & MACH_attr[0] },
+ { "ALIAS", &bool_attr[0], &bool_attr[0] },
+ { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+ { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
+ { "COND-CTI", &bool_attr[0], &bool_attr[0] },
+ { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
+ { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
+ { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
+ { "RELAX", &bool_attr[0], &bool_attr[0] },
+ { "NO-DIS", &bool_attr[0], &bool_attr[0] },
+ { "PBB", &bool_attr[0], &bool_attr[0] },
+ { 0, 0, 0 }
+};
+
+/* Instruction set variants. */
+
+static const CGEN_ISA xstormy16_cgen_isa_table[] = {
+ { "xstormy16", 32, 32, 16, 32 },
+ { 0, 0, 0, 0, 0 }
+};
+
+/* Machine variants. */
+
+static const CGEN_MACH xstormy16_cgen_mach_table[] = {
+ { "xstormy16", "xstormy16", MACH_XSTORMY16, 16 },
+ { 0, 0, 0, 0 }
+};
+
+static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_gr_names_entries[] =
+{
+ { "r0", 0, {0, {0}}, 0, 0 },
+ { "r1", 1, {0, {0}}, 0, 0 },
+ { "r2", 2, {0, {0}}, 0, 0 },
+ { "r3", 3, {0, {0}}, 0, 0 },
+ { "r4", 4, {0, {0}}, 0, 0 },
+ { "r5", 5, {0, {0}}, 0, 0 },
+ { "r6", 6, {0, {0}}, 0, 0 },
+ { "r7", 7, {0, {0}}, 0, 0 },
+ { "r8", 8, {0, {0}}, 0, 0 },
+ { "r9", 9, {0, {0}}, 0, 0 },
+ { "r10", 10, {0, {0}}, 0, 0 },
+ { "r11", 11, {0, {0}}, 0, 0 },
+ { "r12", 12, {0, {0}}, 0, 0 },
+ { "r13", 13, {0, {0}}, 0, 0 },
+ { "r14", 14, {0, {0}}, 0, 0 },
+ { "r15", 15, {0, {0}}, 0, 0 },
+ { "psw", 14, {0, {0}}, 0, 0 },
+ { "sp", 15, {0, {0}}, 0, 0 }
+};
+
+CGEN_KEYWORD xstormy16_cgen_opval_gr_names =
+{
+ & xstormy16_cgen_opval_gr_names_entries[0],
+ 18,
+ 0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_gr_Rbj_names_entries[] =
+{
+ { "r8", 0, {0, {0}}, 0, 0 },
+ { "r9", 1, {0, {0}}, 0, 0 }
+};
+
+CGEN_KEYWORD xstormy16_cgen_opval_gr_Rbj_names =
+{
+ & xstormy16_cgen_opval_gr_Rbj_names_entries[0],
+ 2,
+ 0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_h_branchcond_entries[] =
+{
+ { "ge", 0, {0, {0}}, 0, 0 },
+ { "nc", 1, {0, {0}}, 0, 0 },
+ { "lt", 2, {0, {0}}, 0, 0 },
+ { "c", 3, {0, {0}}, 0, 0 },
+ { "gt", 4, {0, {0}}, 0, 0 },
+ { "hi", 5, {0, {0}}, 0, 0 },
+ { "le", 6, {0, {0}}, 0, 0 },
+ { "ls", 7, {0, {0}}, 0, 0 },
+ { "pl", 8, {0, {0}}, 0, 0 },
+ { "nv", 9, {0, {0}}, 0, 0 },
+ { "mi", 10, {0, {0}}, 0, 0 },
+ { "v", 11, {0, {0}}, 0, 0 },
+ { "nz.b", 12, {0, {0}}, 0, 0 },
+ { "nz", 13, {0, {0}}, 0, 0 },
+ { "z.b", 14, {0, {0}}, 0, 0 },
+ { "z", 15, {0, {0}}, 0, 0 }
+};
+
+CGEN_KEYWORD xstormy16_cgen_opval_h_branchcond =
+{
+ & xstormy16_cgen_opval_h_branchcond_entries[0],
+ 16,
+ 0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_h_wordsize_entries[] =
+{
+ { ".b", 0, {0, {0}}, 0, 0 },
+ { ".w", 1, {0, {0}}, 0, 0 },
+ { "", 1, {0, {0}}, 0, 0 }
+};
+
+CGEN_KEYWORD xstormy16_cgen_opval_h_wordsize =
+{
+ & xstormy16_cgen_opval_h_wordsize_entries[0],
+ 3,
+ 0, 0, 0, 0, ""
+};
+
+
+/* The hardware table. */
+
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define A(a) (1 << CGEN_HW_##a)
+#else
+#define A(a) (1 << CGEN_HW_/**/a)
+#endif
+
+const CGEN_HW_ENTRY xstormy16_cgen_hw_table[] =
+{
+ { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+ { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+ { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+ { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+ { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+ { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { (1<<MACH_BASE) } } },
+ { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_gr_names, { 0, { (1<<MACH_BASE) } } },
+ { "h-Rbj", HW_H_RBJ, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_gr_Rbj_names, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
+ { "h-Rpsw", HW_H_RPSW, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
+ { "h-z8", HW_H_Z8, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
+ { "h-z16", HW_H_Z16, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
+ { "h-cy", HW_H_CY, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
+ { "h-hc", HW_H_HC, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
+ { "h-ov", HW_H_OV, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
+ { "h-pt", HW_H_PT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
+ { "h-s", HW_H_S, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
+ { "h-branchcond", HW_H_BRANCHCOND, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_h_branchcond, { 0, { (1<<MACH_BASE) } } },
+ { "h-wordsize", HW_H_WORDSIZE, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_h_wordsize, { 0, { (1<<MACH_BASE) } } },
+ { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
+};
+
+#undef A
+
+
+/* The instruction field table. */
+
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define A(a) (1 << CGEN_IFLD_##a)
+#else
+#define A(a) (1 << CGEN_IFLD_/**/a)
+#endif
+
+const CGEN_IFLD xstormy16_cgen_ifld_table[] =
+{
+ { XSTORMY16_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } },
+ { XSTORMY16_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } },
+ { XSTORMY16_F_RD, "f-Rd", 0, 32, 12, 4, { 0, { (1<<MACH_BASE) } } },
+ { XSTORMY16_F_RDM, "f-Rdm", 0, 32, 13, 3, { 0, { (1<<MACH_BASE) } } },
+ { XSTORMY16_F_RM, "f-Rm", 0, 32, 4, 3, { 0, { (1<<MACH_BASE) } } },
+ { XSTORMY16_F_RS, "f-Rs", 0, 32, 8, 4, { 0, { (1<<MACH_BASE) } } },
+ { XSTORMY16_F_RB, "f-Rb", 0, 32, 17, 3, { 0, { (1<<MACH_BASE) } } },
+ { XSTORMY16_F_RBJ, "f-Rbj", 0, 32, 11, 1, { 0, { (1<<MACH_BASE) } } },
+ { XSTORMY16_F_OP1, "f-op1", 0, 32, 0, 4, { 0, { (1<<MACH_BASE) } } },
+ { XSTORMY16_F_OP2, "f-op2", 0, 32, 4, 4, { 0, { (1<<MACH_BASE) } } },
+ { XSTORMY16_F_OP2A, "f-op2a", 0, 32, 4, 3, { 0, { (1<<MACH_BASE) } } },
+ { XSTORMY16_F_OP2M, "f-op2m", 0, 32, 7, 1, { 0, { (1<<MACH_BASE) } } },
+ { XSTORMY16_F_OP3, "f-op3", 0, 32, 8, 4, { 0, { (1<<MACH_BASE) } } },
+ { XSTORMY16_F_OP3A, "f-op3a", 0, 32, 8, 2, { 0, { (1<<MACH_BASE) } } },
+ { XSTORMY16_F_OP3B, "f-op3b", 0, 32, 8, 3, { 0, { (1<<MACH_BASE) } } },
+ { XSTORMY16_F_OP4, "f-op4", 0, 32, 12, 4, { 0, { (1<<MACH_BASE) } } },
+ { XSTORMY16_F_OP4M, "f-op4m", 0, 32, 12, 1, { 0, { (1<<MACH_BASE) } } },
+ { XSTORMY16_F_OP4B, "f-op4b", 0, 32, 15, 1, { 0, { (1<<MACH_BASE) } } },
+ { XSTORMY16_F_OP5, "f-op5", 0, 32, 16, 4, { 0, { (1<<MACH_BASE) } } },
+ { XSTORMY16_F_OP5A, "f-op5a", 0, 32, 16, 1, { 0, { (1<<MACH_BASE) } } },
+ { XSTORMY16_F_OP, "f-op", 0, 32, 0, 16, { 0, { (1<<MACH_BASE) } } },
+ { XSTORMY16_F_IMM2, "f-imm2", 0, 32, 10, 2, { 0, { (1<<MACH_BASE) } } },
+ { XSTORMY16_F_IMM3, "f-imm3", 0, 32, 4, 3, { 0, { (1<<MACH_BASE) } } },
+ { XSTORMY16_F_IMM3B, "f-imm3b", 0, 32, 17, 3, { 0, { (1<<MACH_BASE) } } },
+ { XSTORMY16_F_IMM4, "f-imm4", 0, 32, 8, 4, { 0, { (1<<MACH_BASE) } } },
+ { XSTORMY16_F_IMM8, "f-imm8", 0, 32, 8, 8, { 0, { (1<<MACH_BASE) } } },
+ { XSTORMY16_F_IMM12, "f-imm12", 0, 32, 20, 12, { 0, { (1<<MACH_BASE) } } },
+ { XSTORMY16_F_IMM16, "f-imm16", 0, 32, 16, 16, { 0|A(SIGN_OPT), { (1<<MACH_BASE) } } },
+ { XSTORMY16_F_LMEM8, "f-lmem8", 0, 32, 8, 8, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } },
+ { XSTORMY16_F_HMEM8, "f-hmem8", 0, 32, 8, 8, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } },
+ { XSTORMY16_F_REL8_2, "f-rel8-2", 0, 32, 8, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
+ { XSTORMY16_F_REL8_4, "f-rel8-4", 0, 32, 8, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
+ { XSTORMY16_F_REL12, "f-rel12", 0, 32, 20, 12, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
+ { XSTORMY16_F_REL12A, "f-rel12a", 0, 32, 4, 11, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
+ { XSTORMY16_F_ABS24_1, "f-abs24-1", 0, 32, 8, 8, { 0, { (1<<MACH_BASE) } } },
+ { XSTORMY16_F_ABS24_2, "f-abs24-2", 0, 32, 16, 16, { 0, { (1<<MACH_BASE) } } },
+ { 0, 0, 0, 0, 0, 0, {0, {0}} }
+};
+
+#undef A
+
+
+/* The operand table. */
+
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define A(a) (1 << CGEN_OPERAND_##a)
+#else
+#define A(a) (1 << CGEN_OPERAND_/**/a)
+#endif
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define OPERAND(op) XSTORMY16_OPERAND_##op
+#else
+#define OPERAND(op) XSTORMY16_OPERAND_/**/op
+#endif
+
+const CGEN_OPERAND xstormy16_cgen_operand_table[] =
+{
+/* pc: program counter */
+ { "pc", XSTORMY16_OPERAND_PC, HW_H_PC, 0, 0,
+ { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
+/* psw-z8: */
+ { "psw-z8", XSTORMY16_OPERAND_PSW_Z8, HW_H_Z8, 0, 0,
+ { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
+/* psw-z16: */
+ { "psw-z16", XSTORMY16_OPERAND_PSW_Z16, HW_H_Z16, 0, 0,
+ { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
+/* psw-cy: */
+ { "psw-cy", XSTORMY16_OPERAND_PSW_CY, HW_H_CY, 0, 0,
+ { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
+/* psw-hc: */
+ { "psw-hc", XSTORMY16_OPERAND_PSW_HC, HW_H_HC, 0, 0,
+ { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
+/* psw-ov: */
+ { "psw-ov", XSTORMY16_OPERAND_PSW_OV, HW_H_OV, 0, 0,
+ { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
+/* psw-pt: */
+ { "psw-pt", XSTORMY16_OPERAND_PSW_PT, HW_H_PT, 0, 0,
+ { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
+/* psw-s: */
+ { "psw-s", XSTORMY16_OPERAND_PSW_S, HW_H_S, 0, 0,
+ { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
+/* Rd: general register destination */
+ { "Rd", XSTORMY16_OPERAND_RD, HW_H_GR, 12, 4,
+ { 0, { (1<<MACH_BASE) } } },
+/* Rdm: general register destination */
+ { "Rdm", XSTORMY16_OPERAND_RDM, HW_H_GR, 13, 3,
+ { 0, { (1<<MACH_BASE) } } },
+/* Rm: general register for memory */
+ { "Rm", XSTORMY16_OPERAND_RM, HW_H_GR, 4, 3,
+ { 0, { (1<<MACH_BASE) } } },
+/* Rs: general register source */
+ { "Rs", XSTORMY16_OPERAND_RS, HW_H_GR, 8, 4,
+ { 0, { (1<<MACH_BASE) } } },
+/* Rb: base register */
+ { "Rb", XSTORMY16_OPERAND_RB, HW_H_GR, 17, 3,
+ { 0, { (1<<MACH_BASE) } } },
+/* Rbj: base register for jump */
+ { "Rbj", XSTORMY16_OPERAND_RBJ, HW_H_RBJ, 11, 1,
+ { 0, { (1<<MACH_BASE) } } },
+/* bcond2: branch condition opcode */
+ { "bcond2", XSTORMY16_OPERAND_BCOND2, HW_H_BRANCHCOND, 4, 4,
+ { 0, { (1<<MACH_BASE) } } },
+/* ws2: word size opcode */
+ { "ws2", XSTORMY16_OPERAND_WS2, HW_H_WORDSIZE, 7, 1,
+ { 0, { (1<<MACH_BASE) } } },
+/* bcond5: branch condition opcode */
+ { "bcond5", XSTORMY16_OPERAND_BCOND5, HW_H_BRANCHCOND, 16, 4,
+ { 0, { (1<<MACH_BASE) } } },
+/* imm2: 2 bit unsigned immediate */
+ { "imm2", XSTORMY16_OPERAND_IMM2, HW_H_UINT, 10, 2,
+ { 0, { (1<<MACH_BASE) } } },
+/* imm3: 3 bit unsigned immediate */
+ { "imm3", XSTORMY16_OPERAND_IMM3, HW_H_UINT, 4, 3,
+ { 0, { (1<<MACH_BASE) } } },
+/* imm3b: 3 bit unsigned immediate for bit tests */
+ { "imm3b", XSTORMY16_OPERAND_IMM3B, HW_H_UINT, 17, 3,
+ { 0, { (1<<MACH_BASE) } } },
+/* imm4: 4 bit unsigned immediate */
+ { "imm4", XSTORMY16_OPERAND_IMM4, HW_H_UINT, 8, 4,
+ { 0, { (1<<MACH_BASE) } } },
+/* imm8: 8 bit unsigned immediate */
+ { "imm8", XSTORMY16_OPERAND_IMM8, HW_H_UINT, 8, 8,
+ { 0, { (1<<MACH_BASE) } } },
+/* imm8small: 8 bit unsigned immediate */
+ { "imm8small", XSTORMY16_OPERAND_IMM8SMALL, HW_H_UINT, 8, 8,
+ { 0, { (1<<MACH_BASE) } } },
+/* imm12: 12 bit signed immediate */
+ { "imm12", XSTORMY16_OPERAND_IMM12, HW_H_SINT, 20, 12,
+ { 0, { (1<<MACH_BASE) } } },
+/* imm16: 16 bit immediate */
+ { "imm16", XSTORMY16_OPERAND_IMM16, HW_H_UINT, 16, 16,
+ { 0|A(SIGN_OPT), { (1<<MACH_BASE) } } },
+/* lmem8: 8 bit unsigned immediate low memory */
+ { "lmem8", XSTORMY16_OPERAND_LMEM8, HW_H_UINT, 8, 8,
+ { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } },
+/* hmem8: 8 bit unsigned immediate high memory */
+ { "hmem8", XSTORMY16_OPERAND_HMEM8, HW_H_UINT, 8, 8,
+ { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } },
+/* rel8-2: 8 bit relative address */
+ { "rel8-2", XSTORMY16_OPERAND_REL8_2, HW_H_UINT, 8, 8,
+ { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
+/* rel8-4: 8 bit relative address */
+ { "rel8-4", XSTORMY16_OPERAND_REL8_4, HW_H_UINT, 8, 8,
+ { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
+/* rel12: 12 bit relative address */
+ { "rel12", XSTORMY16_OPERAND_REL12, HW_H_UINT, 20, 12,
+ { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
+/* rel12a: 12 bit relative address */
+ { "rel12a", XSTORMY16_OPERAND_REL12A, HW_H_UINT, 4, 11,
+ { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
+/* abs24: 24 bit absolute address */
+ { "abs24", XSTORMY16_OPERAND_ABS24, HW_H_UINT, 8, 24,
+ { 0|A(ABS_ADDR)|A(VIRTUAL), { (1<<MACH_BASE) } } },
+/* psw: program status word */
+ { "psw", XSTORMY16_OPERAND_PSW, HW_H_GR, 0, 0,
+ { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
+/* Rpsw: N0-N3 of the program status word */
+ { "Rpsw", XSTORMY16_OPERAND_RPSW, HW_H_RPSW, 0, 0,
+ { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
+/* sp: stack pointer */
+ { "sp", XSTORMY16_OPERAND_SP, HW_H_GR, 0, 0,
+ { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
+/* R0: R0 */
+ { "R0", XSTORMY16_OPERAND_R0, HW_H_GR, 0, 0,
+ { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
+/* R1: R1 */
+ { "R1", XSTORMY16_OPERAND_R1, HW_H_GR, 0, 0,
+ { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
+/* R2: R2 */
+ { "R2", XSTORMY16_OPERAND_R2, HW_H_GR, 0, 0,
+ { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
+/* R8: R8 */
+ { "R8", XSTORMY16_OPERAND_R8, HW_H_GR, 0, 0,
+ { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
+ { 0, 0, 0, 0, 0, {0, {0}} }
+};
+
+#undef A
+
+
+/* The instruction table. */
+
+#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define A(a) (1 << CGEN_INSN_##a)
+#else
+#define A(a) (1 << CGEN_INSN_/**/a)
+#endif
+
+static const CGEN_IBASE xstormy16_cgen_insn_table[MAX_INSNS] =
+{
+ /* Special null first entry.
+ A `num' value of zero is thus invalid.
+ Also, the special `invalid' insn resides here. */
+ { 0, 0, 0, 0, {0, {0}} },
+/* mov$ws2 $lmem8,#$imm16 */
+ {
+ XSTORMY16_INSN_MOVLMEMIMM, "movlmemimm", "mov", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* mov$ws2 $hmem8,#$imm16 */
+ {
+ XSTORMY16_INSN_MOVHMEMIMM, "movhmemimm", "mov", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* mov$ws2 $Rm,$lmem8 */
+ {
+ XSTORMY16_INSN_MOVLGRMEM, "movlgrmem", "mov", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* mov$ws2 $Rm,$hmem8 */
+ {
+ XSTORMY16_INSN_MOVHGRMEM, "movhgrmem", "mov", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* mov$ws2 $lmem8,$Rm */
+ {
+ XSTORMY16_INSN_MOVLMEMGR, "movlmemgr", "mov", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* mov$ws2 $hmem8,$Rm */
+ {
+ XSTORMY16_INSN_MOVHMEMGR, "movhmemgr", "mov", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* mov$ws2 $Rdm,($Rs) */
+ {
+ XSTORMY16_INSN_MOVGRGRI, "movgrgri", "mov", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* mov$ws2 $Rdm,($Rs++) */
+ {
+ XSTORMY16_INSN_MOVGRGRIPOSTINC, "movgrgripostinc", "mov", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* mov$ws2 $Rdm,(--$Rs) */
+ {
+ XSTORMY16_INSN_MOVGRGRIPREDEC, "movgrgripredec", "mov", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* mov$ws2 ($Rs),$Rdm */
+ {
+ XSTORMY16_INSN_MOVGRIGR, "movgrigr", "mov", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* mov$ws2 ($Rs++),$Rdm */
+ {
+ XSTORMY16_INSN_MOVGRIPOSTINCGR, "movgripostincgr", "mov", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* mov$ws2 (--$Rs),$Rdm */
+ {
+ XSTORMY16_INSN_MOVGRIPREDECGR, "movgripredecgr", "mov", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* mov$ws2 $Rdm,($Rs,$imm12) */
+ {
+ XSTORMY16_INSN_MOVGRGRII, "movgrgrii", "mov", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* mov$ws2 $Rdm,($Rs++,$imm12) */
+ {
+ XSTORMY16_INSN_MOVGRGRIIPOSTINC, "movgrgriipostinc", "mov", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* mov$ws2 $Rdm,(--$Rs,$imm12) */
+ {
+ XSTORMY16_INSN_MOVGRGRIIPREDEC, "movgrgriipredec", "mov", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* mov$ws2 ($Rs,$imm12),$Rdm */
+ {
+ XSTORMY16_INSN_MOVGRIIGR, "movgriigr", "mov", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* mov$ws2 ($Rs++,$imm12),$Rdm */
+ {
+ XSTORMY16_INSN_MOVGRIIPOSTINCGR, "movgriipostincgr", "mov", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* mov$ws2 (--$Rs,$imm12),$Rdm */
+ {
+ XSTORMY16_INSN_MOVGRIIPREDECGR, "movgriipredecgr", "mov", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* mov $Rd,$Rs */
+ {
+ XSTORMY16_INSN_MOVGRGR, "movgrgr", "mov", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* mov.w Rx,#$imm8 */
+ {
+ XSTORMY16_INSN_MOVWIMM8, "movwimm8", "mov.w", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* mov.w $Rm,#$imm8small */
+ {
+ XSTORMY16_INSN_MOVWGRIMM8, "movwgrimm8", "mov.w", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* mov.w $Rd,#$imm16 */
+ {
+ XSTORMY16_INSN_MOVWGRIMM16, "movwgrimm16", "mov.w", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* mov.b $Rd,RxL */
+ {
+ XSTORMY16_INSN_MOVLOWGR, "movlowgr", "mov.b", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* mov.b $Rd,RxH */
+ {
+ XSTORMY16_INSN_MOVHIGHGR, "movhighgr", "mov.b", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* movf$ws2 $Rdm,($Rs) */
+ {
+ XSTORMY16_INSN_MOVFGRGRI, "movfgrgri", "movf", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* movf$ws2 $Rdm,($Rs++) */
+ {
+ XSTORMY16_INSN_MOVFGRGRIPOSTINC, "movfgrgripostinc", "movf", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* movf$ws2 $Rdm,(--$Rs) */
+ {
+ XSTORMY16_INSN_MOVFGRGRIPREDEC, "movfgrgripredec", "movf", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* movf$ws2 ($Rs),$Rdm */
+ {
+ XSTORMY16_INSN_MOVFGRIGR, "movfgrigr", "movf", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* movf$ws2 ($Rs++),$Rdm */
+ {
+ XSTORMY16_INSN_MOVFGRIPOSTINCGR, "movfgripostincgr", "movf", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* movf$ws2 (--$Rs),$Rdm */
+ {
+ XSTORMY16_INSN_MOVFGRIPREDECGR, "movfgripredecgr", "movf", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* movf$ws2 $Rdm,($Rb,$Rs,$imm12) */
+ {
+ XSTORMY16_INSN_MOVFGRGRII, "movfgrgrii", "movf", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* movf$ws2 $Rdm,($Rb,$Rs++,$imm12) */
+ {
+ XSTORMY16_INSN_MOVFGRGRIIPOSTINC, "movfgrgriipostinc", "movf", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* movf$ws2 $Rdm,($Rb,--$Rs,$imm12) */
+ {
+ XSTORMY16_INSN_MOVFGRGRIIPREDEC, "movfgrgriipredec", "movf", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* movf$ws2 ($Rb,$Rs,$imm12),$Rdm */
+ {
+ XSTORMY16_INSN_MOVFGRIIGR, "movfgriigr", "movf", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* movf$ws2 ($Rb,$Rs++,$imm12),$Rdm */
+ {
+ XSTORMY16_INSN_MOVFGRIIPOSTINCGR, "movfgriipostincgr", "movf", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* movf$ws2 ($Rb,--$Rs,$imm12),$Rdm */
+ {
+ XSTORMY16_INSN_MOVFGRIIPREDECGR, "movfgriipredecgr", "movf", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* mask $Rd,$Rs */
+ {
+ XSTORMY16_INSN_MASKGRGR, "maskgrgr", "mask", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* mask $Rd,#$imm16 */
+ {
+ XSTORMY16_INSN_MASKGRIMM16, "maskgrimm16", "mask", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* push $Rd */
+ {
+ XSTORMY16_INSN_PUSHGR, "pushgr", "push", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* pop $Rd */
+ {
+ XSTORMY16_INSN_POPGR, "popgr", "pop", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* swpn $Rd */
+ {
+ XSTORMY16_INSN_SWPN, "swpn", "swpn", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* swpb $Rd */
+ {
+ XSTORMY16_INSN_SWPB, "swpb", "swpb", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* swpw $Rd,$Rs */
+ {
+ XSTORMY16_INSN_SWPW, "swpw", "swpw", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* and $Rd,$Rs */
+ {
+ XSTORMY16_INSN_ANDGRGR, "andgrgr", "and", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* and Rx,#$imm8 */
+ {
+ XSTORMY16_INSN_ANDIMM8, "andimm8", "and", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* and $Rd,#$imm16 */
+ {
+ XSTORMY16_INSN_ANDGRIMM16, "andgrimm16", "and", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* or $Rd,$Rs */
+ {
+ XSTORMY16_INSN_ORGRGR, "orgrgr", "or", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* or Rx,#$imm8 */
+ {
+ XSTORMY16_INSN_ORIMM8, "orimm8", "or", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* or $Rd,#$imm16 */
+ {
+ XSTORMY16_INSN_ORGRIMM16, "orgrimm16", "or", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* xor $Rd,$Rs */
+ {
+ XSTORMY16_INSN_XORGRGR, "xorgrgr", "xor", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* xor Rx,#$imm8 */
+ {
+ XSTORMY16_INSN_XORIMM8, "xorimm8", "xor", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* xor $Rd,#$imm16 */
+ {
+ XSTORMY16_INSN_XORGRIMM16, "xorgrimm16", "xor", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* not $Rd */
+ {
+ XSTORMY16_INSN_NOTGR, "notgr", "not", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* add $Rd,$Rs */
+ {
+ XSTORMY16_INSN_ADDGRGR, "addgrgr", "add", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* add $Rd,#$imm4 */
+ {
+ XSTORMY16_INSN_ADDGRIMM4, "addgrimm4", "add", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* add Rx,#$imm8 */
+ {
+ XSTORMY16_INSN_ADDIMM8, "addimm8", "add", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* add $Rd,#$imm16 */
+ {
+ XSTORMY16_INSN_ADDGRIMM16, "addgrimm16", "add", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* adc $Rd,$Rs */
+ {
+ XSTORMY16_INSN_ADCGRGR, "adcgrgr", "adc", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* adc $Rd,#$imm4 */
+ {
+ XSTORMY16_INSN_ADCGRIMM4, "adcgrimm4", "adc", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* adc Rx,#$imm8 */
+ {
+ XSTORMY16_INSN_ADCIMM8, "adcimm8", "adc", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* adc $Rd,#$imm16 */
+ {
+ XSTORMY16_INSN_ADCGRIMM16, "adcgrimm16", "adc", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* sub $Rd,$Rs */
+ {
+ XSTORMY16_INSN_SUBGRGR, "subgrgr", "sub", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* sub $Rd,#$imm4 */
+ {
+ XSTORMY16_INSN_SUBGRIMM4, "subgrimm4", "sub", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* sub Rx,#$imm8 */
+ {
+ XSTORMY16_INSN_SUBIMM8, "subimm8", "sub", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* sub $Rd,#$imm16 */
+ {
+ XSTORMY16_INSN_SUBGRIMM16, "subgrimm16", "sub", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* sbc $Rd,$Rs */
+ {
+ XSTORMY16_INSN_SBCGRGR, "sbcgrgr", "sbc", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* sbc $Rd,#$imm4 */
+ {
+ XSTORMY16_INSN_SBCGRIMM4, "sbcgrimm4", "sbc", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* sbc Rx,#$imm8 */
+ {
+ XSTORMY16_INSN_SBCGRIMM8, "sbcgrimm8", "sbc", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* sbc $Rd,#$imm16 */
+ {
+ XSTORMY16_INSN_SBCGRIMM16, "sbcgrimm16", "sbc", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* inc $Rd,#$imm2 */
+ {
+ XSTORMY16_INSN_INCGRIMM2, "incgrimm2", "inc", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* dec $Rd,#$imm2 */
+ {
+ XSTORMY16_INSN_DECGRIMM2, "decgrimm2", "dec", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* rrc $Rd,$Rs */
+ {
+ XSTORMY16_INSN_RRCGRGR, "rrcgrgr", "rrc", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* rrc $Rd,#$imm4 */
+ {
+ XSTORMY16_INSN_RRCGRIMM4, "rrcgrimm4", "rrc", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* rlc $Rd,$Rs */
+ {
+ XSTORMY16_INSN_RLCGRGR, "rlcgrgr", "rlc", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* rlc $Rd,#$imm4 */
+ {
+ XSTORMY16_INSN_RLCGRIMM4, "rlcgrimm4", "rlc", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* shr $Rd,$Rs */
+ {
+ XSTORMY16_INSN_SHRGRGR, "shrgrgr", "shr", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* shr $Rd,#$imm4 */
+ {
+ XSTORMY16_INSN_SHRGRIMM, "shrgrimm", "shr", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* shl $Rd,$Rs */
+ {
+ XSTORMY16_INSN_SHLGRGR, "shlgrgr", "shl", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* shl $Rd,#$imm4 */
+ {
+ XSTORMY16_INSN_SHLGRIMM, "shlgrimm", "shl", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* asr $Rd,$Rs */
+ {
+ XSTORMY16_INSN_ASRGRGR, "asrgrgr", "asr", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* asr $Rd,#$imm4 */
+ {
+ XSTORMY16_INSN_ASRGRIMM, "asrgrimm", "asr", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* set1 $Rd,#$imm4 */
+ {
+ XSTORMY16_INSN_SET1GRIMM, "set1grimm", "set1", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* set1 $Rd,$Rs */
+ {
+ XSTORMY16_INSN_SET1GRGR, "set1grgr", "set1", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* set1 $lmem8,#$imm3 */
+ {
+ XSTORMY16_INSN_SET1LMEMIMM, "set1lmemimm", "set1", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* set1 $hmem8,#$imm3 */
+ {
+ XSTORMY16_INSN_SET1HMEMIMM, "set1hmemimm", "set1", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* clr1 $Rd,#$imm4 */
+ {
+ XSTORMY16_INSN_CLR1GRIMM, "clr1grimm", "clr1", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* clr1 $Rd,$Rs */
+ {
+ XSTORMY16_INSN_CLR1GRGR, "clr1grgr", "clr1", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* clr1 $lmem8,#$imm3 */
+ {
+ XSTORMY16_INSN_CLR1LMEMIMM, "clr1lmemimm", "clr1", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* clr1 $hmem8,#$imm3 */
+ {
+ XSTORMY16_INSN_CLR1HMEMIMM, "clr1hmemimm", "clr1", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* cbw $Rd */
+ {
+ XSTORMY16_INSN_CBWGR, "cbwgr", "cbw", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* rev $Rd */
+ {
+ XSTORMY16_INSN_REVGR, "revgr", "rev", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* b$bcond5 $Rd,$Rs,$rel12 */
+ {
+ XSTORMY16_INSN_BCCGRGR, "bccgrgr", "b", 32,
+ { 0|A(COND_CTI), { (1<<MACH_BASE) } }
+ },
+/* b$bcond5 $Rm,#$imm8,$rel12 */
+ {
+ XSTORMY16_INSN_BCCGRIMM8, "bccgrimm8", "b", 32,
+ { 0|A(COND_CTI), { (1<<MACH_BASE) } }
+ },
+/* b$bcond2 Rx,#$imm16,${rel8-4} */
+ {
+ XSTORMY16_INSN_BCCIMM16, "bccimm16", "b", 32,
+ { 0|A(COND_CTI), { (1<<MACH_BASE) } }
+ },
+/* bn $Rd,#$imm4,$rel12 */
+ {
+ XSTORMY16_INSN_BNGRIMM4, "bngrimm4", "bn", 32,
+ { 0|A(COND_CTI), { (1<<MACH_BASE) } }
+ },
+/* bn $Rd,$Rs,$rel12 */
+ {
+ XSTORMY16_INSN_BNGRGR, "bngrgr", "bn", 32,
+ { 0|A(COND_CTI), { (1<<MACH_BASE) } }
+ },
+/* bn $lmem8,#$imm3b,$rel12 */
+ {
+ XSTORMY16_INSN_BNLMEMIMM, "bnlmemimm", "bn", 32,
+ { 0|A(COND_CTI), { (1<<MACH_BASE) } }
+ },
+/* bn $hmem8,#$imm3b,$rel12 */
+ {
+ XSTORMY16_INSN_BNHMEMIMM, "bnhmemimm", "bn", 32,
+ { 0|A(COND_CTI), { (1<<MACH_BASE) } }
+ },
+/* bp $Rd,#$imm4,$rel12 */
+ {
+ XSTORMY16_INSN_BPGRIMM4, "bpgrimm4", "bp", 32,
+ { 0|A(COND_CTI), { (1<<MACH_BASE) } }
+ },
+/* bp $Rd,$Rs,$rel12 */
+ {
+ XSTORMY16_INSN_BPGRGR, "bpgrgr", "bp", 32,
+ { 0|A(COND_CTI), { (1<<MACH_BASE) } }
+ },
+/* bp $lmem8,#$imm3b,$rel12 */
+ {
+ XSTORMY16_INSN_BPLMEMIMM, "bplmemimm", "bp", 32,
+ { 0|A(COND_CTI), { (1<<MACH_BASE) } }
+ },
+/* bp $hmem8,#$imm3b,$rel12 */
+ {
+ XSTORMY16_INSN_BPHMEMIMM, "bphmemimm", "bp", 32,
+ { 0|A(COND_CTI), { (1<<MACH_BASE) } }
+ },
+/* b$bcond2 ${rel8-2} */
+ {
+ XSTORMY16_INSN_BCC, "bcc", "b", 16,
+ { 0|A(COND_CTI), { (1<<MACH_BASE) } }
+ },
+/* br $Rd */
+ {
+ XSTORMY16_INSN_BGR, "bgr", "br", 16,
+ { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+ },
+/* br $rel12a */
+ {
+ XSTORMY16_INSN_BR, "br", "br", 16,
+ { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+ },
+/* jmp $Rbj,$Rd */
+ {
+ XSTORMY16_INSN_JMP, "jmp", "jmp", 16,
+ { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+ },
+/* jmpf $abs24 */
+ {
+ XSTORMY16_INSN_JMPF, "jmpf", "jmpf", 32,
+ { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+ },
+/* callr $Rd */
+ {
+ XSTORMY16_INSN_CALLRGR, "callrgr", "callr", 16,
+ { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+ },
+/* callr $rel12a */
+ {
+ XSTORMY16_INSN_CALLRIMM, "callrimm", "callr", 16,
+ { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+ },
+/* call $Rbj,$Rd */
+ {
+ XSTORMY16_INSN_CALLGR, "callgr", "call", 16,
+ { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+ },
+/* callf $abs24 */
+ {
+ XSTORMY16_INSN_CALLFIMM, "callfimm", "callf", 32,
+ { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+ },
+/* icallr $Rd */
+ {
+ XSTORMY16_INSN_ICALLRGR, "icallrgr", "icallr", 16,
+ { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+ },
+/* icall $Rbj,$Rd */
+ {
+ XSTORMY16_INSN_ICALLGR, "icallgr", "icall", 16,
+ { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+ },
+/* icallf $abs24 */
+ {
+ XSTORMY16_INSN_ICALLFIMM, "icallfimm", "icallf", 32,
+ { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+ },
+/* iret */
+ {
+ XSTORMY16_INSN_IRET, "iret", "iret", 16,
+ { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+ },
+/* ret */
+ {
+ XSTORMY16_INSN_RET, "ret", "ret", 16,
+ { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+ },
+/* mul */
+ {
+ XSTORMY16_INSN_MUL, "mul", "mul", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* div */
+ {
+ XSTORMY16_INSN_DIV, "div", "div", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* nop */
+ {
+ XSTORMY16_INSN_NOP, "nop", "nop", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* halt */
+ {
+ XSTORMY16_INSN_HALT, "halt", "halt", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* hold */
+ {
+ XSTORMY16_INSN_HOLD, "hold", "hold", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* brk */
+ {
+ XSTORMY16_INSN_BRK, "brk", "brk", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* --unused-- */
+ {
+ XSTORMY16_INSN_SYSCALL, "syscall", "--unused--", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+};
+
+#undef OP
+#undef A
+
+/* Initialize anything needed to be done once, before any cpu_open call. */
+static void init_tables PARAMS ((void));
+
+static void
+init_tables ()
+{
+}
+
+static const CGEN_MACH * lookup_mach_via_bfd_name
+ PARAMS ((const CGEN_MACH *, const char *));
+static void build_hw_table PARAMS ((CGEN_CPU_TABLE *));
+static void build_ifield_table PARAMS ((CGEN_CPU_TABLE *));
+static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
+static void build_insn_table PARAMS ((CGEN_CPU_TABLE *));
+static void xstormy16_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
+
+/* Subroutine of xstormy16_cgen_cpu_open to look up a mach via its bfd name. */
+
+static const CGEN_MACH *
+lookup_mach_via_bfd_name (table, name)
+ const CGEN_MACH *table;
+ const char *name;
+{
+ while (table->name)
+ {
+ if (strcmp (name, table->bfd_name) == 0)
+ return table;
+ ++table;
+ }
+ abort ();
+}
+
+/* Subroutine of xstormy16_cgen_cpu_open to build the hardware table. */
+
+static void
+build_hw_table (cd)
+ CGEN_CPU_TABLE *cd;
+{
+ int i;
+ int machs = cd->machs;
+ const CGEN_HW_ENTRY *init = & xstormy16_cgen_hw_table[0];
+ /* MAX_HW is only an upper bound on the number of selected entries.
+ However each entry is indexed by it's enum so there can be holes in
+ the table. */
+ const CGEN_HW_ENTRY **selected =
+ (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
+
+ cd->hw_table.init_entries = init;
+ cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
+ memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
+ /* ??? For now we just use machs to determine which ones we want. */
+ for (i = 0; init[i].name != NULL; ++i)
+ if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
+ & machs)
+ selected[init[i].type] = &init[i];
+ cd->hw_table.entries = selected;
+ cd->hw_table.num_entries = MAX_HW;
+}
+
+/* Subroutine of xstormy16_cgen_cpu_open to build the hardware table. */
+
+static void
+build_ifield_table (cd)
+ CGEN_CPU_TABLE *cd;
+{
+ cd->ifld_table = & xstormy16_cgen_ifld_table[0];
+}
+
+/* Subroutine of xstormy16_cgen_cpu_open to build the hardware table. */
+
+static void
+build_operand_table (cd)
+ CGEN_CPU_TABLE *cd;
+{
+ int i;
+ int machs = cd->machs;
+ const CGEN_OPERAND *init = & xstormy16_cgen_operand_table[0];
+ /* MAX_OPERANDS is only an upper bound on the number of selected entries.
+ However each entry is indexed by it's enum so there can be holes in
+ the table. */
+ const CGEN_OPERAND **selected =
+ (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
+
+ cd->operand_table.init_entries = init;
+ cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
+ memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
+ /* ??? For now we just use mach to determine which ones we want. */
+ for (i = 0; init[i].name != NULL; ++i)
+ if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
+ & machs)
+ selected[init[i].type] = &init[i];
+ cd->operand_table.entries = selected;
+ cd->operand_table.num_entries = MAX_OPERANDS;
+}
+
+/* Subroutine of xstormy16_cgen_cpu_open to build the hardware table.
+ ??? This could leave out insns not supported by the specified mach/isa,
+ but that would cause errors like "foo only supported by bar" to become
+ "unknown insn", so for now we include all insns and require the app to
+ do the checking later.
+ ??? On the other hand, parsing of such insns may require their hardware or
+ operand elements to be in the table [which they mightn't be]. */
+
+static void
+build_insn_table (cd)
+ CGEN_CPU_TABLE *cd;
+{
+ int i;
+ const CGEN_IBASE *ib = & xstormy16_cgen_insn_table[0];
+ CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
+
+ memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
+ for (i = 0; i < MAX_INSNS; ++i)
+ insns[i].base = &ib[i];
+ cd->insn_table.init_entries = insns;
+ cd->insn_table.entry_size = sizeof (CGEN_IBASE);
+ cd->insn_table.num_init_entries = MAX_INSNS;
+}
+
+/* Subroutine of xstormy16_cgen_cpu_open to rebuild the tables. */
+
+static void
+xstormy16_cgen_rebuild_tables (cd)
+ CGEN_CPU_TABLE *cd;
+{
+ int i;
+ unsigned int isas = cd->isas;
+ unsigned int machs = cd->machs;
+
+ cd->int_insn_p = CGEN_INT_INSN_P;
+
+ /* Data derived from the isa spec. */
+#define UNSET (CGEN_SIZE_UNKNOWN + 1)
+ cd->default_insn_bitsize = UNSET;
+ cd->base_insn_bitsize = UNSET;
+ cd->min_insn_bitsize = 65535; /* some ridiculously big number */
+ cd->max_insn_bitsize = 0;
+ for (i = 0; i < MAX_ISAS; ++i)
+ if (((1 << i) & isas) != 0)
+ {
+ const CGEN_ISA *isa = & xstormy16_cgen_isa_table[i];
+
+ /* Default insn sizes of all selected isas must be
+ equal or we set the result to 0, meaning "unknown". */
+ if (cd->default_insn_bitsize == UNSET)
+ cd->default_insn_bitsize = isa->default_insn_bitsize;
+ else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
+ ; /* this is ok */
+ else
+ cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
+
+ /* Base insn sizes of all selected isas must be equal
+ or we set the result to 0, meaning "unknown". */
+ if (cd->base_insn_bitsize == UNSET)
+ cd->base_insn_bitsize = isa->base_insn_bitsize;
+ else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
+ ; /* this is ok */
+ else
+ cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
+
+ /* Set min,max insn sizes. */
+ if (isa->min_insn_bitsize < cd->min_insn_bitsize)
+ cd->min_insn_bitsize = isa->min_insn_bitsize;
+ if (isa->max_insn_bitsize > cd->max_insn_bitsize)
+ cd->max_insn_bitsize = isa->max_insn_bitsize;
+ }
+
+ /* Data derived from the mach spec. */
+ for (i = 0; i < MAX_MACHS; ++i)
+ if (((1 << i) & machs) != 0)
+ {
+ const CGEN_MACH *mach = & xstormy16_cgen_mach_table[i];
+
+ if (mach->insn_chunk_bitsize != 0)
+ {
+ if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
+ {
+ fprintf (stderr, "xstormy16_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
+ cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
+ abort ();
+ }
+
+ cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
+ }
+ }
+
+ /* Determine which hw elements are used by MACH. */
+ build_hw_table (cd);
+
+ /* Build the ifield table. */
+ build_ifield_table (cd);
+
+ /* Determine which operands are used by MACH/ISA. */
+ build_operand_table (cd);
+
+ /* Build the instruction table. */
+ build_insn_table (cd);
+}
+
+/* Initialize a cpu table and return a descriptor.
+ It's much like opening a file, and must be the first function called.
+ The arguments are a set of (type/value) pairs, terminated with
+ CGEN_CPU_OPEN_END.
+
+ Currently supported values:
+ CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr
+ CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr
+ CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
+ CGEN_CPU_OPEN_ENDIAN: specify endian choice
+ CGEN_CPU_OPEN_END: terminates arguments
+
+ ??? Simultaneous multiple isas might not make sense, but it's not (yet)
+ precluded.
+
+ ??? We only support ISO C stdargs here, not K&R.
+ Laziness, plus experiment to see if anything requires K&R - eventually
+ K&R will no longer be supported - e.g. GDB is currently trying this. */
+
+CGEN_CPU_DESC
+xstormy16_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
+{
+ CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
+ static int init_p;
+ unsigned int isas = 0; /* 0 = "unspecified" */
+ unsigned int machs = 0; /* 0 = "unspecified" */
+ enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
+ va_list ap;
+
+ if (! init_p)
+ {
+ init_tables ();
+ init_p = 1;
+ }
+
+ memset (cd, 0, sizeof (*cd));
+
+ va_start (ap, arg_type);
+ while (arg_type != CGEN_CPU_OPEN_END)
+ {
+ switch (arg_type)
+ {
+ case CGEN_CPU_OPEN_ISAS :
+ isas = va_arg (ap, unsigned int);
+ break;
+ case CGEN_CPU_OPEN_MACHS :
+ machs = va_arg (ap, unsigned int);
+ break;
+ case CGEN_CPU_OPEN_BFDMACH :
+ {
+ const char *name = va_arg (ap, const char *);
+ const CGEN_MACH *mach =
+ lookup_mach_via_bfd_name (xstormy16_cgen_mach_table, name);
+
+ machs |= 1 << mach->num;
+ break;
+ }
+ case CGEN_CPU_OPEN_ENDIAN :
+ endian = va_arg (ap, enum cgen_endian);
+ break;
+ default :
+ fprintf (stderr, "xstormy16_cgen_cpu_open: unsupported argument `%d'\n",
+ arg_type);
+ abort (); /* ??? return NULL? */
+ }
+ arg_type = va_arg (ap, enum cgen_cpu_open_arg);
+ }
+ va_end (ap);
+
+ /* mach unspecified means "all" */
+ if (machs == 0)
+ machs = (1 << MAX_MACHS) - 1;
+ /* base mach is always selected */
+ machs |= 1;
+ /* isa unspecified means "all" */
+ if (isas == 0)
+ isas = (1 << MAX_ISAS) - 1;
+ if (endian == CGEN_ENDIAN_UNKNOWN)
+ {
+ /* ??? If target has only one, could have a default. */
+ fprintf (stderr, "xstormy16_cgen_cpu_open: no endianness specified\n");
+ abort ();
+ }
+
+ cd->isas = isas;
+ cd->machs = machs;
+ cd->endian = endian;
+ /* FIXME: for the sparc case we can determine insn-endianness statically.
+ The worry here is where both data and insn endian can be independently
+ chosen, in which case this function will need another argument.
+ Actually, will want to allow for more arguments in the future anyway. */
+ cd->insn_endian = endian;
+
+ /* Table (re)builder. */
+ cd->rebuild_tables = xstormy16_cgen_rebuild_tables;
+ xstormy16_cgen_rebuild_tables (cd);
+
+ /* Default to not allowing signed overflow. */
+ cd->signed_overflow_ok_p = 0;
+
+ return (CGEN_CPU_DESC) cd;
+}
+
+/* Cover fn to xstormy16_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
+ MACH_NAME is the bfd name of the mach. */
+
+CGEN_CPU_DESC
+xstormy16_cgen_cpu_open_1 (mach_name, endian)
+ const char *mach_name;
+ enum cgen_endian endian;
+{
+ return xstormy16_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
+ CGEN_CPU_OPEN_ENDIAN, endian,
+ CGEN_CPU_OPEN_END);
+}
+
+/* Close a cpu table.
+ ??? This can live in a machine independent file, but there's currently
+ no place to put this file (there's no libcgen). libopcodes is the wrong
+ place as some simulator ports use this but they don't use libopcodes. */
+
+void
+xstormy16_cgen_cpu_close (cd)
+ CGEN_CPU_DESC cd;
+{
+ if (cd->insn_table.init_entries)
+ free ((CGEN_INSN *) cd->insn_table.init_entries);
+ if (cd->hw_table.entries)
+ free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
+ free (cd);
+}
+
diff --git a/opcodes/xstormy16-desc.h b/opcodes/xstormy16-desc.h
new file mode 100644
index 0000000..c00ca79
--- /dev/null
+++ b/opcodes/xstormy16-desc.h
@@ -0,0 +1,289 @@
+/* CPU data header for xstormy16.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifndef XSTORMY16_CPU_H
+#define XSTORMY16_CPU_H
+
+#define CGEN_ARCH xstormy16
+
+/* Given symbol S, return xstormy16_cgen_<S>. */
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define CGEN_SYM(s) xstormy16##_cgen_##s
+#else
+#define CGEN_SYM(s) xstormy16/**/_cgen_/**/s
+#endif
+
+
+/* Selected cpu families. */
+#define HAVE_CPU_XSTORMY16
+
+#define CGEN_INSN_LSB0_P 0
+
+/* Minimum size of any insn (in bytes). */
+#define CGEN_MIN_INSN_SIZE 2
+
+/* Maximum size of any insn (in bytes). */
+#define CGEN_MAX_INSN_SIZE 4
+
+#define CGEN_INT_INSN_P 1
+
+/* Maximum number of syntax elements in an instruction. */
+#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 19
+
+/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
+ e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands
+ we can't hash on everything up to the space. */
+#define CGEN_MNEMONIC_OPERANDS
+
+/* Maximum number of fields in an instruction. */
+#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 9
+
+/* Enums. */
+
+/* Enum declaration for . */
+typedef enum gr_names {
+ H_GR_R0 = 0, H_GR_R1 = 1, H_GR_R2 = 2, H_GR_R3 = 3
+ , H_GR_R4 = 4, H_GR_R5 = 5, H_GR_R6 = 6, H_GR_R7 = 7
+ , H_GR_R8 = 8, H_GR_R9 = 9, H_GR_R10 = 10, H_GR_R11 = 11
+ , H_GR_R12 = 12, H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15
+ , H_GR_PSW = 14, H_GR_SP = 15
+} GR_NAMES;
+
+/* Enum declaration for . */
+typedef enum gr_rbj_names {
+ H_RBJ_R8, H_RBJ_R9
+} GR_RBJ_NAMES;
+
+/* Enum declaration for insn op enums. */
+typedef enum insn_op1 {
+ OP1_0, OP1_1, OP1_2, OP1_3
+ , OP1_4, OP1_5, OP1_6, OP1_7
+ , OP1_8, OP1_9, OP1_A, OP1_B
+ , OP1_C, OP1_D, OP1_E, OP1_F
+} INSN_OP1;
+
+/* Enum declaration for insn op enums. */
+typedef enum insn_op2 {
+ OP2_0, OP2_1, OP2_2, OP2_3
+ , OP2_4, OP2_5, OP2_6, OP2_7
+ , OP2_8, OP2_9, OP2_A, OP2_B
+ , OP2_C, OP2_D, OP2_E, OP2_F
+} INSN_OP2;
+
+/* Enum declaration for insn op enums. */
+typedef enum insn_op2a {
+ OP2A_0, OP2A_2, OP2A_4, OP2A_6
+ , OP2A_8, OP2A_A, OP2A_C, OP2A_E
+} INSN_OP2A;
+
+/* Enum declaration for insn op enums. */
+typedef enum insn_op2m {
+ OP2M_0, OP2M_1
+} INSN_OP2M;
+
+/* Enum declaration for insn op enums. */
+typedef enum insn_op3 {
+ OP3_0, OP3_1, OP3_2, OP3_3
+ , OP3_4, OP3_5, OP3_6, OP3_7
+ , OP3_8, OP3_9, OP3_A, OP3_B
+ , OP3_C, OP3_D, OP3_E, OP3_F
+} INSN_OP3;
+
+/* Enum declaration for insn op enums. */
+typedef enum insn_op3a {
+ OP3A_0, OP3A_1, OP3A_2, OP3A_3
+} INSN_OP3A;
+
+/* Enum declaration for insn op enums. */
+typedef enum insn_op3b {
+ OP3B_0, OP3B_2, OP3B_4, OP3B_6
+ , OP3B_8, OP3B_A, OP3B_C, OP3B_E
+} INSN_OP3B;
+
+/* Enum declaration for insn op enums. */
+typedef enum insn_op4 {
+ OP4_0, OP4_1, OP4_2, OP4_3
+ , OP4_4, OP4_5, OP4_6, OP4_7
+ , OP4_8, OP4_9, OP4_A, OP4_B
+ , OP4_C, OP4_D, OP4_E, OP4_F
+} INSN_OP4;
+
+/* Enum declaration for insn op enums. */
+typedef enum insn_op4m {
+ OP4M_0, OP4M_1
+} INSN_OP4M;
+
+/* Enum declaration for insn op enums. */
+typedef enum insn_op4b {
+ OP4B_0, OP4B_1
+} INSN_OP4B;
+
+/* Enum declaration for insn op enums. */
+typedef enum insn_op5 {
+ OP5_0, OP5_1, OP5_2, OP5_3
+ , OP5_4, OP5_5, OP5_6, OP5_7
+ , OP5_8, OP5_9, OP5_A, OP5_B
+ , OP5_C, OP5_D, OP5_E, OP5_F
+} INSN_OP5;
+
+/* Enum declaration for insn op enums. */
+typedef enum insn_op5a {
+ OP5A_0, OP5A_1
+} INSN_OP5A;
+
+/* Attributes. */
+
+/* Enum declaration for machine type selection. */
+typedef enum mach_attr {
+ MACH_BASE, MACH_XSTORMY16, MACH_MAX
+} MACH_ATTR;
+
+/* Enum declaration for instruction set selection. */
+typedef enum isa_attr {
+ ISA_XSTORMY16, ISA_MAX
+} ISA_ATTR;
+
+/* Number of architecture variants. */
+#define MAX_ISAS 1
+#define MAX_MACHS ((int) MACH_MAX)
+
+/* Ifield support. */
+
+extern const struct cgen_ifld xstormy16_cgen_ifld_table[];
+
+/* Ifield attribute indices. */
+
+/* Enum declaration for cgen_ifld attrs. */
+typedef enum cgen_ifld_attr {
+ CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
+ , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
+ , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
+} CGEN_IFLD_ATTR;
+
+/* Number of non-boolean elements in cgen_ifld_attr. */
+#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
+
+/* Enum declaration for xstormy16 ifield types. */
+typedef enum ifield_type {
+ XSTORMY16_F_NIL, XSTORMY16_F_ANYOF, XSTORMY16_F_RD, XSTORMY16_F_RDM
+ , XSTORMY16_F_RM, XSTORMY16_F_RS, XSTORMY16_F_RB, XSTORMY16_F_RBJ
+ , XSTORMY16_F_OP1, XSTORMY16_F_OP2, XSTORMY16_F_OP2A, XSTORMY16_F_OP2M
+ , XSTORMY16_F_OP3, XSTORMY16_F_OP3A, XSTORMY16_F_OP3B, XSTORMY16_F_OP4
+ , XSTORMY16_F_OP4M, XSTORMY16_F_OP4B, XSTORMY16_F_OP5, XSTORMY16_F_OP5A
+ , XSTORMY16_F_OP, XSTORMY16_F_IMM2, XSTORMY16_F_IMM3, XSTORMY16_F_IMM3B
+ , XSTORMY16_F_IMM4, XSTORMY16_F_IMM8, XSTORMY16_F_IMM12, XSTORMY16_F_IMM16
+ , XSTORMY16_F_LMEM8, XSTORMY16_F_HMEM8, XSTORMY16_F_REL8_2, XSTORMY16_F_REL8_4
+ , XSTORMY16_F_REL12, XSTORMY16_F_REL12A, XSTORMY16_F_ABS24_1, XSTORMY16_F_ABS24_2
+ , XSTORMY16_F_ABS24, XSTORMY16_F_MAX
+} IFIELD_TYPE;
+
+#define MAX_IFLD ((int) XSTORMY16_F_MAX)
+
+/* Hardware attribute indices. */
+
+/* Enum declaration for cgen_hw attrs. */
+typedef enum cgen_hw_attr {
+ CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
+ , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
+} CGEN_HW_ATTR;
+
+/* Number of non-boolean elements in cgen_hw_attr. */
+#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
+
+/* Enum declaration for xstormy16 hardware types. */
+typedef enum cgen_hw_type {
+ HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
+ , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_RBJ
+ , HW_H_RPSW, HW_H_Z8, HW_H_Z16, HW_H_CY
+ , HW_H_HC, HW_H_OV, HW_H_PT, HW_H_S
+ , HW_H_BRANCHCOND, HW_H_WORDSIZE, HW_MAX
+} CGEN_HW_TYPE;
+
+#define MAX_HW ((int) HW_MAX)
+
+/* Operand attribute indices. */
+
+/* Enum declaration for cgen_operand attrs. */
+typedef enum cgen_operand_attr {
+ CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
+ , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
+ , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS
+} CGEN_OPERAND_ATTR;
+
+/* Number of non-boolean elements in cgen_operand_attr. */
+#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
+
+/* Enum declaration for xstormy16 operand types. */
+typedef enum cgen_operand_type {
+ XSTORMY16_OPERAND_PC, XSTORMY16_OPERAND_PSW_Z8, XSTORMY16_OPERAND_PSW_Z16, XSTORMY16_OPERAND_PSW_CY
+ , XSTORMY16_OPERAND_PSW_HC, XSTORMY16_OPERAND_PSW_OV, XSTORMY16_OPERAND_PSW_PT, XSTORMY16_OPERAND_PSW_S
+ , XSTORMY16_OPERAND_RD, XSTORMY16_OPERAND_RDM, XSTORMY16_OPERAND_RM, XSTORMY16_OPERAND_RS
+ , XSTORMY16_OPERAND_RB, XSTORMY16_OPERAND_RBJ, XSTORMY16_OPERAND_BCOND2, XSTORMY16_OPERAND_WS2
+ , XSTORMY16_OPERAND_BCOND5, XSTORMY16_OPERAND_IMM2, XSTORMY16_OPERAND_IMM3, XSTORMY16_OPERAND_IMM3B
+ , XSTORMY16_OPERAND_IMM4, XSTORMY16_OPERAND_IMM8, XSTORMY16_OPERAND_IMM8SMALL, XSTORMY16_OPERAND_IMM12
+ , XSTORMY16_OPERAND_IMM16, XSTORMY16_OPERAND_LMEM8, XSTORMY16_OPERAND_HMEM8, XSTORMY16_OPERAND_REL8_2
+ , XSTORMY16_OPERAND_REL8_4, XSTORMY16_OPERAND_REL12, XSTORMY16_OPERAND_REL12A, XSTORMY16_OPERAND_ABS24
+ , XSTORMY16_OPERAND_PSW, XSTORMY16_OPERAND_RPSW, XSTORMY16_OPERAND_SP, XSTORMY16_OPERAND_R0
+ , XSTORMY16_OPERAND_R1, XSTORMY16_OPERAND_R2, XSTORMY16_OPERAND_R8, XSTORMY16_OPERAND_MAX
+} CGEN_OPERAND_TYPE;
+
+/* Number of operands types. */
+#define MAX_OPERANDS 39
+
+/* Maximum number of operands referenced by any insn. */
+#define MAX_OPERAND_INSTANCES 8
+
+/* Insn attribute indices. */
+
+/* Enum declaration for cgen_insn attrs. */
+typedef enum cgen_insn_attr {
+ CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
+ , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX
+ , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31
+ , CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS
+} CGEN_INSN_ATTR;
+
+/* Number of non-boolean elements in cgen_insn_attr. */
+#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
+
+/* cgen.h uses things we just defined. */
+#include "opcode/cgen.h"
+
+/* Attributes. */
+extern const CGEN_ATTR_TABLE xstormy16_cgen_hardware_attr_table[];
+extern const CGEN_ATTR_TABLE xstormy16_cgen_ifield_attr_table[];
+extern const CGEN_ATTR_TABLE xstormy16_cgen_operand_attr_table[];
+extern const CGEN_ATTR_TABLE xstormy16_cgen_insn_attr_table[];
+
+/* Hardware decls. */
+
+extern CGEN_KEYWORD xstormy16_cgen_opval_gr_names;
+extern CGEN_KEYWORD xstormy16_cgen_opval_gr_Rbj_names;
+extern CGEN_KEYWORD xstormy16_cgen_opval_h_branchcond;
+extern CGEN_KEYWORD xstormy16_cgen_opval_h_wordsize;
+
+
+
+
+#endif /* XSTORMY16_CPU_H */
diff --git a/opcodes/xstormy16-dis.c b/opcodes/xstormy16-dis.c
new file mode 100644
index 0000000..595ed2a
--- /dev/null
+++ b/opcodes/xstormy16-dis.c
@@ -0,0 +1,565 @@
+/* Disassembler interface for targets using CGEN. -*- C -*-
+ CGEN: Cpu tools GENerator
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+- the resultant file is machine generated, cgen-dis.in isn't
+
+Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+/* ??? Eventually more and more of this stuff can go to cpu-independent files.
+ Keep that in mind. */
+
+#include "sysdep.h"
+#include <stdio.h>
+#include "ansidecl.h"
+#include "dis-asm.h"
+#include "bfd.h"
+#include "symcat.h"
+#include "xstormy16-desc.h"
+#include "xstormy16-opc.h"
+#include "opintl.h"
+
+/* Default text to print if an instruction isn't recognized. */
+#define UNKNOWN_INSN_MSG _("*unknown*")
+
+static void print_normal
+ PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int));
+static void print_address
+ PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int));
+static void print_keyword
+ PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int));
+static void print_insn_normal
+ PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *,
+ bfd_vma, int));
+static int print_insn
+ PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, unsigned));
+static int default_print_insn
+ PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
+static int read_insn
+ PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int,
+ CGEN_EXTRACT_INFO *, unsigned long *));
+
+/* -- disassembler routines inserted here */
+
+
+void xstormy16_cgen_print_operand
+ PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *,
+ void const *, bfd_vma, int));
+
+/* Main entry point for printing operands.
+ XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
+ of dis-asm.h on cgen.h.
+
+ This function is basically just a big switch statement. Earlier versions
+ used tables to look up the function to use, but
+ - if the table contains both assembler and disassembler functions then
+ the disassembler contains much of the assembler and vice-versa,
+ - there's a lot of inlining possibilities as things grow,
+ - using a switch statement avoids the function call overhead.
+
+ This function could be moved into `print_insn_normal', but keeping it
+ separate makes clear the interface between `print_insn_normal' and each of
+ the handlers. */
+
+void
+xstormy16_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
+ CGEN_CPU_DESC cd;
+ int opindex;
+ PTR xinfo;
+ CGEN_FIELDS *fields;
+ void const *attrs ATTRIBUTE_UNUSED;
+ bfd_vma pc;
+ int length;
+{
+ disassemble_info *info = (disassemble_info *) xinfo;
+
+ switch (opindex)
+ {
+ case XSTORMY16_OPERAND_RB :
+ print_keyword (cd, info, & xstormy16_cgen_opval_gr_names, fields->f_Rb, 0);
+ break;
+ case XSTORMY16_OPERAND_RBJ :
+ print_keyword (cd, info, & xstormy16_cgen_opval_gr_Rbj_names, fields->f_Rbj, 0);
+ break;
+ case XSTORMY16_OPERAND_RD :
+ print_keyword (cd, info, & xstormy16_cgen_opval_gr_names, fields->f_Rd, 0);
+ break;
+ case XSTORMY16_OPERAND_RDM :
+ print_keyword (cd, info, & xstormy16_cgen_opval_gr_names, fields->f_Rdm, 0);
+ break;
+ case XSTORMY16_OPERAND_RM :
+ print_keyword (cd, info, & xstormy16_cgen_opval_gr_names, fields->f_Rm, 0);
+ break;
+ case XSTORMY16_OPERAND_RS :
+ print_keyword (cd, info, & xstormy16_cgen_opval_gr_names, fields->f_Rs, 0);
+ break;
+ case XSTORMY16_OPERAND_ABS24 :
+ print_normal (cd, info, fields->f_abs24, 0|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
+ break;
+ case XSTORMY16_OPERAND_BCOND2 :
+ print_keyword (cd, info, & xstormy16_cgen_opval_h_branchcond, fields->f_op2, 0);
+ break;
+ case XSTORMY16_OPERAND_BCOND5 :
+ print_keyword (cd, info, & xstormy16_cgen_opval_h_branchcond, fields->f_op5, 0);
+ break;
+ case XSTORMY16_OPERAND_HMEM8 :
+ print_normal (cd, info, fields->f_hmem8, 0|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
+ break;
+ case XSTORMY16_OPERAND_IMM12 :
+ print_normal (cd, info, fields->f_imm12, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
+ break;
+ case XSTORMY16_OPERAND_IMM16 :
+ print_normal (cd, info, fields->f_imm16, 0|(1<<CGEN_OPERAND_SIGN_OPT), pc, length);
+ break;
+ case XSTORMY16_OPERAND_IMM2 :
+ print_normal (cd, info, fields->f_imm2, 0, pc, length);
+ break;
+ case XSTORMY16_OPERAND_IMM3 :
+ print_normal (cd, info, fields->f_imm3, 0, pc, length);
+ break;
+ case XSTORMY16_OPERAND_IMM3B :
+ print_normal (cd, info, fields->f_imm3b, 0, pc, length);
+ break;
+ case XSTORMY16_OPERAND_IMM4 :
+ print_normal (cd, info, fields->f_imm4, 0, pc, length);
+ break;
+ case XSTORMY16_OPERAND_IMM8 :
+ print_normal (cd, info, fields->f_imm8, 0, pc, length);
+ break;
+ case XSTORMY16_OPERAND_IMM8SMALL :
+ print_normal (cd, info, fields->f_imm8, 0, pc, length);
+ break;
+ case XSTORMY16_OPERAND_LMEM8 :
+ print_normal (cd, info, fields->f_lmem8, 0|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
+ break;
+ case XSTORMY16_OPERAND_REL12 :
+ print_normal (cd, info, fields->f_rel12, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
+ break;
+ case XSTORMY16_OPERAND_REL12A :
+ print_normal (cd, info, fields->f_rel12a, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
+ break;
+ case XSTORMY16_OPERAND_REL8_2 :
+ print_normal (cd, info, fields->f_rel8_2, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
+ break;
+ case XSTORMY16_OPERAND_REL8_4 :
+ print_normal (cd, info, fields->f_rel8_4, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
+ break;
+ case XSTORMY16_OPERAND_WS2 :
+ print_keyword (cd, info, & xstormy16_cgen_opval_h_wordsize, fields->f_op2m, 0);
+ break;
+
+ default :
+ /* xgettext:c-format */
+ fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
+ opindex);
+ abort ();
+ }
+}
+
+cgen_print_fn * const xstormy16_cgen_print_handlers[] =
+{
+ print_insn_normal,
+};
+
+
+void
+xstormy16_cgen_init_dis (cd)
+ CGEN_CPU_DESC cd;
+{
+ xstormy16_cgen_init_opcode_table (cd);
+ xstormy16_cgen_init_ibld_table (cd);
+ cd->print_handlers = & xstormy16_cgen_print_handlers[0];
+ cd->print_operand = xstormy16_cgen_print_operand;
+}
+
+
+/* Default print handler. */
+
+static void
+print_normal (cd, dis_info, value, attrs, pc, length)
+ CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
+ PTR dis_info;
+ long value;
+ unsigned int attrs;
+ bfd_vma pc ATTRIBUTE_UNUSED;
+ int length ATTRIBUTE_UNUSED;
+{
+ disassemble_info *info = (disassemble_info *) dis_info;
+
+#ifdef CGEN_PRINT_NORMAL
+ CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length);
+#endif
+
+ /* Print the operand as directed by the attributes. */
+ if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
+ ; /* nothing to do */
+ else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
+ (*info->fprintf_func) (info->stream, "%ld", value);
+ else
+ (*info->fprintf_func) (info->stream, "0x%lx", value);
+}
+
+/* Default address handler. */
+
+static void
+print_address (cd, dis_info, value, attrs, pc, length)
+ CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
+ PTR dis_info;
+ bfd_vma value;
+ unsigned int attrs;
+ bfd_vma pc ATTRIBUTE_UNUSED;
+ int length ATTRIBUTE_UNUSED;
+{
+ disassemble_info *info = (disassemble_info *) dis_info;
+
+#ifdef CGEN_PRINT_ADDRESS
+ CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length);
+#endif
+
+ /* Print the operand as directed by the attributes. */
+ if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
+ ; /* nothing to do */
+ else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
+ (*info->print_address_func) (value, info);
+ else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
+ (*info->print_address_func) (value, info);
+ else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
+ (*info->fprintf_func) (info->stream, "%ld", (long) value);
+ else
+ (*info->fprintf_func) (info->stream, "0x%lx", (long) value);
+}
+
+/* Keyword print handler. */
+
+static void
+print_keyword (cd, dis_info, keyword_table, value, attrs)
+ CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
+ PTR dis_info;
+ CGEN_KEYWORD *keyword_table;
+ long value;
+ unsigned int attrs ATTRIBUTE_UNUSED;
+{
+ disassemble_info *info = (disassemble_info *) dis_info;
+ const CGEN_KEYWORD_ENTRY *ke;
+
+ ke = cgen_keyword_lookup_value (keyword_table, value);
+ if (ke != NULL)
+ (*info->fprintf_func) (info->stream, "%s", ke->name);
+ else
+ (*info->fprintf_func) (info->stream, "???");
+}
+
+/* Default insn printer.
+
+ DIS_INFO is defined as `PTR' so the disassembler needn't know anything
+ about disassemble_info. */
+
+static void
+print_insn_normal (cd, dis_info, insn, fields, pc, length)
+ CGEN_CPU_DESC cd;
+ PTR dis_info;
+ const CGEN_INSN *insn;
+ CGEN_FIELDS *fields;
+ bfd_vma pc;
+ int length;
+{
+ const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
+ disassemble_info *info = (disassemble_info *) dis_info;
+ const CGEN_SYNTAX_CHAR_TYPE *syn;
+
+ CGEN_INIT_PRINT (cd);
+
+ for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
+ {
+ if (CGEN_SYNTAX_MNEMONIC_P (*syn))
+ {
+ (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
+ continue;
+ }
+ if (CGEN_SYNTAX_CHAR_P (*syn))
+ {
+ (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
+ continue;
+ }
+
+ /* We have an operand. */
+ xstormy16_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
+ fields, CGEN_INSN_ATTRS (insn), pc, length);
+ }
+}
+
+/* Subroutine of print_insn. Reads an insn into the given buffers and updates
+ the extract info.
+ Returns 0 if all is well, non-zero otherwise. */
+
+static int
+read_insn (cd, pc, info, buf, buflen, ex_info, insn_value)
+ CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
+ bfd_vma pc;
+ disassemble_info *info;
+ char *buf;
+ int buflen;
+ CGEN_EXTRACT_INFO *ex_info;
+ unsigned long *insn_value;
+{
+ int status = (*info->read_memory_func) (pc, buf, buflen, info);
+ if (status != 0)
+ {
+ (*info->memory_error_func) (status, pc, info);
+ return -1;
+ }
+
+ ex_info->dis_info = info;
+ ex_info->valid = (1 << buflen) - 1;
+ ex_info->insn_bytes = buf;
+
+ *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG);
+ return 0;
+}
+
+/* Utility to print an insn.
+ BUF is the base part of the insn, target byte order, BUFLEN bytes long.
+ The result is the size of the insn in bytes or zero for an unknown insn
+ or -1 if an error occurs fetching data (memory_error_func will have
+ been called). */
+
+static int
+print_insn (cd, pc, info, buf, buflen)
+ CGEN_CPU_DESC cd;
+ bfd_vma pc;
+ disassemble_info *info;
+ char *buf;
+ unsigned int buflen;
+{
+ CGEN_INSN_INT insn_value;
+ const CGEN_INSN_LIST *insn_list;
+ CGEN_EXTRACT_INFO ex_info;
+
+ /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
+ insn_value = cgen_get_insn_value (cd, buf, buflen * 8);
+
+ /* Fill in ex_info fields like read_insn would. Don't actually call
+ read_insn, since the incoming buffer is already read (and possibly
+ modified a la m32r). */
+ ex_info.valid = (1 << buflen) - 1;
+ ex_info.dis_info = info;
+ ex_info.insn_bytes = buf;
+
+ /* The instructions are stored in hash lists.
+ Pick the first one and keep trying until we find the right one. */
+
+ insn_list = CGEN_DIS_LOOKUP_INSN (cd, buf, insn_value);
+ while (insn_list != NULL)
+ {
+ const CGEN_INSN *insn = insn_list->insn;
+ CGEN_FIELDS fields;
+ int length;
+ unsigned long insn_value_cropped;
+
+#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+ /* Not needed as insn shouldn't be in hash lists if not supported. */
+ /* Supported by this cpu? */
+ if (! xstormy16_cgen_insn_supported (cd, insn))
+ {
+ insn_list = CGEN_DIS_NEXT_INSN (insn_list);
+ continue;
+ }
+#endif
+
+ /* Basic bit mask must be correct. */
+ /* ??? May wish to allow target to defer this check until the extract
+ handler. */
+
+ /* Base size may exceed this instruction's size. Extract the
+ relevant part from the buffer. */
+ if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
+ (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
+ insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
+ info->endian == BFD_ENDIAN_BIG);
+ else
+ insn_value_cropped = insn_value;
+
+ if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
+ == CGEN_INSN_BASE_VALUE (insn))
+ {
+ /* Printing is handled in two passes. The first pass parses the
+ machine insn and extracts the fields. The second pass prints
+ them. */
+
+ /* Make sure the entire insn is loaded into insn_value, if it
+ can fit. */
+ if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
+ (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
+ {
+ unsigned long full_insn_value;
+ int rc = read_insn (cd, pc, info, buf,
+ CGEN_INSN_BITSIZE (insn) / 8,
+ & ex_info, & full_insn_value);
+ if (rc != 0)
+ return rc;
+ length = CGEN_EXTRACT_FN (cd, insn)
+ (cd, insn, &ex_info, full_insn_value, &fields, pc);
+ }
+ else
+ length = CGEN_EXTRACT_FN (cd, insn)
+ (cd, insn, &ex_info, insn_value_cropped, &fields, pc);
+
+ /* length < 0 -> error */
+ if (length < 0)
+ return length;
+ if (length > 0)
+ {
+ CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
+ /* length is in bits, result is in bytes */
+ return length / 8;
+ }
+ }
+
+ insn_list = CGEN_DIS_NEXT_INSN (insn_list);
+ }
+
+ return 0;
+}
+
+/* Default value for CGEN_PRINT_INSN.
+ The result is the size of the insn in bytes or zero for an unknown insn
+ or -1 if an error occured fetching bytes. */
+
+#ifndef CGEN_PRINT_INSN
+#define CGEN_PRINT_INSN default_print_insn
+#endif
+
+static int
+default_print_insn (cd, pc, info)
+ CGEN_CPU_DESC cd;
+ bfd_vma pc;
+ disassemble_info *info;
+{
+ char buf[CGEN_MAX_INSN_SIZE];
+ int buflen;
+ int status;
+
+ /* Attempt to read the base part of the insn. */
+ buflen = cd->base_insn_bitsize / 8;
+ status = (*info->read_memory_func) (pc, buf, buflen, info);
+
+ /* Try again with the minimum part, if min < base. */
+ if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
+ {
+ buflen = cd->min_insn_bitsize / 8;
+ status = (*info->read_memory_func) (pc, buf, buflen, info);
+ }
+
+ if (status != 0)
+ {
+ (*info->memory_error_func) (status, pc, info);
+ return -1;
+ }
+
+ return print_insn (cd, pc, info, buf, buflen);
+}
+
+/* Main entry point.
+ Print one instruction from PC on INFO->STREAM.
+ Return the size of the instruction (in bytes). */
+
+int
+print_insn_xstormy16 (pc, info)
+ bfd_vma pc;
+ disassemble_info *info;
+{
+ static CGEN_CPU_DESC cd = 0;
+ static int prev_isa;
+ static int prev_mach;
+ static int prev_endian;
+ int length;
+ int isa,mach;
+ int endian = (info->endian == BFD_ENDIAN_BIG
+ ? CGEN_ENDIAN_BIG
+ : CGEN_ENDIAN_LITTLE);
+ enum bfd_architecture arch;
+
+ /* ??? gdb will set mach but leave the architecture as "unknown" */
+#ifndef CGEN_BFD_ARCH
+#define CGEN_BFD_ARCH bfd_arch_xstormy16
+#endif
+ arch = info->arch;
+ if (arch == bfd_arch_unknown)
+ arch = CGEN_BFD_ARCH;
+
+ /* There's no standard way to compute the machine or isa number
+ so we leave it to the target. */
+#ifdef CGEN_COMPUTE_MACH
+ mach = CGEN_COMPUTE_MACH (info);
+#else
+ mach = info->mach;
+#endif
+
+#ifdef CGEN_COMPUTE_ISA
+ isa = CGEN_COMPUTE_ISA (info);
+#else
+ isa = 0;
+#endif
+
+ /* If we've switched cpu's, close the current table and open a new one. */
+ if (cd
+ && (isa != prev_isa
+ || mach != prev_mach
+ || endian != prev_endian))
+ {
+ xstormy16_cgen_cpu_close (cd);
+ cd = 0;
+ }
+
+ /* If we haven't initialized yet, initialize the opcode table. */
+ if (! cd)
+ {
+ const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
+ const char *mach_name;
+
+ if (!arch_type)
+ abort ();
+ mach_name = arch_type->printable_name;
+
+ prev_isa = isa;
+ prev_mach = mach;
+ prev_endian = endian;
+ cd = xstormy16_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
+ CGEN_CPU_OPEN_BFDMACH, mach_name,
+ CGEN_CPU_OPEN_ENDIAN, prev_endian,
+ CGEN_CPU_OPEN_END);
+ if (!cd)
+ abort ();
+ xstormy16_cgen_init_dis (cd);
+ }
+
+ /* We try to have as much common code as possible.
+ But at this point some targets need to take over. */
+ /* ??? Some targets may need a hook elsewhere. Try to avoid this,
+ but if not possible try to move this hook elsewhere rather than
+ have two hooks. */
+ length = CGEN_PRINT_INSN (cd, pc, info);
+ if (length > 0)
+ return length;
+ if (length < 0)
+ return -1;
+
+ (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
+ return cd->default_insn_bitsize / 8;
+}
diff --git a/opcodes/xstormy16-ibld.c b/opcodes/xstormy16-ibld.c
new file mode 100644
index 0000000..2304514
--- /dev/null
+++ b/opcodes/xstormy16-ibld.c
@@ -0,0 +1,1246 @@
+/* Instruction building/extraction support for xstormy16. -*- C -*-
+
+THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
+- the resultant file is machine generated, cgen-ibld.in isn't
+
+Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+/* ??? Eventually more and more of this stuff can go to cpu-independent files.
+ Keep that in mind. */
+
+#include "sysdep.h"
+#include <stdio.h>
+#include "ansidecl.h"
+#include "dis-asm.h"
+#include "bfd.h"
+#include "symcat.h"
+#include "xstormy16-desc.h"
+#include "xstormy16-opc.h"
+#include "opintl.h"
+#include "safe-ctype.h"
+
+#undef min
+#define min(a,b) ((a) < (b) ? (a) : (b))
+#undef max
+#define max(a,b) ((a) > (b) ? (a) : (b))
+
+/* Used by the ifield rtx function. */
+#define FLD(f) (fields->f)
+
+static const char * insert_normal
+ PARAMS ((CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int,
+ unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR));
+static const char * insert_insn_normal
+ PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *,
+ CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma));
+static int extract_normal
+ PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
+ unsigned int, unsigned int, unsigned int, unsigned int,
+ unsigned int, unsigned int, bfd_vma, long *));
+static int extract_insn_normal
+ PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
+ CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma));
+#if CGEN_INT_INSN_P
+static void put_insn_int_value
+ PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT));
+#endif
+#if ! CGEN_INT_INSN_P
+static CGEN_INLINE void insert_1
+ PARAMS ((CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *));
+static CGEN_INLINE int fill_cache
+ PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma));
+static CGEN_INLINE long extract_1
+ PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int,
+ unsigned char *, bfd_vma));
+#endif
+
+/* Operand insertion. */
+
+#if ! CGEN_INT_INSN_P
+
+/* Subroutine of insert_normal. */
+
+static CGEN_INLINE void
+insert_1 (cd, value, start, length, word_length, bufp)
+ CGEN_CPU_DESC cd;
+ unsigned long value;
+ int start,length,word_length;
+ unsigned char *bufp;
+{
+ unsigned long x,mask;
+ int shift;
+
+ x = cgen_get_insn_value (cd, bufp, word_length);
+
+ /* Written this way to avoid undefined behaviour. */
+ mask = (((1L << (length - 1)) - 1) << 1) | 1;
+ if (CGEN_INSN_LSB0_P)
+ shift = (start + 1) - length;
+ else
+ shift = (word_length - (start + length));
+ x = (x & ~(mask << shift)) | ((value & mask) << shift);
+
+ cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x);
+}
+
+#endif /* ! CGEN_INT_INSN_P */
+
+/* Default insertion routine.
+
+ ATTRS is a mask of the boolean attributes.
+ WORD_OFFSET is the offset in bits from the start of the insn of the value.
+ WORD_LENGTH is the length of the word in bits in which the value resides.
+ START is the starting bit number in the word, architecture origin.
+ LENGTH is the length of VALUE in bits.
+ TOTAL_LENGTH is the total length of the insn in bits.
+
+ The result is an error message or NULL if success. */
+
+/* ??? This duplicates functionality with bfd's howto table and
+ bfd_install_relocation. */
+/* ??? This doesn't handle bfd_vma's. Create another function when
+ necessary. */
+
+static const char *
+insert_normal (cd, value, attrs, word_offset, start, length, word_length,
+ total_length, buffer)
+ CGEN_CPU_DESC cd;
+ long value;
+ unsigned int attrs;
+ unsigned int word_offset, start, length, word_length, total_length;
+ CGEN_INSN_BYTES_PTR buffer;
+{
+ static char errbuf[100];
+ /* Written this way to avoid undefined behaviour. */
+ unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1;
+
+ /* If LENGTH is zero, this operand doesn't contribute to the value. */
+ if (length == 0)
+ return NULL;
+
+#if 0
+ if (CGEN_INT_INSN_P
+ && word_offset != 0)
+ abort ();
+#endif
+
+ if (word_length > 32)
+ abort ();
+
+ /* For architectures with insns smaller than the base-insn-bitsize,
+ word_length may be too big. */
+ if (cd->min_insn_bitsize < cd->base_insn_bitsize)
+ {
+ if (word_offset == 0
+ && word_length > total_length)
+ word_length = total_length;
+ }
+
+ /* Ensure VALUE will fit. */
+ if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT))
+ {
+ long minval = - (1L << (length - 1));
+ unsigned long maxval = mask;
+
+ if ((value > 0 && (unsigned long) value > maxval)
+ || value < minval)
+ {
+ /* xgettext:c-format */
+ sprintf (errbuf,
+ _("operand out of range (%ld not between %ld and %lu)"),
+ value, minval, maxval);
+ return errbuf;
+ }
+ }
+ else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED))
+ {
+ unsigned long maxval = mask;
+
+ if ((unsigned long) value > maxval)
+ {
+ /* xgettext:c-format */
+ sprintf (errbuf,
+ _("operand out of range (%lu not between 0 and %lu)"),
+ value, maxval);
+ return errbuf;
+ }
+ }
+ else
+ {
+ if (! cgen_signed_overflow_ok_p (cd))
+ {
+ long minval = - (1L << (length - 1));
+ long maxval = (1L << (length - 1)) - 1;
+
+ if (value < minval || value > maxval)
+ {
+ sprintf
+ /* xgettext:c-format */
+ (errbuf, _("operand out of range (%ld not between %ld and %ld)"),
+ value, minval, maxval);
+ return errbuf;
+ }
+ }
+ }
+
+#if CGEN_INT_INSN_P
+
+ {
+ int shift;
+
+ if (CGEN_INSN_LSB0_P)
+ shift = (word_offset + start + 1) - length;
+ else
+ shift = total_length - (word_offset + start + length);
+ *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift);
+ }
+
+#else /* ! CGEN_INT_INSN_P */
+
+ {
+ unsigned char *bufp = (unsigned char *) buffer + word_offset / 8;
+
+ insert_1 (cd, value, start, length, word_length, bufp);
+ }
+
+#endif /* ! CGEN_INT_INSN_P */
+
+ return NULL;
+}
+
+/* Default insn builder (insert handler).
+ The instruction is recorded in CGEN_INT_INSN_P byte order (meaning
+ that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is
+ recorded in host byte order, otherwise BUFFER is an array of bytes
+ and the value is recorded in target byte order).
+ The result is an error message or NULL if success. */
+
+static const char *
+insert_insn_normal (cd, insn, fields, buffer, pc)
+ CGEN_CPU_DESC cd;
+ const CGEN_INSN * insn;
+ CGEN_FIELDS * fields;
+ CGEN_INSN_BYTES_PTR buffer;
+ bfd_vma pc;
+{
+ const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
+ unsigned long value;
+ const CGEN_SYNTAX_CHAR_TYPE * syn;
+
+ CGEN_INIT_INSERT (cd);
+ value = CGEN_INSN_BASE_VALUE (insn);
+
+ /* If we're recording insns as numbers (rather than a string of bytes),
+ target byte order handling is deferred until later. */
+
+#if CGEN_INT_INSN_P
+
+ put_insn_int_value (cd, buffer, cd->base_insn_bitsize,
+ CGEN_FIELDS_BITSIZE (fields), value);
+
+#else
+
+ cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize,
+ (unsigned) CGEN_FIELDS_BITSIZE (fields)),
+ value);
+
+#endif /* ! CGEN_INT_INSN_P */
+
+ /* ??? It would be better to scan the format's fields.
+ Still need to be able to insert a value based on the operand though;
+ e.g. storing a branch displacement that got resolved later.
+ Needs more thought first. */
+
+ for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn)
+ {
+ const char *errmsg;
+
+ if (CGEN_SYNTAX_CHAR_P (* syn))
+ continue;
+
+ errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
+ fields, buffer, pc);
+ if (errmsg)
+ return errmsg;
+ }
+
+ return NULL;
+}
+
+#if CGEN_INT_INSN_P
+/* Cover function to store an insn value into an integral insn. Must go here
+ because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */
+
+static void
+put_insn_int_value (cd, buf, length, insn_length, value)
+ CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
+ CGEN_INSN_BYTES_PTR buf;
+ int length;
+ int insn_length;
+ CGEN_INSN_INT value;
+{
+ /* For architectures with insns smaller than the base-insn-bitsize,
+ length may be too big. */
+ if (length > insn_length)
+ *buf = value;
+ else
+ {
+ int shift = insn_length - length;
+ /* Written this way to avoid undefined behaviour. */
+ CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
+ *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
+ }
+}
+#endif
+
+/* Operand extraction. */
+
+#if ! CGEN_INT_INSN_P
+
+/* Subroutine of extract_normal.
+ Ensure sufficient bytes are cached in EX_INFO.
+ OFFSET is the offset in bytes from the start of the insn of the value.
+ BYTES is the length of the needed value.
+ Returns 1 for success, 0 for failure. */
+
+static CGEN_INLINE int
+fill_cache (cd, ex_info, offset, bytes, pc)
+ CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
+ CGEN_EXTRACT_INFO *ex_info;
+ int offset, bytes;
+ bfd_vma pc;
+{
+ /* It's doubtful that the middle part has already been fetched so
+ we don't optimize that case. kiss. */
+ unsigned int mask;
+ disassemble_info *info = (disassemble_info *) ex_info->dis_info;
+
+ /* First do a quick check. */
+ mask = (1 << bytes) - 1;
+ if (((ex_info->valid >> offset) & mask) == mask)
+ return 1;
+
+ /* Search for the first byte we need to read. */
+ for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1)
+ if (! (mask & ex_info->valid))
+ break;
+
+ if (bytes)
+ {
+ int status;
+
+ pc += offset;
+ status = (*info->read_memory_func)
+ (pc, ex_info->insn_bytes + offset, bytes, info);
+
+ if (status != 0)
+ {
+ (*info->memory_error_func) (status, pc, info);
+ return 0;
+ }
+
+ ex_info->valid |= ((1 << bytes) - 1) << offset;
+ }
+
+ return 1;
+}
+
+/* Subroutine of extract_normal. */
+
+static CGEN_INLINE long
+extract_1 (cd, ex_info, start, length, word_length, bufp, pc)
+ CGEN_CPU_DESC cd;
+ CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED;
+ int start,length,word_length;
+ unsigned char *bufp;
+ bfd_vma pc ATTRIBUTE_UNUSED;
+{
+ unsigned long x;
+ int shift;
+#if 0
+ int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
+#endif
+ x = cgen_get_insn_value (cd, bufp, word_length);
+
+ if (CGEN_INSN_LSB0_P)
+ shift = (start + 1) - length;
+ else
+ shift = (word_length - (start + length));
+ return x >> shift;
+}
+
+#endif /* ! CGEN_INT_INSN_P */
+
+/* Default extraction routine.
+
+ INSN_VALUE is the first base_insn_bitsize bits of the insn in host order,
+ or sometimes less for cases like the m32r where the base insn size is 32
+ but some insns are 16 bits.
+ ATTRS is a mask of the boolean attributes. We only need `SIGNED',
+ but for generality we take a bitmask of all of them.
+ WORD_OFFSET is the offset in bits from the start of the insn of the value.
+ WORD_LENGTH is the length of the word in bits in which the value resides.
+ START is the starting bit number in the word, architecture origin.
+ LENGTH is the length of VALUE in bits.
+ TOTAL_LENGTH is the total length of the insn in bits.
+
+ Returns 1 for success, 0 for failure. */
+
+/* ??? The return code isn't properly used. wip. */
+
+/* ??? This doesn't handle bfd_vma's. Create another function when
+ necessary. */
+
+static int
+extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length,
+ word_length, total_length, pc, valuep)
+ CGEN_CPU_DESC cd;
+#if ! CGEN_INT_INSN_P
+ CGEN_EXTRACT_INFO *ex_info;
+#else
+ CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED;
+#endif
+ CGEN_INSN_INT insn_value;
+ unsigned int attrs;
+ unsigned int word_offset, start, length, word_length, total_length;
+#if ! CGEN_INT_INSN_P
+ bfd_vma pc;
+#else
+ bfd_vma pc ATTRIBUTE_UNUSED;
+#endif
+ long *valuep;
+{
+ long value, mask;
+
+ /* If LENGTH is zero, this operand doesn't contribute to the value
+ so give it a standard value of zero. */
+ if (length == 0)
+ {
+ *valuep = 0;
+ return 1;
+ }
+
+#if 0
+ if (CGEN_INT_INSN_P
+ && word_offset != 0)
+ abort ();
+#endif
+
+ if (word_length > 32)
+ abort ();
+
+ /* For architectures with insns smaller than the insn-base-bitsize,
+ word_length may be too big. */
+ if (cd->min_insn_bitsize < cd->base_insn_bitsize)
+ {
+ if (word_offset == 0
+ && word_length > total_length)
+ word_length = total_length;
+ }
+
+ /* Does the value reside in INSN_VALUE, and at the right alignment? */
+
+ if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length))
+ {
+ if (CGEN_INSN_LSB0_P)
+ value = insn_value >> ((word_offset + start + 1) - length);
+ else
+ value = insn_value >> (total_length - ( word_offset + start + length));
+ }
+
+#if ! CGEN_INT_INSN_P
+
+ else
+ {
+ unsigned char *bufp = ex_info->insn_bytes + word_offset / 8;
+
+ if (word_length > 32)
+ abort ();
+
+ if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0)
+ return 0;
+
+ value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc);
+ }
+
+#endif /* ! CGEN_INT_INSN_P */
+
+ /* Written this way to avoid undefined behaviour. */
+ mask = (((1L << (length - 1)) - 1) << 1) | 1;
+
+ value &= mask;
+ /* sign extend? */
+ if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)
+ && (value & (1L << (length - 1))))
+ value |= ~mask;
+
+ *valuep = value;
+
+ return 1;
+}
+
+/* Default insn extractor.
+
+ INSN_VALUE is the first base_insn_bitsize bits, translated to host order.
+ The extracted fields are stored in FIELDS.
+ EX_INFO is used to handle reading variable length insns.
+ Return the length of the insn in bits, or 0 if no match,
+ or -1 if an error occurs fetching data (memory_error_func will have
+ been called). */
+
+static int
+extract_insn_normal (cd, insn, ex_info, insn_value, fields, pc)
+ CGEN_CPU_DESC cd;
+ const CGEN_INSN *insn;
+ CGEN_EXTRACT_INFO *ex_info;
+ CGEN_INSN_INT insn_value;
+ CGEN_FIELDS *fields;
+ bfd_vma pc;
+{
+ const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
+ const CGEN_SYNTAX_CHAR_TYPE *syn;
+
+ CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
+
+ CGEN_INIT_EXTRACT (cd);
+
+ for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
+ {
+ int length;
+
+ if (CGEN_SYNTAX_CHAR_P (*syn))
+ continue;
+
+ length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
+ ex_info, insn_value, fields, pc);
+ if (length <= 0)
+ return length;
+ }
+
+ /* We recognized and successfully extracted this insn. */
+ return CGEN_INSN_BITSIZE (insn);
+}
+
+/* machine generated code added here */
+
+const char * xstormy16_cgen_insert_operand
+ PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma));
+
+/* Main entry point for operand insertion.
+
+ This function is basically just a big switch statement. Earlier versions
+ used tables to look up the function to use, but
+ - if the table contains both assembler and disassembler functions then
+ the disassembler contains much of the assembler and vice-versa,
+ - there's a lot of inlining possibilities as things grow,
+ - using a switch statement avoids the function call overhead.
+
+ This function could be moved into `parse_insn_normal', but keeping it
+ separate makes clear the interface between `parse_insn_normal' and each of
+ the handlers. It's also needed by GAS to insert operands that couldn't be
+ resolved during parsing. */
+
+const char *
+xstormy16_cgen_insert_operand (cd, opindex, fields, buffer, pc)
+ CGEN_CPU_DESC cd;
+ int opindex;
+ CGEN_FIELDS * fields;
+ CGEN_INSN_BYTES_PTR buffer;
+ bfd_vma pc ATTRIBUTE_UNUSED;
+{
+ const char * errmsg = NULL;
+ unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
+
+ switch (opindex)
+ {
+ case XSTORMY16_OPERAND_RB :
+ errmsg = insert_normal (cd, fields->f_Rb, 0, 0, 17, 3, 32, total_length, buffer);
+ break;
+ case XSTORMY16_OPERAND_RBJ :
+ errmsg = insert_normal (cd, fields->f_Rbj, 0, 0, 11, 1, 32, total_length, buffer);
+ break;
+ case XSTORMY16_OPERAND_RD :
+ errmsg = insert_normal (cd, fields->f_Rd, 0, 0, 12, 4, 32, total_length, buffer);
+ break;
+ case XSTORMY16_OPERAND_RDM :
+ errmsg = insert_normal (cd, fields->f_Rdm, 0, 0, 13, 3, 32, total_length, buffer);
+ break;
+ case XSTORMY16_OPERAND_RM :
+ errmsg = insert_normal (cd, fields->f_Rm, 0, 0, 4, 3, 32, total_length, buffer);
+ break;
+ case XSTORMY16_OPERAND_RS :
+ errmsg = insert_normal (cd, fields->f_Rs, 0, 0, 8, 4, 32, total_length, buffer);
+ break;
+ case XSTORMY16_OPERAND_ABS24 :
+ {
+{
+ FLD (f_abs24_1) = ((FLD (f_abs24)) & (255));
+ FLD (f_abs24_2) = ((unsigned int) (FLD (f_abs24)) >> (8));
+}
+ errmsg = insert_normal (cd, fields->f_abs24_1, 0, 0, 8, 8, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ errmsg = insert_normal (cd, fields->f_abs24_2, 0, 0, 16, 16, 32, total_length, buffer);
+ if (errmsg)
+ break;
+ }
+ break;
+ case XSTORMY16_OPERAND_BCOND2 :
+ errmsg = insert_normal (cd, fields->f_op2, 0, 0, 4, 4, 32, total_length, buffer);
+ break;
+ case XSTORMY16_OPERAND_BCOND5 :
+ errmsg = insert_normal (cd, fields->f_op5, 0, 0, 16, 4, 32, total_length, buffer);
+ break;
+ case XSTORMY16_OPERAND_HMEM8 :
+ {
+ long value = fields->f_hmem8;
+ value = ((value) - (32512));
+ errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_ABS_ADDR), 0, 8, 8, 32, total_length, buffer);
+ }
+ break;
+ case XSTORMY16_OPERAND_IMM12 :
+ errmsg = insert_normal (cd, fields->f_imm12, 0|(1<<CGEN_IFLD_SIGNED), 0, 20, 12, 32, total_length, buffer);
+ break;
+ case XSTORMY16_OPERAND_IMM16 :
+ errmsg = insert_normal (cd, fields->f_imm16, 0|(1<<CGEN_IFLD_SIGN_OPT), 0, 16, 16, 32, total_length, buffer);
+ break;
+ case XSTORMY16_OPERAND_IMM2 :
+ errmsg = insert_normal (cd, fields->f_imm2, 0, 0, 10, 2, 32, total_length, buffer);
+ break;
+ case XSTORMY16_OPERAND_IMM3 :
+ errmsg = insert_normal (cd, fields->f_imm3, 0, 0, 4, 3, 32, total_length, buffer);
+ break;
+ case XSTORMY16_OPERAND_IMM3B :
+ errmsg = insert_normal (cd, fields->f_imm3b, 0, 0, 17, 3, 32, total_length, buffer);
+ break;
+ case XSTORMY16_OPERAND_IMM4 :
+ errmsg = insert_normal (cd, fields->f_imm4, 0, 0, 8, 4, 32, total_length, buffer);
+ break;
+ case XSTORMY16_OPERAND_IMM8 :
+ errmsg = insert_normal (cd, fields->f_imm8, 0, 0, 8, 8, 32, total_length, buffer);
+ break;
+ case XSTORMY16_OPERAND_IMM8SMALL :
+ errmsg = insert_normal (cd, fields->f_imm8, 0, 0, 8, 8, 32, total_length, buffer);
+ break;
+ case XSTORMY16_OPERAND_LMEM8 :
+ errmsg = insert_normal (cd, fields->f_lmem8, 0|(1<<CGEN_IFLD_ABS_ADDR), 0, 8, 8, 32, total_length, buffer);
+ break;
+ case XSTORMY16_OPERAND_REL12 :
+ {
+ long value = fields->f_rel12;
+ value = ((value) - (((pc) + (4))));
+ errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 20, 12, 32, total_length, buffer);
+ }
+ break;
+ case XSTORMY16_OPERAND_REL12A :
+ {
+ long value = fields->f_rel12a;
+ value = ((int) (((value) - (((pc) + (2))))) >> (1));
+ errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 4, 11, 32, total_length, buffer);
+ }
+ break;
+ case XSTORMY16_OPERAND_REL8_2 :
+ {
+ long value = fields->f_rel8_2;
+ value = ((value) - (((pc) + (2))));
+ errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 8, 32, total_length, buffer);
+ }
+ break;
+ case XSTORMY16_OPERAND_REL8_4 :
+ {
+ long value = fields->f_rel8_4;
+ value = ((value) - (((pc) + (4))));
+ errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 8, 32, total_length, buffer);
+ }
+ break;
+ case XSTORMY16_OPERAND_WS2 :
+ errmsg = insert_normal (cd, fields->f_op2m, 0, 0, 7, 1, 32, total_length, buffer);
+ break;
+
+ default :
+ /* xgettext:c-format */
+ fprintf (stderr, _("Unrecognized field %d while building insn.\n"),
+ opindex);
+ abort ();
+ }
+
+ return errmsg;
+}
+
+int xstormy16_cgen_extract_operand
+ PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
+ CGEN_FIELDS *, bfd_vma));
+
+/* Main entry point for operand extraction.
+ The result is <= 0 for error, >0 for success.
+ ??? Actual values aren't well defined right now.
+
+ This function is basically just a big switch statement. Earlier versions
+ used tables to look up the function to use, but
+ - if the table contains both assembler and disassembler functions then
+ the disassembler contains much of the assembler and vice-versa,
+ - there's a lot of inlining possibilities as things grow,
+ - using a switch statement avoids the function call overhead.
+
+ This function could be moved into `print_insn_normal', but keeping it
+ separate makes clear the interface between `print_insn_normal' and each of
+ the handlers. */
+
+int
+xstormy16_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc)
+ CGEN_CPU_DESC cd;
+ int opindex;
+ CGEN_EXTRACT_INFO *ex_info;
+ CGEN_INSN_INT insn_value;
+ CGEN_FIELDS * fields;
+ bfd_vma pc;
+{
+ /* Assume success (for those operands that are nops). */
+ int length = 1;
+ unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
+
+ switch (opindex)
+ {
+ case XSTORMY16_OPERAND_RB :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 3, 32, total_length, pc, & fields->f_Rb);
+ break;
+ case XSTORMY16_OPERAND_RBJ :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 1, 32, total_length, pc, & fields->f_Rbj);
+ break;
+ case XSTORMY16_OPERAND_RD :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_Rd);
+ break;
+ case XSTORMY16_OPERAND_RDM :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 13, 3, 32, total_length, pc, & fields->f_Rdm);
+ break;
+ case XSTORMY16_OPERAND_RM :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 3, 32, total_length, pc, & fields->f_Rm);
+ break;
+ case XSTORMY16_OPERAND_RS :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 32, total_length, pc, & fields->f_Rs);
+ break;
+ case XSTORMY16_OPERAND_ABS24 :
+ {
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 32, total_length, pc, & fields->f_abs24_1);
+ if (length <= 0) break;
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_abs24_2);
+ if (length <= 0) break;
+ FLD (f_abs24) = ((((FLD (f_abs24_2)) << (8))) | (FLD (f_abs24_1)));
+ }
+ break;
+ case XSTORMY16_OPERAND_BCOND2 :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_op2);
+ break;
+ case XSTORMY16_OPERAND_BCOND5 :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 4, 32, total_length, pc, & fields->f_op5);
+ break;
+ case XSTORMY16_OPERAND_HMEM8 :
+ {
+ long value;
+ length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_ABS_ADDR), 0, 8, 8, 32, total_length, pc, & value);
+ value = ((value) + (32512));
+ fields->f_hmem8 = value;
+ }
+ break;
+ case XSTORMY16_OPERAND_IMM12 :
+ length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 20, 12, 32, total_length, pc, & fields->f_imm12);
+ break;
+ case XSTORMY16_OPERAND_IMM16 :
+ length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGN_OPT), 0, 16, 16, 32, total_length, pc, & fields->f_imm16);
+ break;
+ case XSTORMY16_OPERAND_IMM2 :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 2, 32, total_length, pc, & fields->f_imm2);
+ break;
+ case XSTORMY16_OPERAND_IMM3 :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 3, 32, total_length, pc, & fields->f_imm3);
+ break;
+ case XSTORMY16_OPERAND_IMM3B :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 3, 32, total_length, pc, & fields->f_imm3b);
+ break;
+ case XSTORMY16_OPERAND_IMM4 :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 32, total_length, pc, & fields->f_imm4);
+ break;
+ case XSTORMY16_OPERAND_IMM8 :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 32, total_length, pc, & fields->f_imm8);
+ break;
+ case XSTORMY16_OPERAND_IMM8SMALL :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 32, total_length, pc, & fields->f_imm8);
+ break;
+ case XSTORMY16_OPERAND_LMEM8 :
+ length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_ABS_ADDR), 0, 8, 8, 32, total_length, pc, & fields->f_lmem8);
+ break;
+ case XSTORMY16_OPERAND_REL12 :
+ {
+ long value;
+ length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 20, 12, 32, total_length, pc, & value);
+ value = ((value) + (((pc) + (4))));
+ fields->f_rel12 = value;
+ }
+ break;
+ case XSTORMY16_OPERAND_REL12A :
+ {
+ long value;
+ length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 4, 11, 32, total_length, pc, & value);
+ value = ((((value) << (1))) + (((pc) + (2))));
+ fields->f_rel12a = value;
+ }
+ break;
+ case XSTORMY16_OPERAND_REL8_2 :
+ {
+ long value;
+ length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 8, 32, total_length, pc, & value);
+ value = ((value) + (((pc) + (2))));
+ fields->f_rel8_2 = value;
+ }
+ break;
+ case XSTORMY16_OPERAND_REL8_4 :
+ {
+ long value;
+ length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 8, 32, total_length, pc, & value);
+ value = ((value) + (((pc) + (4))));
+ fields->f_rel8_4 = value;
+ }
+ break;
+ case XSTORMY16_OPERAND_WS2 :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 1, 32, total_length, pc, & fields->f_op2m);
+ break;
+
+ default :
+ /* xgettext:c-format */
+ fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"),
+ opindex);
+ abort ();
+ }
+
+ return length;
+}
+
+cgen_insert_fn * const xstormy16_cgen_insert_handlers[] =
+{
+ insert_insn_normal,
+};
+
+cgen_extract_fn * const xstormy16_cgen_extract_handlers[] =
+{
+ extract_insn_normal,
+};
+
+int xstormy16_cgen_get_int_operand
+ PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
+bfd_vma xstormy16_cgen_get_vma_operand
+ PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
+
+/* Getting values from cgen_fields is handled by a collection of functions.
+ They are distinguished by the type of the VALUE argument they return.
+ TODO: floating point, inlining support, remove cases where result type
+ not appropriate. */
+
+int
+xstormy16_cgen_get_int_operand (cd, opindex, fields)
+ CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
+ int opindex;
+ const CGEN_FIELDS * fields;
+{
+ int value;
+
+ switch (opindex)
+ {
+ case XSTORMY16_OPERAND_RB :
+ value = fields->f_Rb;
+ break;
+ case XSTORMY16_OPERAND_RBJ :
+ value = fields->f_Rbj;
+ break;
+ case XSTORMY16_OPERAND_RD :
+ value = fields->f_Rd;
+ break;
+ case XSTORMY16_OPERAND_RDM :
+ value = fields->f_Rdm;
+ break;
+ case XSTORMY16_OPERAND_RM :
+ value = fields->f_Rm;
+ break;
+ case XSTORMY16_OPERAND_RS :
+ value = fields->f_Rs;
+ break;
+ case XSTORMY16_OPERAND_ABS24 :
+ value = fields->f_abs24;
+ break;
+ case XSTORMY16_OPERAND_BCOND2 :
+ value = fields->f_op2;
+ break;
+ case XSTORMY16_OPERAND_BCOND5 :
+ value = fields->f_op5;
+ break;
+ case XSTORMY16_OPERAND_HMEM8 :
+ value = fields->f_hmem8;
+ break;
+ case XSTORMY16_OPERAND_IMM12 :
+ value = fields->f_imm12;
+ break;
+ case XSTORMY16_OPERAND_IMM16 :
+ value = fields->f_imm16;
+ break;
+ case XSTORMY16_OPERAND_IMM2 :
+ value = fields->f_imm2;
+ break;
+ case XSTORMY16_OPERAND_IMM3 :
+ value = fields->f_imm3;
+ break;
+ case XSTORMY16_OPERAND_IMM3B :
+ value = fields->f_imm3b;
+ break;
+ case XSTORMY16_OPERAND_IMM4 :
+ value = fields->f_imm4;
+ break;
+ case XSTORMY16_OPERAND_IMM8 :
+ value = fields->f_imm8;
+ break;
+ case XSTORMY16_OPERAND_IMM8SMALL :
+ value = fields->f_imm8;
+ break;
+ case XSTORMY16_OPERAND_LMEM8 :
+ value = fields->f_lmem8;
+ break;
+ case XSTORMY16_OPERAND_REL12 :
+ value = fields->f_rel12;
+ break;
+ case XSTORMY16_OPERAND_REL12A :
+ value = fields->f_rel12a;
+ break;
+ case XSTORMY16_OPERAND_REL8_2 :
+ value = fields->f_rel8_2;
+ break;
+ case XSTORMY16_OPERAND_REL8_4 :
+ value = fields->f_rel8_4;
+ break;
+ case XSTORMY16_OPERAND_WS2 :
+ value = fields->f_op2m;
+ break;
+
+ default :
+ /* xgettext:c-format */
+ fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
+ opindex);
+ abort ();
+ }
+
+ return value;
+}
+
+bfd_vma
+xstormy16_cgen_get_vma_operand (cd, opindex, fields)
+ CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
+ int opindex;
+ const CGEN_FIELDS * fields;
+{
+ bfd_vma value;
+
+ switch (opindex)
+ {
+ case XSTORMY16_OPERAND_RB :
+ value = fields->f_Rb;
+ break;
+ case XSTORMY16_OPERAND_RBJ :
+ value = fields->f_Rbj;
+ break;
+ case XSTORMY16_OPERAND_RD :
+ value = fields->f_Rd;
+ break;
+ case XSTORMY16_OPERAND_RDM :
+ value = fields->f_Rdm;
+ break;
+ case XSTORMY16_OPERAND_RM :
+ value = fields->f_Rm;
+ break;
+ case XSTORMY16_OPERAND_RS :
+ value = fields->f_Rs;
+ break;
+ case XSTORMY16_OPERAND_ABS24 :
+ value = fields->f_abs24;
+ break;
+ case XSTORMY16_OPERAND_BCOND2 :
+ value = fields->f_op2;
+ break;
+ case XSTORMY16_OPERAND_BCOND5 :
+ value = fields->f_op5;
+ break;
+ case XSTORMY16_OPERAND_HMEM8 :
+ value = fields->f_hmem8;
+ break;
+ case XSTORMY16_OPERAND_IMM12 :
+ value = fields->f_imm12;
+ break;
+ case XSTORMY16_OPERAND_IMM16 :
+ value = fields->f_imm16;
+ break;
+ case XSTORMY16_OPERAND_IMM2 :
+ value = fields->f_imm2;
+ break;
+ case XSTORMY16_OPERAND_IMM3 :
+ value = fields->f_imm3;
+ break;
+ case XSTORMY16_OPERAND_IMM3B :
+ value = fields->f_imm3b;
+ break;
+ case XSTORMY16_OPERAND_IMM4 :
+ value = fields->f_imm4;
+ break;
+ case XSTORMY16_OPERAND_IMM8 :
+ value = fields->f_imm8;
+ break;
+ case XSTORMY16_OPERAND_IMM8SMALL :
+ value = fields->f_imm8;
+ break;
+ case XSTORMY16_OPERAND_LMEM8 :
+ value = fields->f_lmem8;
+ break;
+ case XSTORMY16_OPERAND_REL12 :
+ value = fields->f_rel12;
+ break;
+ case XSTORMY16_OPERAND_REL12A :
+ value = fields->f_rel12a;
+ break;
+ case XSTORMY16_OPERAND_REL8_2 :
+ value = fields->f_rel8_2;
+ break;
+ case XSTORMY16_OPERAND_REL8_4 :
+ value = fields->f_rel8_4;
+ break;
+ case XSTORMY16_OPERAND_WS2 :
+ value = fields->f_op2m;
+ break;
+
+ default :
+ /* xgettext:c-format */
+ fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
+ opindex);
+ abort ();
+ }
+
+ return value;
+}
+
+void xstormy16_cgen_set_int_operand
+ PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int));
+void xstormy16_cgen_set_vma_operand
+ PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma));
+
+/* Stuffing values in cgen_fields is handled by a collection of functions.
+ They are distinguished by the type of the VALUE argument they accept.
+ TODO: floating point, inlining support, remove cases where argument type
+ not appropriate. */
+
+void
+xstormy16_cgen_set_int_operand (cd, opindex, fields, value)
+ CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
+ int opindex;
+ CGEN_FIELDS * fields;
+ int value;
+{
+ switch (opindex)
+ {
+ case XSTORMY16_OPERAND_RB :
+ fields->f_Rb = value;
+ break;
+ case XSTORMY16_OPERAND_RBJ :
+ fields->f_Rbj = value;
+ break;
+ case XSTORMY16_OPERAND_RD :
+ fields->f_Rd = value;
+ break;
+ case XSTORMY16_OPERAND_RDM :
+ fields->f_Rdm = value;
+ break;
+ case XSTORMY16_OPERAND_RM :
+ fields->f_Rm = value;
+ break;
+ case XSTORMY16_OPERAND_RS :
+ fields->f_Rs = value;
+ break;
+ case XSTORMY16_OPERAND_ABS24 :
+ fields->f_abs24 = value;
+ break;
+ case XSTORMY16_OPERAND_BCOND2 :
+ fields->f_op2 = value;
+ break;
+ case XSTORMY16_OPERAND_BCOND5 :
+ fields->f_op5 = value;
+ break;
+ case XSTORMY16_OPERAND_HMEM8 :
+ fields->f_hmem8 = value;
+ break;
+ case XSTORMY16_OPERAND_IMM12 :
+ fields->f_imm12 = value;
+ break;
+ case XSTORMY16_OPERAND_IMM16 :
+ fields->f_imm16 = value;
+ break;
+ case XSTORMY16_OPERAND_IMM2 :
+ fields->f_imm2 = value;
+ break;
+ case XSTORMY16_OPERAND_IMM3 :
+ fields->f_imm3 = value;
+ break;
+ case XSTORMY16_OPERAND_IMM3B :
+ fields->f_imm3b = value;
+ break;
+ case XSTORMY16_OPERAND_IMM4 :
+ fields->f_imm4 = value;
+ break;
+ case XSTORMY16_OPERAND_IMM8 :
+ fields->f_imm8 = value;
+ break;
+ case XSTORMY16_OPERAND_IMM8SMALL :
+ fields->f_imm8 = value;
+ break;
+ case XSTORMY16_OPERAND_LMEM8 :
+ fields->f_lmem8 = value;
+ break;
+ case XSTORMY16_OPERAND_REL12 :
+ fields->f_rel12 = value;
+ break;
+ case XSTORMY16_OPERAND_REL12A :
+ fields->f_rel12a = value;
+ break;
+ case XSTORMY16_OPERAND_REL8_2 :
+ fields->f_rel8_2 = value;
+ break;
+ case XSTORMY16_OPERAND_REL8_4 :
+ fields->f_rel8_4 = value;
+ break;
+ case XSTORMY16_OPERAND_WS2 :
+ fields->f_op2m = value;
+ break;
+
+ default :
+ /* xgettext:c-format */
+ fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
+ opindex);
+ abort ();
+ }
+}
+
+void
+xstormy16_cgen_set_vma_operand (cd, opindex, fields, value)
+ CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
+ int opindex;
+ CGEN_FIELDS * fields;
+ bfd_vma value;
+{
+ switch (opindex)
+ {
+ case XSTORMY16_OPERAND_RB :
+ fields->f_Rb = value;
+ break;
+ case XSTORMY16_OPERAND_RBJ :
+ fields->f_Rbj = value;
+ break;
+ case XSTORMY16_OPERAND_RD :
+ fields->f_Rd = value;
+ break;
+ case XSTORMY16_OPERAND_RDM :
+ fields->f_Rdm = value;
+ break;
+ case XSTORMY16_OPERAND_RM :
+ fields->f_Rm = value;
+ break;
+ case XSTORMY16_OPERAND_RS :
+ fields->f_Rs = value;
+ break;
+ case XSTORMY16_OPERAND_ABS24 :
+ fields->f_abs24 = value;
+ break;
+ case XSTORMY16_OPERAND_BCOND2 :
+ fields->f_op2 = value;
+ break;
+ case XSTORMY16_OPERAND_BCOND5 :
+ fields->f_op5 = value;
+ break;
+ case XSTORMY16_OPERAND_HMEM8 :
+ fields->f_hmem8 = value;
+ break;
+ case XSTORMY16_OPERAND_IMM12 :
+ fields->f_imm12 = value;
+ break;
+ case XSTORMY16_OPERAND_IMM16 :
+ fields->f_imm16 = value;
+ break;
+ case XSTORMY16_OPERAND_IMM2 :
+ fields->f_imm2 = value;
+ break;
+ case XSTORMY16_OPERAND_IMM3 :
+ fields->f_imm3 = value;
+ break;
+ case XSTORMY16_OPERAND_IMM3B :
+ fields->f_imm3b = value;
+ break;
+ case XSTORMY16_OPERAND_IMM4 :
+ fields->f_imm4 = value;
+ break;
+ case XSTORMY16_OPERAND_IMM8 :
+ fields->f_imm8 = value;
+ break;
+ case XSTORMY16_OPERAND_IMM8SMALL :
+ fields->f_imm8 = value;
+ break;
+ case XSTORMY16_OPERAND_LMEM8 :
+ fields->f_lmem8 = value;
+ break;
+ case XSTORMY16_OPERAND_REL12 :
+ fields->f_rel12 = value;
+ break;
+ case XSTORMY16_OPERAND_REL12A :
+ fields->f_rel12a = value;
+ break;
+ case XSTORMY16_OPERAND_REL8_2 :
+ fields->f_rel8_2 = value;
+ break;
+ case XSTORMY16_OPERAND_REL8_4 :
+ fields->f_rel8_4 = value;
+ break;
+ case XSTORMY16_OPERAND_WS2 :
+ fields->f_op2m = value;
+ break;
+
+ default :
+ /* xgettext:c-format */
+ fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
+ opindex);
+ abort ();
+ }
+}
+
+/* Function to call before using the instruction builder tables. */
+
+void
+xstormy16_cgen_init_ibld_table (cd)
+ CGEN_CPU_DESC cd;
+{
+ cd->insert_handlers = & xstormy16_cgen_insert_handlers[0];
+ cd->extract_handlers = & xstormy16_cgen_extract_handlers[0];
+
+ cd->insert_operand = xstormy16_cgen_insert_operand;
+ cd->extract_operand = xstormy16_cgen_extract_operand;
+
+ cd->get_int_operand = xstormy16_cgen_get_int_operand;
+ cd->set_int_operand = xstormy16_cgen_set_int_operand;
+ cd->get_vma_operand = xstormy16_cgen_get_vma_operand;
+ cd->set_vma_operand = xstormy16_cgen_set_vma_operand;
+}
diff --git a/opcodes/xstormy16-opc.c b/opcodes/xstormy16-opc.c
new file mode 100644
index 0000000..c4dc9c0
--- /dev/null
+++ b/opcodes/xstormy16-opc.c
@@ -0,0 +1,1171 @@
+/* Instruction opcode table for xstormy16.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#include "sysdep.h"
+#include "ansidecl.h"
+#include "bfd.h"
+#include "symcat.h"
+#include "xstormy16-desc.h"
+#include "xstormy16-opc.h"
+#include "libiberty.h"
+
+/* The hash functions are recorded here to help keep assembler code out of
+ the disassembler and vice versa. */
+
+static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
+static unsigned int asm_hash_insn PARAMS ((const char *));
+static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
+static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
+
+/* Instruction formats. */
+
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define F(f) & xstormy16_cgen_ifld_table[XSTORMY16_##f]
+#else
+#define F(f) & xstormy16_cgen_ifld_table[XSTORMY16_/**/f]
+#endif
+static const CGEN_IFMT ifmt_empty = {
+ 0, 0, 0x0, { { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movlmemimm = {
+ 32, 32, 0xfe000000, { { F (F_OP1) }, { F (F_OP2A) }, { F (F_OP2M) }, { F (F_LMEM8) }, { F (F_IMM16) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movhmemimm = {
+ 32, 32, 0xfe000000, { { F (F_OP1) }, { F (F_OP2A) }, { F (F_OP2M) }, { F (F_HMEM8) }, { F (F_IMM16) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movlgrmem = {
+ 16, 16, 0xf000, { { F (F_OP1) }, { F (F_RM) }, { F (F_OP2M) }, { F (F_LMEM8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movhgrmem = {
+ 16, 16, 0xf000, { { F (F_OP1) }, { F (F_RM) }, { F (F_OP2M) }, { F (F_HMEM8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movgrgri = {
+ 16, 16, 0xfe08, { { F (F_OP1) }, { F (F_OP2A) }, { F (F_OP2M) }, { F (F_RS) }, { F (F_OP4M) }, { F (F_RDM) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movgrgrii = {
+ 32, 32, 0xfe08f000, { { F (F_OP1) }, { F (F_OP2A) }, { F (F_OP2M) }, { F (F_RS) }, { F (F_OP4M) }, { F (F_RDM) }, { F (F_OP5) }, { F (F_IMM12) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movgrgr = {
+ 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_RS) }, { F (F_RD) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movwimm8 = {
+ 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_IMM8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movwgrimm8 = {
+ 16, 16, 0xf100, { { F (F_OP1) }, { F (F_RM) }, { F (F_OP2M) }, { F (F_IMM8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movwgrimm16 = {
+ 32, 32, 0xfff00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_OP3) }, { F (F_RD) }, { F (F_IMM16) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movlowgr = {
+ 16, 16, 0xfff0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_OP3) }, { F (F_RD) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movfgrgrii = {
+ 32, 32, 0xfe088000, { { F (F_OP1) }, { F (F_OP2A) }, { F (F_OP2M) }, { F (F_RS) }, { F (F_OP4M) }, { F (F_RDM) }, { F (F_OP5A) }, { F (F_RB) }, { F (F_IMM12) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_addgrimm4 = {
+ 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_IMM4) }, { F (F_RD) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_incgrimm2 = {
+ 16, 16, 0xffc0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_OP3A) }, { F (F_IMM2) }, { F (F_RD) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_set1lmemimm = {
+ 16, 16, 0xf100, { { F (F_OP1) }, { F (F_IMM3) }, { F (F_OP2M) }, { F (F_LMEM8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_set1hmemimm = {
+ 16, 16, 0xf100, { { F (F_OP1) }, { F (F_IMM3) }, { F (F_OP2M) }, { F (F_HMEM8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bccgrgr = {
+ 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_RS) }, { F (F_RD) }, { F (F_OP5) }, { F (F_REL12) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bccgrimm8 = {
+ 32, 32, 0xf1000000, { { F (F_OP1) }, { F (F_RM) }, { F (F_OP2M) }, { F (F_IMM8) }, { F (F_OP5) }, { F (F_REL12) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bccimm16 = {
+ 32, 32, 0xf0000000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_REL8_4) }, { F (F_IMM16) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bngrimm4 = {
+ 32, 32, 0xff00f000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_IMM4) }, { F (F_RD) }, { F (F_OP5) }, { F (F_REL12) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bngrgr = {
+ 32, 32, 0xff00f000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_RS) }, { F (F_RD) }, { F (F_OP5) }, { F (F_REL12) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bnlmemimm = {
+ 32, 32, 0xff008000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_LMEM8) }, { F (F_OP5A) }, { F (F_IMM3B) }, { F (F_REL12) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bnhmemimm = {
+ 32, 32, 0xff008000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_HMEM8) }, { F (F_OP5A) }, { F (F_IMM3B) }, { F (F_REL12) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bcc = {
+ 16, 16, 0xf000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_REL8_2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_br = {
+ 16, 16, 0xf001, { { F (F_OP1) }, { F (F_REL12A) }, { F (F_OP4B) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_jmp = {
+ 16, 16, 0xffe0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_OP3B) }, { F (F_RBJ) }, { F (F_RD) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_jmpf = {
+ 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_ABS24) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_iret = {
+ 16, 16, 0xffff, { { F (F_OP) }, { 0 } }
+};
+
+#undef F
+
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define A(a) (1 << CGEN_INSN_##a)
+#else
+#define A(a) (1 << CGEN_INSN_/**/a)
+#endif
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define OPERAND(op) XSTORMY16_OPERAND_##op
+#else
+#define OPERAND(op) XSTORMY16_OPERAND_/**/op
+#endif
+#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
+#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
+
+/* The instruction table. */
+
+static const CGEN_OPCODE xstormy16_cgen_insn_opcode_table[MAX_INSNS] =
+{
+ /* Special null first entry.
+ A `num' value of zero is thus invalid.
+ Also, the special `invalid' insn resides here. */
+ { { 0, 0, 0, 0 }, {{0}}, 0, {0}},
+/* mov$ws2 $lmem8,#$imm16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (WS2), ' ', OP (LMEM8), ',', '#', OP (IMM16), 0 } },
+ & ifmt_movlmemimm, { 0x78000000 }
+ },
+/* mov$ws2 $hmem8,#$imm16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (WS2), ' ', OP (HMEM8), ',', '#', OP (IMM16), 0 } },
+ & ifmt_movhmemimm, { 0x7a000000 }
+ },
+/* mov$ws2 $Rm,$lmem8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (WS2), ' ', OP (RM), ',', OP (LMEM8), 0 } },
+ & ifmt_movlgrmem, { 0x8000 }
+ },
+/* mov$ws2 $Rm,$hmem8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (WS2), ' ', OP (RM), ',', OP (HMEM8), 0 } },
+ & ifmt_movhgrmem, { 0xa000 }
+ },
+/* mov$ws2 $lmem8,$Rm */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (WS2), ' ', OP (LMEM8), ',', OP (RM), 0 } },
+ & ifmt_movlgrmem, { 0x9000 }
+ },
+/* mov$ws2 $hmem8,$Rm */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (WS2), ' ', OP (HMEM8), ',', OP (RM), 0 } },
+ & ifmt_movhgrmem, { 0xb000 }
+ },
+/* mov$ws2 $Rdm,($Rs) */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RS), ')', 0 } },
+ & ifmt_movgrgri, { 0x7000 }
+ },
+/* mov$ws2 $Rdm,($Rs++) */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RS), '+', '+', ')', 0 } },
+ & ifmt_movgrgri, { 0x6000 }
+ },
+/* mov$ws2 $Rdm,(--$Rs) */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', '-', '-', OP (RS), ')', 0 } },
+ & ifmt_movgrgri, { 0x6800 }
+ },
+/* mov$ws2 ($Rs),$Rdm */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (WS2), ' ', '(', OP (RS), ')', ',', OP (RDM), 0 } },
+ & ifmt_movgrgri, { 0x7200 }
+ },
+/* mov$ws2 ($Rs++),$Rdm */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (WS2), ' ', '(', OP (RS), '+', '+', ')', ',', OP (RDM), 0 } },
+ & ifmt_movgrgri, { 0x6200 }
+ },
+/* mov$ws2 (--$Rs),$Rdm */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (WS2), ' ', '(', '-', '-', OP (RS), ')', ',', OP (RDM), 0 } },
+ & ifmt_movgrgri, { 0x6a00 }
+ },
+/* mov$ws2 $Rdm,($Rs,$imm12) */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RS), ',', OP (IMM12), ')', 0 } },
+ & ifmt_movgrgrii, { 0x70080000 }
+ },
+/* mov$ws2 $Rdm,($Rs++,$imm12) */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RS), '+', '+', ',', OP (IMM12), ')', 0 } },
+ & ifmt_movgrgrii, { 0x60080000 }
+ },
+/* mov$ws2 $Rdm,(--$Rs,$imm12) */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', '-', '-', OP (RS), ',', OP (IMM12), ')', 0 } },
+ & ifmt_movgrgrii, { 0x68080000 }
+ },
+/* mov$ws2 ($Rs,$imm12),$Rdm */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (WS2), ' ', '(', OP (RS), ',', OP (IMM12), ')', ',', OP (RDM), 0 } },
+ & ifmt_movgrgrii, { 0x72080000 }
+ },
+/* mov$ws2 ($Rs++,$imm12),$Rdm */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (WS2), ' ', '(', OP (RS), '+', '+', ',', OP (IMM12), ')', ',', OP (RDM), 0 } },
+ & ifmt_movgrgrii, { 0x62080000 }
+ },
+/* mov$ws2 (--$Rs,$imm12),$Rdm */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (WS2), ' ', '(', '-', '-', OP (RS), ',', OP (IMM12), ')', ',', OP (RDM), 0 } },
+ & ifmt_movgrgrii, { 0x6a080000 }
+ },
+/* mov $Rd,$Rs */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } },
+ & ifmt_movgrgr, { 0x4600 }
+ },
+/* mov.w Rx,#$imm8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', 'R', 'x', ',', '#', OP (IMM8), 0 } },
+ & ifmt_movwimm8, { 0x4700 }
+ },
+/* mov.w $Rm,#$imm8small */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RM), ',', '#', OP (IMM8SMALL), 0 } },
+ & ifmt_movwgrimm8, { 0x2100 }
+ },
+/* mov.w $Rd,#$imm16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '#', OP (IMM16), 0 } },
+ & ifmt_movwgrimm16, { 0x31300000 }
+ },
+/* mov.b $Rd,RxL */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', 'R', 'x', 'L', 0 } },
+ & ifmt_movlowgr, { 0x30c0 }
+ },
+/* mov.b $Rd,RxH */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', 'R', 'x', 'H', 0 } },
+ & ifmt_movlowgr, { 0x30d0 }
+ },
+/* movf$ws2 $Rdm,($Rs) */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RS), ')', 0 } },
+ & ifmt_movgrgri, { 0x7400 }
+ },
+/* movf$ws2 $Rdm,($Rs++) */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RS), '+', '+', ')', 0 } },
+ & ifmt_movgrgri, { 0x6400 }
+ },
+/* movf$ws2 $Rdm,(--$Rs) */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', '-', '-', OP (RS), ')', 0 } },
+ & ifmt_movgrgri, { 0x6c00 }
+ },
+/* movf$ws2 ($Rs),$Rdm */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (WS2), ' ', '(', OP (RS), ')', ',', OP (RDM), 0 } },
+ & ifmt_movgrgri, { 0x7600 }
+ },
+/* movf$ws2 ($Rs++),$Rdm */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (WS2), ' ', '(', OP (RS), '+', '+', ')', ',', OP (RDM), 0 } },
+ & ifmt_movgrgri, { 0x6600 }
+ },
+/* movf$ws2 (--$Rs),$Rdm */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (WS2), ' ', '(', '-', '-', OP (RS), ')', ',', OP (RDM), 0 } },
+ & ifmt_movgrgri, { 0x6e00 }
+ },
+/* movf$ws2 $Rdm,($Rb,$Rs,$imm12) */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RB), ',', OP (RS), ',', OP (IMM12), ')', 0 } },
+ & ifmt_movfgrgrii, { 0x74080000 }
+ },
+/* movf$ws2 $Rdm,($Rb,$Rs++,$imm12) */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RB), ',', OP (RS), '+', '+', ',', OP (IMM12), ')', 0 } },
+ & ifmt_movfgrgrii, { 0x64080000 }
+ },
+/* movf$ws2 $Rdm,($Rb,--$Rs,$imm12) */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RB), ',', '-', '-', OP (RS), ',', OP (IMM12), ')', 0 } },
+ & ifmt_movfgrgrii, { 0x6c080000 }
+ },
+/* movf$ws2 ($Rb,$Rs,$imm12),$Rdm */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (WS2), ' ', '(', OP (RB), ',', OP (RS), ',', OP (IMM12), ')', ',', OP (RDM), 0 } },
+ & ifmt_movfgrgrii, { 0x76080000 }
+ },
+/* movf$ws2 ($Rb,$Rs++,$imm12),$Rdm */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (WS2), ' ', '(', OP (RB), ',', OP (RS), '+', '+', ',', OP (IMM12), ')', ',', OP (RDM), 0 } },
+ & ifmt_movfgrgrii, { 0x66080000 }
+ },
+/* movf$ws2 ($Rb,--$Rs,$imm12),$Rdm */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (WS2), ' ', '(', OP (RB), ',', '-', '-', OP (RS), ',', OP (IMM12), ')', ',', OP (RDM), 0 } },
+ & ifmt_movfgrgrii, { 0x6e080000 }
+ },
+/* mask $Rd,$Rs */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } },
+ & ifmt_movgrgr, { 0x3300 }
+ },
+/* mask $Rd,#$imm16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '#', OP (IMM16), 0 } },
+ & ifmt_movwgrimm16, { 0x30e00000 }
+ },
+/* push $Rd */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), 0 } },
+ & ifmt_movlowgr, { 0x80 }
+ },
+/* pop $Rd */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), 0 } },
+ & ifmt_movlowgr, { 0x90 }
+ },
+/* swpn $Rd */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), 0 } },
+ & ifmt_movlowgr, { 0x3090 }
+ },
+/* swpb $Rd */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), 0 } },
+ & ifmt_movlowgr, { 0x3080 }
+ },
+/* swpw $Rd,$Rs */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } },
+ & ifmt_movgrgr, { 0x3200 }
+ },
+/* and $Rd,$Rs */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } },
+ & ifmt_movgrgr, { 0x4000 }
+ },
+/* and Rx,#$imm8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', 'R', 'x', ',', '#', OP (IMM8), 0 } },
+ & ifmt_movwimm8, { 0x4100 }
+ },
+/* and $Rd,#$imm16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '#', OP (IMM16), 0 } },
+ & ifmt_movwgrimm16, { 0x31000000 }
+ },
+/* or $Rd,$Rs */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } },
+ & ifmt_movgrgr, { 0x4200 }
+ },
+/* or Rx,#$imm8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', 'R', 'x', ',', '#', OP (IMM8), 0 } },
+ & ifmt_movwimm8, { 0x4300 }
+ },
+/* or $Rd,#$imm16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '#', OP (IMM16), 0 } },
+ & ifmt_movwgrimm16, { 0x31100000 }
+ },
+/* xor $Rd,$Rs */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } },
+ & ifmt_movgrgr, { 0x4400 }
+ },
+/* xor Rx,#$imm8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', 'R', 'x', ',', '#', OP (IMM8), 0 } },
+ & ifmt_movwimm8, { 0x4500 }
+ },
+/* xor $Rd,#$imm16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '#', OP (IMM16), 0 } },
+ & ifmt_movwgrimm16, { 0x31200000 }
+ },
+/* not $Rd */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), 0 } },
+ & ifmt_movlowgr, { 0x30b0 }
+ },
+/* add $Rd,$Rs */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } },
+ & ifmt_movgrgr, { 0x4900 }
+ },
+/* add $Rd,#$imm4 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '#', OP (IMM4), 0 } },
+ & ifmt_addgrimm4, { 0x5100 }
+ },
+/* add Rx,#$imm8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', 'R', 'x', ',', '#', OP (IMM8), 0 } },
+ & ifmt_movwimm8, { 0x5900 }
+ },
+/* add $Rd,#$imm16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '#', OP (IMM16), 0 } },
+ & ifmt_movwgrimm16, { 0x31400000 }
+ },
+/* adc $Rd,$Rs */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } },
+ & ifmt_movgrgr, { 0x4b00 }
+ },
+/* adc $Rd,#$imm4 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '#', OP (IMM4), 0 } },
+ & ifmt_addgrimm4, { 0x5300 }
+ },
+/* adc Rx,#$imm8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', 'R', 'x', ',', '#', OP (IMM8), 0 } },
+ & ifmt_movwimm8, { 0x5b00 }
+ },
+/* adc $Rd,#$imm16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '#', OP (IMM16), 0 } },
+ & ifmt_movwgrimm16, { 0x31500000 }
+ },
+/* sub $Rd,$Rs */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } },
+ & ifmt_movgrgr, { 0x4d00 }
+ },
+/* sub $Rd,#$imm4 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '#', OP (IMM4), 0 } },
+ & ifmt_addgrimm4, { 0x5500 }
+ },
+/* sub Rx,#$imm8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', 'R', 'x', ',', '#', OP (IMM8), 0 } },
+ & ifmt_movwimm8, { 0x5d00 }
+ },
+/* sub $Rd,#$imm16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '#', OP (IMM16), 0 } },
+ & ifmt_movwgrimm16, { 0x31600000 }
+ },
+/* sbc $Rd,$Rs */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } },
+ & ifmt_movgrgr, { 0x4f00 }
+ },
+/* sbc $Rd,#$imm4 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '#', OP (IMM4), 0 } },
+ & ifmt_addgrimm4, { 0x5700 }
+ },
+/* sbc Rx,#$imm8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', 'R', 'x', ',', '#', OP (IMM8), 0 } },
+ & ifmt_movwimm8, { 0x5f00 }
+ },
+/* sbc $Rd,#$imm16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '#', OP (IMM16), 0 } },
+ & ifmt_movwgrimm16, { 0x31700000 }
+ },
+/* inc $Rd,#$imm2 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '#', OP (IMM2), 0 } },
+ & ifmt_incgrimm2, { 0x3000 }
+ },
+/* dec $Rd,#$imm2 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '#', OP (IMM2), 0 } },
+ & ifmt_incgrimm2, { 0x3040 }
+ },
+/* rrc $Rd,$Rs */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } },
+ & ifmt_movgrgr, { 0x3800 }
+ },
+/* rrc $Rd,#$imm4 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '#', OP (IMM4), 0 } },
+ & ifmt_addgrimm4, { 0x3900 }
+ },
+/* rlc $Rd,$Rs */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } },
+ & ifmt_movgrgr, { 0x3a00 }
+ },
+/* rlc $Rd,#$imm4 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '#', OP (IMM4), 0 } },
+ & ifmt_addgrimm4, { 0x3b00 }
+ },
+/* shr $Rd,$Rs */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } },
+ & ifmt_movgrgr, { 0x3c00 }
+ },
+/* shr $Rd,#$imm4 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '#', OP (IMM4), 0 } },
+ & ifmt_addgrimm4, { 0x3d00 }
+ },
+/* shl $Rd,$Rs */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } },
+ & ifmt_movgrgr, { 0x3e00 }
+ },
+/* shl $Rd,#$imm4 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '#', OP (IMM4), 0 } },
+ & ifmt_addgrimm4, { 0x3f00 }
+ },
+/* asr $Rd,$Rs */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } },
+ & ifmt_movgrgr, { 0x3600 }
+ },
+/* asr $Rd,#$imm4 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '#', OP (IMM4), 0 } },
+ & ifmt_addgrimm4, { 0x3700 }
+ },
+/* set1 $Rd,#$imm4 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '#', OP (IMM4), 0 } },
+ & ifmt_addgrimm4, { 0x900 }
+ },
+/* set1 $Rd,$Rs */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } },
+ & ifmt_movgrgr, { 0xb00 }
+ },
+/* set1 $lmem8,#$imm3 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (LMEM8), ',', '#', OP (IMM3), 0 } },
+ & ifmt_set1lmemimm, { 0xe100 }
+ },
+/* set1 $hmem8,#$imm3 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (HMEM8), ',', '#', OP (IMM3), 0 } },
+ & ifmt_set1hmemimm, { 0xf100 }
+ },
+/* clr1 $Rd,#$imm4 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '#', OP (IMM4), 0 } },
+ & ifmt_addgrimm4, { 0x800 }
+ },
+/* clr1 $Rd,$Rs */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } },
+ & ifmt_movgrgr, { 0xa00 }
+ },
+/* clr1 $lmem8,#$imm3 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (LMEM8), ',', '#', OP (IMM3), 0 } },
+ & ifmt_set1lmemimm, { 0xe000 }
+ },
+/* clr1 $hmem8,#$imm3 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (HMEM8), ',', '#', OP (IMM3), 0 } },
+ & ifmt_set1hmemimm, { 0xf000 }
+ },
+/* cbw $Rd */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), 0 } },
+ & ifmt_movlowgr, { 0x30a0 }
+ },
+/* rev $Rd */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), 0 } },
+ & ifmt_movlowgr, { 0x30f0 }
+ },
+/* b$bcond5 $Rd,$Rs,$rel12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (BCOND5), ' ', OP (RD), ',', OP (RS), ',', OP (REL12), 0 } },
+ & ifmt_bccgrgr, { 0xd000000 }
+ },
+/* b$bcond5 $Rm,#$imm8,$rel12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (BCOND5), ' ', OP (RM), ',', '#', OP (IMM8), ',', OP (REL12), 0 } },
+ & ifmt_bccgrimm8, { 0x20000000 }
+ },
+/* b$bcond2 Rx,#$imm16,${rel8-4} */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (BCOND2), ' ', 'R', 'x', ',', '#', OP (IMM16), ',', OP (REL8_4), 0 } },
+ & ifmt_bccimm16, { 0xc0000000 }
+ },
+/* bn $Rd,#$imm4,$rel12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '#', OP (IMM4), ',', OP (REL12), 0 } },
+ & ifmt_bngrimm4, { 0x4000000 }
+ },
+/* bn $Rd,$Rs,$rel12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (REL12), 0 } },
+ & ifmt_bngrgr, { 0x6000000 }
+ },
+/* bn $lmem8,#$imm3b,$rel12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (LMEM8), ',', '#', OP (IMM3B), ',', OP (REL12), 0 } },
+ & ifmt_bnlmemimm, { 0x7c000000 }
+ },
+/* bn $hmem8,#$imm3b,$rel12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (HMEM8), ',', '#', OP (IMM3B), ',', OP (REL12), 0 } },
+ & ifmt_bnhmemimm, { 0x7e000000 }
+ },
+/* bp $Rd,#$imm4,$rel12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '#', OP (IMM4), ',', OP (REL12), 0 } },
+ & ifmt_bngrimm4, { 0x5000000 }
+ },
+/* bp $Rd,$Rs,$rel12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (REL12), 0 } },
+ & ifmt_bngrgr, { 0x7000000 }
+ },
+/* bp $lmem8,#$imm3b,$rel12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (LMEM8), ',', '#', OP (IMM3B), ',', OP (REL12), 0 } },
+ & ifmt_bnlmemimm, { 0x7d000000 }
+ },
+/* bp $hmem8,#$imm3b,$rel12 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (HMEM8), ',', '#', OP (IMM3B), ',', OP (REL12), 0 } },
+ & ifmt_bnhmemimm, { 0x7f000000 }
+ },
+/* b$bcond2 ${rel8-2} */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (BCOND2), ' ', OP (REL8_2), 0 } },
+ & ifmt_bcc, { 0xd000 }
+ },
+/* br $Rd */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), 0 } },
+ & ifmt_movlowgr, { 0x20 }
+ },
+/* br $rel12a */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (REL12A), 0 } },
+ & ifmt_br, { 0x1000 }
+ },
+/* jmp $Rbj,$Rd */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RBJ), ',', OP (RD), 0 } },
+ & ifmt_jmp, { 0x40 }
+ },
+/* jmpf $abs24 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (ABS24), 0 } },
+ & ifmt_jmpf, { 0x2000000 }
+ },
+/* callr $Rd */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), 0 } },
+ & ifmt_movlowgr, { 0x10 }
+ },
+/* callr $rel12a */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (REL12A), 0 } },
+ & ifmt_br, { 0x1001 }
+ },
+/* call $Rbj,$Rd */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RBJ), ',', OP (RD), 0 } },
+ & ifmt_jmp, { 0xa0 }
+ },
+/* callf $abs24 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (ABS24), 0 } },
+ & ifmt_jmpf, { 0x1000000 }
+ },
+/* icallr $Rd */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), 0 } },
+ & ifmt_movlowgr, { 0x30 }
+ },
+/* icall $Rbj,$Rd */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RBJ), ',', OP (RD), 0 } },
+ & ifmt_jmp, { 0x60 }
+ },
+/* icallf $abs24 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (ABS24), 0 } },
+ & ifmt_jmpf, { 0x3000000 }
+ },
+/* iret */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, 0 } },
+ & ifmt_iret, { 0x2 }
+ },
+/* ret */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, 0 } },
+ & ifmt_iret, { 0x3 }
+ },
+/* mul */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, 0 } },
+ & ifmt_iret, { 0xd0 }
+ },
+/* div */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, 0 } },
+ & ifmt_iret, { 0xc0 }
+ },
+/* nop */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, 0 } },
+ & ifmt_iret, { 0x0 }
+ },
+/* halt */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, 0 } },
+ & ifmt_iret, { 0x8 }
+ },
+/* hold */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, 0 } },
+ & ifmt_iret, { 0xa }
+ },
+/* brk */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, 0 } },
+ & ifmt_iret, { 0x5 }
+ },
+/* --unused-- */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, 0 } },
+ & ifmt_iret, { 0x1 }
+ },
+};
+
+#undef A
+#undef OPERAND
+#undef MNEM
+#undef OP
+
+/* Formats for ALIAS macro-insns. */
+
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define F(f) & xstormy16_cgen_ifld_table[XSTORMY16_##f]
+#else
+#define F(f) & xstormy16_cgen_ifld_table[XSTORMY16_/**/f]
+#endif
+static const CGEN_IFMT ifmt_movimm8 = {
+ 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_IMM8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movgrimm8 = {
+ 16, 16, 0xf100, { { F (F_OP1) }, { F (F_RM) }, { F (F_OP2M) }, { F (F_IMM8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movgrimm16 = {
+ 32, 32, 0xfff00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_OP3) }, { F (F_RD) }, { F (F_IMM16) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_incgr = {
+ 16, 16, 0xfff0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_OP3A) }, { F (F_IMM2) }, { F (F_RD) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_decgr = {
+ 16, 16, 0xfff0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_OP3A) }, { F (F_IMM2) }, { F (F_RD) }, { 0 } }
+};
+
+#undef F
+
+/* Each non-simple macro entry points to an array of expansion possibilities. */
+
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define A(a) (1 << CGEN_INSN_##a)
+#else
+#define A(a) (1 << CGEN_INSN_/**/a)
+#endif
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define OPERAND(op) XSTORMY16_OPERAND_##op
+#else
+#define OPERAND(op) XSTORMY16_OPERAND_/**/op
+#endif
+#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
+#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
+
+/* The macro instruction table. */
+
+static const CGEN_IBASE xstormy16_cgen_macro_insn_table[] =
+{
+/* mov Rx,#$imm8 */
+ {
+ -1, "movimm8", "mov", 16,
+ { 0|A(ALIAS), { (1<<MACH_BASE) } }
+ },
+/* mov $Rm,#$imm8small */
+ {
+ -1, "movgrimm8", "mov", 16,
+ { 0|A(ALIAS), { (1<<MACH_BASE) } }
+ },
+/* mov $Rd,#$imm16 */
+ {
+ -1, "movgrimm16", "mov", 32,
+ { 0|A(ALIAS), { (1<<MACH_BASE) } }
+ },
+/* inc $Rd */
+ {
+ -1, "incgr", "inc", 16,
+ { 0|A(ALIAS), { (1<<MACH_BASE) } }
+ },
+/* dec $Rd */
+ {
+ -1, "decgr", "dec", 16,
+ { 0|A(ALIAS), { (1<<MACH_BASE) } }
+ },
+};
+
+/* The macro instruction opcode table. */
+
+static const CGEN_OPCODE xstormy16_cgen_macro_insn_opcode_table[] =
+{
+/* mov Rx,#$imm8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', 'R', 'x', ',', '#', OP (IMM8), 0 } },
+ & ifmt_movimm8, { 0x4700 }
+ },
+/* mov $Rm,#$imm8small */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RM), ',', '#', OP (IMM8SMALL), 0 } },
+ & ifmt_movgrimm8, { 0x2100 }
+ },
+/* mov $Rd,#$imm16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), ',', '#', OP (IMM16), 0 } },
+ & ifmt_movgrimm16, { 0x31300000 }
+ },
+/* inc $Rd */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), 0 } },
+ & ifmt_incgr, { 0x3000 }
+ },
+/* dec $Rd */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RD), 0 } },
+ & ifmt_decgr, { 0x3040 }
+ },
+};
+
+#undef A
+#undef OPERAND
+#undef MNEM
+#undef OP
+
+#ifndef CGEN_ASM_HASH_P
+#define CGEN_ASM_HASH_P(insn) 1
+#endif
+
+#ifndef CGEN_DIS_HASH_P
+#define CGEN_DIS_HASH_P(insn) 1
+#endif
+
+/* Return non-zero if INSN is to be added to the hash table.
+ Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */
+
+static int
+asm_hash_insn_p (insn)
+ const CGEN_INSN *insn ATTRIBUTE_UNUSED;
+{
+ return CGEN_ASM_HASH_P (insn);
+}
+
+static int
+dis_hash_insn_p (insn)
+ const CGEN_INSN *insn;
+{
+ /* If building the hash table and the NO-DIS attribute is present,
+ ignore. */
+ if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_NO_DIS))
+ return 0;
+ return CGEN_DIS_HASH_P (insn);
+}
+
+#ifndef CGEN_ASM_HASH
+#define CGEN_ASM_HASH_SIZE 127
+#ifdef CGEN_MNEMONIC_OPERANDS
+#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE)
+#else
+#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) /*FIXME*/
+#endif
+#endif
+
+/* It doesn't make much sense to provide a default here,
+ but while this is under development we do.
+ BUFFER is a pointer to the bytes of the insn, target order.
+ VALUE is the first base_insn_bitsize bits as an int in host order. */
+
+#ifndef CGEN_DIS_HASH
+#define CGEN_DIS_HASH_SIZE 256
+#define CGEN_DIS_HASH(buf, value) (*(unsigned char *) (buf))
+#endif
+
+/* The result is the hash value of the insn.
+ Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */
+
+static unsigned int
+asm_hash_insn (mnem)
+ const char * mnem;
+{
+ return CGEN_ASM_HASH (mnem);
+}
+
+/* BUF is a pointer to the bytes of the insn, target order.
+ VALUE is the first base_insn_bitsize bits as an int in host order. */
+
+static unsigned int
+dis_hash_insn (buf, value)
+ const char * buf ATTRIBUTE_UNUSED;
+ CGEN_INSN_INT value ATTRIBUTE_UNUSED;
+{
+ return CGEN_DIS_HASH (buf, value);
+}
+
+static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int));
+
+/* Set the recorded length of the insn in the CGEN_FIELDS struct. */
+
+static void
+set_fields_bitsize (fields, size)
+ CGEN_FIELDS *fields;
+ int size;
+{
+ CGEN_FIELDS_BITSIZE (fields) = size;
+}
+
+/* Function to call before using the operand instance table.
+ This plugs the opcode entries and macro instructions into the cpu table. */
+
+void
+xstormy16_cgen_init_opcode_table (cd)
+ CGEN_CPU_DESC cd;
+{
+ int i;
+ int num_macros = (sizeof (xstormy16_cgen_macro_insn_table) /
+ sizeof (xstormy16_cgen_macro_insn_table[0]));
+ const CGEN_IBASE *ib = & xstormy16_cgen_macro_insn_table[0];
+ const CGEN_OPCODE *oc = & xstormy16_cgen_macro_insn_opcode_table[0];
+ CGEN_INSN *insns = (CGEN_INSN *) xmalloc (num_macros * sizeof (CGEN_INSN));
+ memset (insns, 0, num_macros * sizeof (CGEN_INSN));
+ for (i = 0; i < num_macros; ++i)
+ {
+ insns[i].base = &ib[i];
+ insns[i].opcode = &oc[i];
+ xstormy16_cgen_build_insn_regex (& insns[i]);
+ }
+ cd->macro_insn_table.init_entries = insns;
+ cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE);
+ cd->macro_insn_table.num_init_entries = num_macros;
+
+ oc = & xstormy16_cgen_insn_opcode_table[0];
+ insns = (CGEN_INSN *) cd->insn_table.init_entries;
+ for (i = 0; i < MAX_INSNS; ++i)
+ {
+ insns[i].opcode = &oc[i];
+ xstormy16_cgen_build_insn_regex (& insns[i]);
+ }
+
+ cd->sizeof_fields = sizeof (CGEN_FIELDS);
+ cd->set_fields_bitsize = set_fields_bitsize;
+
+ cd->asm_hash_p = asm_hash_insn_p;
+ cd->asm_hash = asm_hash_insn;
+ cd->asm_hash_size = CGEN_ASM_HASH_SIZE;
+
+ cd->dis_hash_p = dis_hash_insn_p;
+ cd->dis_hash = dis_hash_insn;
+ cd->dis_hash_size = CGEN_DIS_HASH_SIZE;
+}
diff --git a/opcodes/xstormy16-opc.h b/opcodes/xstormy16-opc.h
new file mode 100644
index 0000000..551d266
--- /dev/null
+++ b/opcodes/xstormy16-opc.h
@@ -0,0 +1,136 @@
+/* Instruction opcode header for xstormy16.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifndef XSTORMY16_OPC_H
+#define XSTORMY16_OPC_H
+
+/* -- opc.h */
+
+/* Allows reason codes to be output when assembler errors occur. */
+#define CGEN_VERBOSE_ASSEMBLER_ERRORS
+
+/* We can't use the default hash size because many bits are used by
+ operands. */
+#define CGEN_DIS_HASH_SIZE 1
+#define CGEN_DIS_HASH(buf, value) 0
+/* -- */
+/* Enum declaration for xstormy16 instruction types. */
+typedef enum cgen_insn_type {
+ XSTORMY16_INSN_INVALID, XSTORMY16_INSN_MOVLMEMIMM, XSTORMY16_INSN_MOVHMEMIMM, XSTORMY16_INSN_MOVLGRMEM
+ , XSTORMY16_INSN_MOVHGRMEM, XSTORMY16_INSN_MOVLMEMGR, XSTORMY16_INSN_MOVHMEMGR, XSTORMY16_INSN_MOVGRGRI
+ , XSTORMY16_INSN_MOVGRGRIPOSTINC, XSTORMY16_INSN_MOVGRGRIPREDEC, XSTORMY16_INSN_MOVGRIGR, XSTORMY16_INSN_MOVGRIPOSTINCGR
+ , XSTORMY16_INSN_MOVGRIPREDECGR, XSTORMY16_INSN_MOVGRGRII, XSTORMY16_INSN_MOVGRGRIIPOSTINC, XSTORMY16_INSN_MOVGRGRIIPREDEC
+ , XSTORMY16_INSN_MOVGRIIGR, XSTORMY16_INSN_MOVGRIIPOSTINCGR, XSTORMY16_INSN_MOVGRIIPREDECGR, XSTORMY16_INSN_MOVGRGR
+ , XSTORMY16_INSN_MOVWIMM8, XSTORMY16_INSN_MOVWGRIMM8, XSTORMY16_INSN_MOVWGRIMM16, XSTORMY16_INSN_MOVLOWGR
+ , XSTORMY16_INSN_MOVHIGHGR, XSTORMY16_INSN_MOVFGRGRI, XSTORMY16_INSN_MOVFGRGRIPOSTINC, XSTORMY16_INSN_MOVFGRGRIPREDEC
+ , XSTORMY16_INSN_MOVFGRIGR, XSTORMY16_INSN_MOVFGRIPOSTINCGR, XSTORMY16_INSN_MOVFGRIPREDECGR, XSTORMY16_INSN_MOVFGRGRII
+ , XSTORMY16_INSN_MOVFGRGRIIPOSTINC, XSTORMY16_INSN_MOVFGRGRIIPREDEC, XSTORMY16_INSN_MOVFGRIIGR, XSTORMY16_INSN_MOVFGRIIPOSTINCGR
+ , XSTORMY16_INSN_MOVFGRIIPREDECGR, XSTORMY16_INSN_MASKGRGR, XSTORMY16_INSN_MASKGRIMM16, XSTORMY16_INSN_PUSHGR
+ , XSTORMY16_INSN_POPGR, XSTORMY16_INSN_SWPN, XSTORMY16_INSN_SWPB, XSTORMY16_INSN_SWPW
+ , XSTORMY16_INSN_ANDGRGR, XSTORMY16_INSN_ANDIMM8, XSTORMY16_INSN_ANDGRIMM16, XSTORMY16_INSN_ORGRGR
+ , XSTORMY16_INSN_ORIMM8, XSTORMY16_INSN_ORGRIMM16, XSTORMY16_INSN_XORGRGR, XSTORMY16_INSN_XORIMM8
+ , XSTORMY16_INSN_XORGRIMM16, XSTORMY16_INSN_NOTGR, XSTORMY16_INSN_ADDGRGR, XSTORMY16_INSN_ADDGRIMM4
+ , XSTORMY16_INSN_ADDIMM8, XSTORMY16_INSN_ADDGRIMM16, XSTORMY16_INSN_ADCGRGR, XSTORMY16_INSN_ADCGRIMM4
+ , XSTORMY16_INSN_ADCIMM8, XSTORMY16_INSN_ADCGRIMM16, XSTORMY16_INSN_SUBGRGR, XSTORMY16_INSN_SUBGRIMM4
+ , XSTORMY16_INSN_SUBIMM8, XSTORMY16_INSN_SUBGRIMM16, XSTORMY16_INSN_SBCGRGR, XSTORMY16_INSN_SBCGRIMM4
+ , XSTORMY16_INSN_SBCGRIMM8, XSTORMY16_INSN_SBCGRIMM16, XSTORMY16_INSN_INCGRIMM2, XSTORMY16_INSN_DECGRIMM2
+ , XSTORMY16_INSN_RRCGRGR, XSTORMY16_INSN_RRCGRIMM4, XSTORMY16_INSN_RLCGRGR, XSTORMY16_INSN_RLCGRIMM4
+ , XSTORMY16_INSN_SHRGRGR, XSTORMY16_INSN_SHRGRIMM, XSTORMY16_INSN_SHLGRGR, XSTORMY16_INSN_SHLGRIMM
+ , XSTORMY16_INSN_ASRGRGR, XSTORMY16_INSN_ASRGRIMM, XSTORMY16_INSN_SET1GRIMM, XSTORMY16_INSN_SET1GRGR
+ , XSTORMY16_INSN_SET1LMEMIMM, XSTORMY16_INSN_SET1HMEMIMM, XSTORMY16_INSN_CLR1GRIMM, XSTORMY16_INSN_CLR1GRGR
+ , XSTORMY16_INSN_CLR1LMEMIMM, XSTORMY16_INSN_CLR1HMEMIMM, XSTORMY16_INSN_CBWGR, XSTORMY16_INSN_REVGR
+ , XSTORMY16_INSN_BCCGRGR, XSTORMY16_INSN_BCCGRIMM8, XSTORMY16_INSN_BCCIMM16, XSTORMY16_INSN_BNGRIMM4
+ , XSTORMY16_INSN_BNGRGR, XSTORMY16_INSN_BNLMEMIMM, XSTORMY16_INSN_BNHMEMIMM, XSTORMY16_INSN_BPGRIMM4
+ , XSTORMY16_INSN_BPGRGR, XSTORMY16_INSN_BPLMEMIMM, XSTORMY16_INSN_BPHMEMIMM, XSTORMY16_INSN_BCC
+ , XSTORMY16_INSN_BGR, XSTORMY16_INSN_BR, XSTORMY16_INSN_JMP, XSTORMY16_INSN_JMPF
+ , XSTORMY16_INSN_CALLRGR, XSTORMY16_INSN_CALLRIMM, XSTORMY16_INSN_CALLGR, XSTORMY16_INSN_CALLFIMM
+ , XSTORMY16_INSN_ICALLRGR, XSTORMY16_INSN_ICALLGR, XSTORMY16_INSN_ICALLFIMM, XSTORMY16_INSN_IRET
+ , XSTORMY16_INSN_RET, XSTORMY16_INSN_MUL, XSTORMY16_INSN_DIV, XSTORMY16_INSN_NOP
+ , XSTORMY16_INSN_HALT, XSTORMY16_INSN_HOLD, XSTORMY16_INSN_BRK, XSTORMY16_INSN_SYSCALL
+} CGEN_INSN_TYPE;
+
+/* Index of `invalid' insn place holder. */
+#define CGEN_INSN_INVALID XSTORMY16_INSN_INVALID
+
+/* Total number of insns in table. */
+#define MAX_INSNS ((int) XSTORMY16_INSN_SYSCALL + 1)
+
+/* This struct records data prior to insertion or after extraction. */
+struct cgen_fields
+{
+ int length;
+ long f_nil;
+ long f_anyof;
+ long f_Rd;
+ long f_Rdm;
+ long f_Rm;
+ long f_Rs;
+ long f_Rb;
+ long f_Rbj;
+ long f_op1;
+ long f_op2;
+ long f_op2a;
+ long f_op2m;
+ long f_op3;
+ long f_op3a;
+ long f_op3b;
+ long f_op4;
+ long f_op4m;
+ long f_op4b;
+ long f_op5;
+ long f_op5a;
+ long f_op;
+ long f_imm2;
+ long f_imm3;
+ long f_imm3b;
+ long f_imm4;
+ long f_imm8;
+ long f_imm12;
+ long f_imm16;
+ long f_lmem8;
+ long f_hmem8;
+ long f_rel8_2;
+ long f_rel8_4;
+ long f_rel12;
+ long f_rel12a;
+ long f_abs24_1;
+ long f_abs24_2;
+ long f_abs24;
+};
+
+#define CGEN_INIT_PARSE(od) \
+{\
+}
+#define CGEN_INIT_INSERT(od) \
+{\
+}
+#define CGEN_INIT_EXTRACT(od) \
+{\
+}
+#define CGEN_INIT_PRINT(od) \
+{\
+}
+
+
+#endif /* XSTORMY16_OPC_H */
generated by cgit v1.1 at 2024-11-23 01:09:15 +0000