binutils/

2008-08-01  H.J. Lu  <hongjiu.lu@intel.com>

	* dwarf.c (dwarf_regnames_i386): Remove AVX registers.
	(dwarf_regnames_x86_64): Likewise.

gas/testsuite/

2008-08-01  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/cfi/cfi-i386.s: Remove tests for AVX register maps.
	* gas/cfi/cfi-x86_64.s: Likewise.

	* gas/cfi/cfi-i386.d: Updated.
	* gas/cfi/cfi-x86_64.d: Likewise.

opcodes/

2008-08-01  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-reg.tbl: Use Dw2Inval on AVX registers.
	* i386-tbl.h: Regenerated.

3 files changed, 37 insertions, 32 deletions

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 4b73185..22d20b3 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2008-08-01  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* i386-reg.tbl: Use Dw2Inval on AVX registers.
+	* i386-tbl.h: Regenerated.
+
 2008-07-30  Michael J. Eager  <eager@eagercon.com>
 
 	* ppc-dis.c (print_insn_powerpc): Disassemble FSL/FCR/UDI fields.
diff --git a/opcodes/i386-reg.tbl b/opcodes/i386-reg.tbl
index c88a9e0..d1885e1 100644
--- a/opcodes/i386-reg.tbl
+++ b/opcodes/i386-reg.tbl
@@ -189,22 +189,22 @@ xmm13, RegXMM, RegRex, 5, Dw2Inval, 30
 xmm14, RegXMM, RegRex, 6, Dw2Inval, 31
 xmm15, RegXMM, RegRex, 7, Dw2Inval, 32
 // AVX registers.
-ymm0, RegYMM, 0, 0, 53, 70
-ymm1, RegYMM, 0, 1, 54, 71
-ymm2, RegYMM, 0, 2, 55, 72
-ymm3, RegYMM, 0, 3, 56, 73
-ymm4, RegYMM, 0, 4, 57, 74
-ymm5, RegYMM, 0, 5, 58, 75
-ymm6, RegYMM, 0, 6, 59, 76
-ymm7, RegYMM, 0, 7, 60, 77
-ymm8, RegYMM, RegRex, 0, Dw2Inval, 78
-ymm9, RegYMM, RegRex, 1, Dw2Inval, 79
-ymm10, RegYMM, RegRex, 2, Dw2Inval, 80
-ymm11, RegYMM, RegRex, 3, Dw2Inval, 81
-ymm12, RegYMM, RegRex, 4, Dw2Inval, 82
-ymm13, RegYMM, RegRex, 5, Dw2Inval, 83
-ymm14, RegYMM, RegRex, 6, Dw2Inval, 84
-ymm15, RegYMM, RegRex, 7, Dw2Inval, 85
+ymm0, RegYMM, 0, 0, Dw2Inval, Dw2Inval
+ymm1, RegYMM, 0, 1, Dw2Inval, Dw2Inval
+ymm2, RegYMM, 0, 2, Dw2Inval, Dw2Inval
+ymm3, RegYMM, 0, 3, Dw2Inval, Dw2Inval
+ymm4, RegYMM, 0, 4, Dw2Inval, Dw2Inval
+ymm5, RegYMM, 0, 5, Dw2Inval, Dw2Inval
+ymm6, RegYMM, 0, 6, Dw2Inval, Dw2Inval
+ymm7, RegYMM, 0, 7, Dw2Inval, Dw2Inval
+ymm8, RegYMM, RegRex, 0, Dw2Inval, Dw2Inval
+ymm9, RegYMM, RegRex, 1, Dw2Inval, Dw2Inval
+ymm10, RegYMM, RegRex, 2, Dw2Inval, Dw2Inval
+ymm11, RegYMM, RegRex, 3, Dw2Inval, Dw2Inval
+ymm12, RegYMM, RegRex, 4, Dw2Inval, Dw2Inval
+ymm13, RegYMM, RegRex, 5, Dw2Inval, Dw2Inval
+ymm14, RegYMM, RegRex, 6, Dw2Inval, Dw2Inval
+ymm15, RegYMM, RegRex, 7, Dw2Inval, Dw2Inval
 // No type will make these registers rejected for all purposes except
 // for addressing.  This saves creating one extra type for RIP/EIP.
 rip, BaseIndex, RegRex64, RegRip, Dw2Inval, 16
diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index ad1e331..6f0b165 100644
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -31840,82 +31840,82 @@ const reg_entry i386_regtab[] =
     { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	0, 0, 0, 0, 0, 0 } },
-    0, 0, { 53, 70 } },
+    0, 0, { Dw2Inval, Dw2Inval } },
   { "ymm1",
     { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	0, 0, 0, 0, 0, 0 } },
-    0, 1, { 54, 71 } },
+    0, 1, { Dw2Inval, Dw2Inval } },
   { "ymm2",
     { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	0, 0, 0, 0, 0, 0 } },
-    0, 2, { 55, 72 } },
+    0, 2, { Dw2Inval, Dw2Inval } },
   { "ymm3",
     { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	0, 0, 0, 0, 0, 0 } },
-    0, 3, { 56, 73 } },
+    0, 3, { Dw2Inval, Dw2Inval } },
   { "ymm4",
     { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	0, 0, 0, 0, 0, 0 } },
-    0, 4, { 57, 74 } },
+    0, 4, { Dw2Inval, Dw2Inval } },
   { "ymm5",
     { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	0, 0, 0, 0, 0, 0 } },
-    0, 5, { 58, 75 } },
+    0, 5, { Dw2Inval, Dw2Inval } },
   { "ymm6",
     { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	0, 0, 0, 0, 0, 0 } },
-    0, 6, { 59, 76 } },
+    0, 6, { Dw2Inval, Dw2Inval } },
   { "ymm7",
     { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	0, 0, 0, 0, 0, 0 } },
-    0, 7, { 60, 77 } },
+    0, 7, { Dw2Inval, Dw2Inval } },
   { "ymm8",
     { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	0, 0, 0, 0, 0, 0 } },
-    RegRex, 0, { Dw2Inval, 78 } },
+    RegRex, 0, { Dw2Inval, Dw2Inval } },
   { "ymm9",
     { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	0, 0, 0, 0, 0, 0 } },
-    RegRex, 1, { Dw2Inval, 79 } },
+    RegRex, 1, { Dw2Inval, Dw2Inval } },
   { "ymm10",
     { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	0, 0, 0, 0, 0, 0 } },
-    RegRex, 2, { Dw2Inval, 80 } },
+    RegRex, 2, { Dw2Inval, Dw2Inval } },
   { "ymm11",
     { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	0, 0, 0, 0, 0, 0 } },
-    RegRex, 3, { Dw2Inval, 81 } },
+    RegRex, 3, { Dw2Inval, Dw2Inval } },
   { "ymm12",
     { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	0, 0, 0, 0, 0, 0 } },
-    RegRex, 4, { Dw2Inval, 82 } },
+    RegRex, 4, { Dw2Inval, Dw2Inval } },
   { "ymm13",
     { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	0, 0, 0, 0, 0, 0 } },
-    RegRex, 5, { Dw2Inval, 83 } },
+    RegRex, 5, { Dw2Inval, Dw2Inval } },
   { "ymm14",
     { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	0, 0, 0, 0, 0, 0 } },
-    RegRex, 6, { Dw2Inval, 84 } },
+    RegRex, 6, { Dw2Inval, Dw2Inval } },
   { "ymm15",
     { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	0, 0, 0, 0, 0, 0 } },
-    RegRex, 7, { Dw2Inval, 85 } },
+    RegRex, 7, { Dw2Inval, Dw2Inval } },
   { "rip",
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,