diff options
author | Jan Beulich <jbeulich@novell.com> | 2008-02-13 10:14:40 +0000 |
---|---|---|
committer | Jan Beulich <jbeulich@novell.com> | 2008-02-13 10:14:40 +0000 |
commit | a60de03c6170ebd45927e318164e2306028df86d (patch) | |
tree | 1ffc652acac063787cee604d31310ea6542f0600 /opcodes | |
parent | 36af4ef67677fb266a52888d48fd85d7f889c050 (diff) | |
download | gdb-a60de03c6170ebd45927e318164e2306028df86d.zip gdb-a60de03c6170ebd45927e318164e2306028df86d.tar.gz gdb-a60de03c6170ebd45927e318164e2306028df86d.tar.bz2 |
gas/
2008-02-13 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.c (allow_pseudo_reg): New.
(parse_real_register): Check for NULL just once. Allow all
register table entries when allow_pseudo_reg is non-zero.
Don't allow any registers without type when allow_pseudo_reg
is zero.
(tc_x86_regname_to_dw2regnum): Replace with ...
(tc_x86_parse_to_dw2regnum): ... this.
(tc_x86_frame_initial_instructions): Adjust for above change.
* config/tc-i386.h (tc_regname_to_dw2regnum): Remove.
(tc_parse_to_dw2regnum): New.
(tc_x86_regname_to_dw2regnum): Replace with ...
(tc_x86_parse_to_dw2regnum): ... this.
* dw2gencfi.c (tc_parse_to_dw2regnum): New, broken out of ...
(cfi_parse_reg): ... this. Use tc_parse_to_dw2regnum. Adjust
error handling.
gas/testsuite/
2008-02-13 Jan Beulich <jbeulich@novell.com>
* gas/cfi/cfi-i386.s: Add code testing use of all registers.
Fix a few comments.
* gas/cfi/cfi-x86_64.s: Likewise.
* gas/cfi/cfi-i386.d, gas/cfi/cfi-x86_64.d: Adjust.
opcodes/
2008-02-13 Jan Beulich <jbeulich@novell.com>
* i386-gen.c (process_i386_registers): Process new fields.
* i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
unsigned char. Add dw2_regnum and Dw2Inval.
* i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
register names.
* i386-tbl.h: Re-generate.
Diffstat (limited to 'opcodes')
-rw-r--r-- | opcodes/ChangeLog | 9 | ||||
-rw-r--r-- | opcodes/i386-gen.c | 16 | ||||
-rw-r--r-- | opcodes/i386-opc.h | 8 | ||||
-rw-r--r-- | opcodes/i386-reg.tbl | 361 | ||||
-rw-r--r-- | opcodes/i386-tbl.h | 427 |
5 files changed, 475 insertions, 346 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 8feb654..233ceab 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,12 @@ +2008-02-13 Jan Beulich <jbeulich@novell.com> + + * i386-gen.c (process_i386_registers): Process new fields. + * i386-opc.h (reg_entry): Shrink reg_flags and reg_num to + unsigned char. Add dw2_regnum and Dw2Inval. + * i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo + register names. + * i386-tbl.h: Re-generate. + 2008-02-11 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS. diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index 269759b..04413dc 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -802,6 +802,7 @@ process_i386_registers (FILE *table) char buf[2048]; char *str, *p, *last; char *reg_name, *reg_type, *reg_flags, *reg_num; + char *dw2_32_num, *dw2_64_num; filename = "i386-reg.tbl"; fp = fopen (filename, "r"); @@ -863,11 +864,24 @@ process_i386_registers (FILE *table) /* Find reg_num. */ reg_num = next_field (str, ',', &str); + if (str >= last) + abort (); + fprintf (table, " { \"%s\",\n ", reg_name); process_i386_operand_type (table, reg_type, 0, "\t"); - fprintf (table, ",\n %s, %s },\n", reg_flags, reg_num); + /* Find 32-bit Dwarf2 register number. */ + dw2_32_num = next_field (str, ',', &str); + + if (str >= last) + abort (); + + /* Find 64-bit Dwarf2 register number. */ + dw2_64_num = next_field (str, ',', &str); + + fprintf (table, ",\n %s, %s, { %s, %s } },\n", + reg_flags, reg_num, dw2_32_num, dw2_64_num); } fclose (fp); diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index bbf2ff8..95c315b 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -492,15 +492,17 @@ typedef struct { char *reg_name; i386_operand_type reg_type; - unsigned int reg_flags; + unsigned char reg_flags; #define RegRex 0x1 /* Extended register. */ #define RegRex64 0x2 /* Extended 8 bit register. */ - unsigned int reg_num; -#define RegRip ((unsigned int ) ~0) + unsigned char reg_num; +#define RegRip ((unsigned char ) ~0) #define RegEip (RegRip - 1) /* EIZ and RIZ are fake index registers. */ #define RegEiz (RegEip - 1) #define RegRiz (RegEiz - 1) + signed char dw2_regnum[2]; +#define Dw2Inval (-1) } reg_entry; diff --git a/opcodes/i386-reg.tbl b/opcodes/i386-reg.tbl index bdb7e35..11f2ee7 100644 --- a/opcodes/i386-reg.tbl +++ b/opcodes/i386-reg.tbl @@ -20,187 +20,206 @@ // 02110-1301, USA. // Make %st first as we test for it. -st, FloatReg|FloatAcc, 0, 0 +st, FloatReg|FloatAcc, 0, 0, 11, 33 // 8 bit regs -al, Reg8|Acc|Byte, 0, 0 -cl, Reg8|ShiftCount, 0, 1 -dl, Reg8, 0, 2 -bl, Reg8, 0, 3 -ah, Reg8, 0, 4 -ch, Reg8, 0, 5 -dh, Reg8, 0, 6 -bh, Reg8, 0, 7 -axl, Reg8|Acc|Byte, RegRex64, 0 -cxl, Reg8, RegRex64, 1 -dxl, Reg8, RegRex64, 2 -bxl, Reg8, RegRex64, 3 -spl, Reg8, RegRex64, 4 -bpl, Reg8, RegRex64, 5 -sil, Reg8, RegRex64, 6 -dil, Reg8, RegRex64, 7 -r8b, Reg8, RegRex|RegRex64, 0 -r9b, Reg8, RegRex|RegRex64, 1 -r10b, Reg8, RegRex|RegRex64, 2 -r11b, Reg8, RegRex|RegRex64, 3 -r12b, Reg8, RegRex|RegRex64, 4 -r13b, Reg8, RegRex|RegRex64, 5 -r14b, Reg8, RegRex|RegRex64, 6 -r15b, Reg8, RegRex|RegRex64, 7 +al, Reg8|Acc|Byte, 0, 0, Dw2Inval, Dw2Inval +cl, Reg8|ShiftCount, 0, 1, Dw2Inval, Dw2Inval +dl, Reg8, 0, 2, Dw2Inval, Dw2Inval +bl, Reg8, 0, 3, Dw2Inval, Dw2Inval +ah, Reg8, 0, 4, Dw2Inval, Dw2Inval +ch, Reg8, 0, 5, Dw2Inval, Dw2Inval +dh, Reg8, 0, 6, Dw2Inval, Dw2Inval +bh, Reg8, 0, 7, Dw2Inval, Dw2Inval +axl, Reg8|Acc|Byte, RegRex64, 0, Dw2Inval, Dw2Inval +cxl, Reg8, RegRex64, 1, Dw2Inval, Dw2Inval +dxl, Reg8, RegRex64, 2, Dw2Inval, Dw2Inval +bxl, Reg8, RegRex64, 3, Dw2Inval, Dw2Inval +spl, Reg8, RegRex64, 4, Dw2Inval, Dw2Inval +bpl, Reg8, RegRex64, 5, Dw2Inval, Dw2Inval +sil, Reg8, RegRex64, 6, Dw2Inval, Dw2Inval +dil, Reg8, RegRex64, 7, Dw2Inval, Dw2Inval +r8b, Reg8, RegRex|RegRex64, 0, Dw2Inval, Dw2Inval +r9b, Reg8, RegRex|RegRex64, 1, Dw2Inval, Dw2Inval +r10b, Reg8, RegRex|RegRex64, 2, Dw2Inval, Dw2Inval +r11b, Reg8, RegRex|RegRex64, 3, Dw2Inval, Dw2Inval +r12b, Reg8, RegRex|RegRex64, 4, Dw2Inval, Dw2Inval +r13b, Reg8, RegRex|RegRex64, 5, Dw2Inval, Dw2Inval +r14b, Reg8, RegRex|RegRex64, 6, Dw2Inval, Dw2Inval +r15b, Reg8, RegRex|RegRex64, 7, Dw2Inval, Dw2Inval // 16 bit regs -ax, Reg16|Acc|Word, 0, 0 -cx, Reg16, 0, 1 -dx, Reg16|InOutPortReg, 0, 2 -bx, Reg16|BaseIndex, 0, 3 -sp, Reg16, 0, 4 -bp, Reg16|BaseIndex, 0, 5 -si, Reg16|BaseIndex, 0, 6 -di, Reg16|BaseIndex, 0, 7 -r8w, Reg16, RegRex, 0 -r9w, Reg16, RegRex, 1 -r10w, Reg16, RegRex, 2 -r11w, Reg16, RegRex, 3 -r12w, Reg16, RegRex, 4 -r13w, Reg16, RegRex, 5 -r14w, Reg16, RegRex, 6 -r15w, Reg16, RegRex, 7 +ax, Reg16|Acc|Word, 0, 0, Dw2Inval, Dw2Inval +cx, Reg16, 0, 1, Dw2Inval, Dw2Inval +dx, Reg16|InOutPortReg, 0, 2, Dw2Inval, Dw2Inval +bx, Reg16|BaseIndex, 0, 3, Dw2Inval, Dw2Inval +sp, Reg16, 0, 4, Dw2Inval, Dw2Inval +bp, Reg16|BaseIndex, 0, 5, Dw2Inval, Dw2Inval +si, Reg16|BaseIndex, 0, 6, Dw2Inval, Dw2Inval +di, Reg16|BaseIndex, 0, 7, Dw2Inval, Dw2Inval +r8w, Reg16, RegRex, 0, Dw2Inval, Dw2Inval +r9w, Reg16, RegRex, 1, Dw2Inval, Dw2Inval +r10w, Reg16, RegRex, 2, Dw2Inval, Dw2Inval +r11w, Reg16, RegRex, 3, Dw2Inval, Dw2Inval +r12w, Reg16, RegRex, 4, Dw2Inval, Dw2Inval +r13w, Reg16, RegRex, 5, Dw2Inval, Dw2Inval +r14w, Reg16, RegRex, 6, Dw2Inval, Dw2Inval +r15w, Reg16, RegRex, 7, Dw2Inval, Dw2Inval // 32 bit regs -eax, Reg32|BaseIndex|Acc|Dword, 0, 0 -ecx, Reg32|BaseIndex, 0, 1 -edx, Reg32|BaseIndex, 0, 2 -ebx, Reg32|BaseIndex, 0, 3 -esp, Reg32, 0, 4 -ebp, Reg32|BaseIndex, 0, 5 -esi, Reg32|BaseIndex, 0, 6 -edi, Reg32|BaseIndex, 0, 7 -r8d, Reg32|BaseIndex, RegRex, 0 -r9d, Reg32|BaseIndex, RegRex, 1 -r10d, Reg32|BaseIndex, RegRex, 2 -r11d, Reg32|BaseIndex, RegRex, 3 -r12d, Reg32|BaseIndex, RegRex, 4 -r13d, Reg32|BaseIndex, RegRex, 5 -r14d, Reg32|BaseIndex, RegRex, 6 -r15d, Reg32|BaseIndex, RegRex, 7 -rax, Reg64|BaseIndex|Acc|Qword, 0, 0 -rcx, Reg64|BaseIndex, 0, 1 -rdx, Reg64|BaseIndex, 0, 2 -rbx, Reg64|BaseIndex, 0, 3 -rsp, Reg64, 0, 4 -rbp, Reg64|BaseIndex, 0, 5 -rsi, Reg64|BaseIndex, 0, 6 -rdi, Reg64|BaseIndex, 0, 7 -r8, Reg64|BaseIndex, RegRex, 0 -r9, Reg64|BaseIndex, RegRex, 1 -r10, Reg64|BaseIndex, RegRex, 2 -r11, Reg64|BaseIndex, RegRex, 3 -r12, Reg64|BaseIndex, RegRex, 4 -r13, Reg64|BaseIndex, RegRex, 5 -r14, Reg64|BaseIndex, RegRex, 6 -r15, Reg64|BaseIndex, RegRex, 7 +eax, Reg32|BaseIndex|Acc|Dword, 0, 0, 0, Dw2Inval +ecx, Reg32|BaseIndex, 0, 1, 1, Dw2Inval +edx, Reg32|BaseIndex, 0, 2, 2, Dw2Inval +ebx, Reg32|BaseIndex, 0, 3, 3, Dw2Inval +esp, Reg32, 0, 4, 4, Dw2Inval +ebp, Reg32|BaseIndex, 0, 5, 5, Dw2Inval +esi, Reg32|BaseIndex, 0, 6, 6, Dw2Inval +edi, Reg32|BaseIndex, 0, 7, 7, Dw2Inval +r8d, Reg32|BaseIndex, RegRex, 0, Dw2Inval, Dw2Inval +r9d, Reg32|BaseIndex, RegRex, 1, Dw2Inval, Dw2Inval +r10d, Reg32|BaseIndex, RegRex, 2, Dw2Inval, Dw2Inval +r11d, Reg32|BaseIndex, RegRex, 3, Dw2Inval, Dw2Inval +r12d, Reg32|BaseIndex, RegRex, 4, Dw2Inval, Dw2Inval +r13d, Reg32|BaseIndex, RegRex, 5, Dw2Inval, Dw2Inval +r14d, Reg32|BaseIndex, RegRex, 6, Dw2Inval, Dw2Inval +r15d, Reg32|BaseIndex, RegRex, 7, Dw2Inval, Dw2Inval +rax, Reg64|BaseIndex|Acc|Qword, 0, 0, Dw2Inval, 0 +rcx, Reg64|BaseIndex, 0, 1, Dw2Inval, 2 +rdx, Reg64|BaseIndex, 0, 2, Dw2Inval, 1 +rbx, Reg64|BaseIndex, 0, 3, Dw2Inval, 3 +rsp, Reg64, 0, 4, Dw2Inval, 7 +rbp, Reg64|BaseIndex, 0, 5, Dw2Inval, 6 +rsi, Reg64|BaseIndex, 0, 6, Dw2Inval, 4 +rdi, Reg64|BaseIndex, 0, 7, Dw2Inval, 5 +r8, Reg64|BaseIndex, RegRex, 0, Dw2Inval, 8 +r9, Reg64|BaseIndex, RegRex, 1, Dw2Inval, 9 +r10, Reg64|BaseIndex, RegRex, 2, Dw2Inval, 10 +r11, Reg64|BaseIndex, RegRex, 3, Dw2Inval, 11 +r12, Reg64|BaseIndex, RegRex, 4, Dw2Inval, 12 +r13, Reg64|BaseIndex, RegRex, 5, Dw2Inval, 13 +r14, Reg64|BaseIndex, RegRex, 6, Dw2Inval, 14 +r15, Reg64|BaseIndex, RegRex, 7, Dw2Inval, 15 // Segment registers. -es, SReg2, 0, 0 -cs, SReg2, 0, 1 -ss, SReg2, 0, 2 -ds, SReg2, 0, 3 -fs, SReg3, 0, 4 -gs, SReg3, 0, 5 +es, SReg2, 0, 0, 40, 50 +cs, SReg2, 0, 1, 41, 51 +ss, SReg2, 0, 2, 42, 52 +ds, SReg2, 0, 3, 43, 53 +fs, SReg3, 0, 4, 44, 54 +gs, SReg3, 0, 5, 45, 55 // Control registers. -cr0, Control, 0, 0 -cr1, Control, 0, 1 -cr2, Control, 0, 2 -cr3, Control, 0, 3 -cr4, Control, 0, 4 -cr5, Control, 0, 5 -cr6, Control, 0, 6 -cr7, Control, 0, 7 -cr8, Control, RegRex, 0 -cr9, Control, RegRex, 1 -cr10, Control, RegRex, 2 -cr11, Control, RegRex, 3 -cr12, Control, RegRex, 4 -cr13, Control, RegRex, 5 -cr14, Control, RegRex, 6 -cr15, Control, RegRex, 7 +cr0, Control, 0, 0, Dw2Inval, Dw2Inval +cr1, Control, 0, 1, Dw2Inval, Dw2Inval +cr2, Control, 0, 2, Dw2Inval, Dw2Inval +cr3, Control, 0, 3, Dw2Inval, Dw2Inval +cr4, Control, 0, 4, Dw2Inval, Dw2Inval +cr5, Control, 0, 5, Dw2Inval, Dw2Inval +cr6, Control, 0, 6, Dw2Inval, Dw2Inval +cr7, Control, 0, 7, Dw2Inval, Dw2Inval +cr8, Control, RegRex, 0, Dw2Inval, Dw2Inval +cr9, Control, RegRex, 1, Dw2Inval, Dw2Inval +cr10, Control, RegRex, 2, Dw2Inval, Dw2Inval +cr11, Control, RegRex, 3, Dw2Inval, Dw2Inval +cr12, Control, RegRex, 4, Dw2Inval, Dw2Inval +cr13, Control, RegRex, 5, Dw2Inval, Dw2Inval +cr14, Control, RegRex, 6, Dw2Inval, Dw2Inval +cr15, Control, RegRex, 7, Dw2Inval, Dw2Inval // Debug registers. -db0, Debug, 0, 0 -db1, Debug, 0, 1 -db2, Debug, 0, 2 -db3, Debug, 0, 3 -db4, Debug, 0, 4 -db5, Debug, 0, 5 -db6, Debug, 0, 6 -db7, Debug, 0, 7 -db8, Debug, RegRex, 0 -db9, Debug, RegRex, 1 -db10, Debug, RegRex, 2 -db11, Debug, RegRex, 3 -db12, Debug, RegRex, 4 -db13, Debug, RegRex, 5 -db14, Debug, RegRex, 6 -db15, Debug, RegRex, 7 -dr0, Debug, 0, 0 -dr1, Debug, 0, 1 -dr2, Debug, 0, 2 -dr3, Debug, 0, 3 -dr4, Debug, 0, 4 -dr5, Debug, 0, 5 -dr6, Debug, 0, 6 -dr7, Debug, 0, 7 -dr8, Debug, RegRex, 0 -dr9, Debug, RegRex, 1 -dr10, Debug, RegRex, 2 -dr11, Debug, RegRex, 3 -dr12, Debug, RegRex, 4 -dr13, Debug, RegRex, 5 -dr14, Debug, RegRex, 6 -dr15, Debug, RegRex, 7 +db0, Debug, 0, 0, Dw2Inval, Dw2Inval +db1, Debug, 0, 1, Dw2Inval, Dw2Inval +db2, Debug, 0, 2, Dw2Inval, Dw2Inval +db3, Debug, 0, 3, Dw2Inval, Dw2Inval +db4, Debug, 0, 4, Dw2Inval, Dw2Inval +db5, Debug, 0, 5, Dw2Inval, Dw2Inval +db6, Debug, 0, 6, Dw2Inval, Dw2Inval +db7, Debug, 0, 7, Dw2Inval, Dw2Inval +db8, Debug, RegRex, 0, Dw2Inval, Dw2Inval +db9, Debug, RegRex, 1, Dw2Inval, Dw2Inval +db10, Debug, RegRex, 2, Dw2Inval, Dw2Inval +db11, Debug, RegRex, 3, Dw2Inval, Dw2Inval +db12, Debug, RegRex, 4, Dw2Inval, Dw2Inval +db13, Debug, RegRex, 5, Dw2Inval, Dw2Inval +db14, Debug, RegRex, 6, Dw2Inval, Dw2Inval +db15, Debug, RegRex, 7, Dw2Inval, Dw2Inval +dr0, Debug, 0, 0, Dw2Inval, Dw2Inval +dr1, Debug, 0, 1, Dw2Inval, Dw2Inval +dr2, Debug, 0, 2, Dw2Inval, Dw2Inval +dr3, Debug, 0, 3, Dw2Inval, Dw2Inval +dr4, Debug, 0, 4, Dw2Inval, Dw2Inval +dr5, Debug, 0, 5, Dw2Inval, Dw2Inval +dr6, Debug, 0, 6, Dw2Inval, Dw2Inval +dr7, Debug, 0, 7, Dw2Inval, Dw2Inval +dr8, Debug, RegRex, 0, Dw2Inval, Dw2Inval +dr9, Debug, RegRex, 1, Dw2Inval, Dw2Inval +dr10, Debug, RegRex, 2, Dw2Inval, Dw2Inval +dr11, Debug, RegRex, 3, Dw2Inval, Dw2Inval +dr12, Debug, RegRex, 4, Dw2Inval, Dw2Inval +dr13, Debug, RegRex, 5, Dw2Inval, Dw2Inval +dr14, Debug, RegRex, 6, Dw2Inval, Dw2Inval +dr15, Debug, RegRex, 7, Dw2Inval, Dw2Inval // Test registers. -tr0, Test, 0, 0 -tr1, Test, 0, 1 -tr2, Test, 0, 2 -tr3, Test, 0, 3 -tr4, Test, 0, 4 -tr5, Test, 0, 5 -tr6, Test, 0, 6 -tr7, Test, 0, 7 +tr0, Test, 0, 0, Dw2Inval, Dw2Inval +tr1, Test, 0, 1, Dw2Inval, Dw2Inval +tr2, Test, 0, 2, Dw2Inval, Dw2Inval +tr3, Test, 0, 3, Dw2Inval, Dw2Inval +tr4, Test, 0, 4, Dw2Inval, Dw2Inval +tr5, Test, 0, 5, Dw2Inval, Dw2Inval +tr6, Test, 0, 6, Dw2Inval, Dw2Inval +tr7, Test, 0, 7, Dw2Inval, Dw2Inval // MMX and simd registers. -mm0, RegMMX, 0, 0 -mm1, RegMMX, 0, 1 -mm2, RegMMX, 0, 2 -mm3, RegMMX, 0, 3 -mm4, RegMMX, 0, 4 -mm5, RegMMX, 0, 5 -mm6, RegMMX, 0, 6 -mm7, RegMMX, 0, 7 -xmm0, RegXMM, 0, 0 -xmm1, RegXMM, 0, 1 -xmm2, RegXMM, 0, 2 -xmm3, RegXMM, 0, 3 -xmm4, RegXMM, 0, 4 -xmm5, RegXMM, 0, 5 -xmm6, RegXMM, 0, 6 -xmm7, RegXMM, 0, 7 -xmm8, RegXMM, RegRex, 0 -xmm9, RegXMM, RegRex, 1 -xmm10, RegXMM, RegRex, 2 -xmm11, RegXMM, RegRex, 3 -xmm12, RegXMM, RegRex, 4 -xmm13, RegXMM, RegRex, 5 -xmm14, RegXMM, RegRex, 6 -xmm15, RegXMM, RegRex, 7 +mm0, RegMMX, 0, 0, 29, 41 +mm1, RegMMX, 0, 1, 30, 42 +mm2, RegMMX, 0, 2, 31, 43 +mm3, RegMMX, 0, 3, 32, 44 +mm4, RegMMX, 0, 4, 33, 45 +mm5, RegMMX, 0, 5, 34, 46 +mm6, RegMMX, 0, 6, 35, 47 +mm7, RegMMX, 0, 7, 36, 48 +xmm0, RegXMM, 0, 0, 21, 17 +xmm1, RegXMM, 0, 1, 22, 18 +xmm2, RegXMM, 0, 2, 23, 19 +xmm3, RegXMM, 0, 3, 24, 20 +xmm4, RegXMM, 0, 4, 25, 21 +xmm5, RegXMM, 0, 5, 26, 22 +xmm6, RegXMM, 0, 6, 27, 23 +xmm7, RegXMM, 0, 7, 28, 24 +xmm8, RegXMM, RegRex, 0, Dw2Inval, 25 +xmm9, RegXMM, RegRex, 1, Dw2Inval, 26 +xmm10, RegXMM, RegRex, 2, Dw2Inval, 27 +xmm11, RegXMM, RegRex, 3, Dw2Inval, 28 +xmm12, RegXMM, RegRex, 4, Dw2Inval, 29 +xmm13, RegXMM, RegRex, 5, Dw2Inval, 30 +xmm14, RegXMM, RegRex, 6, Dw2Inval, 31 +xmm15, RegXMM, RegRex, 7, Dw2Inval, 32 // No type will make these registers rejected for all purposes except // for addressing. This saves creating one extra type for RIP/EIP. -rip, BaseIndex, RegRex64, RegRip -eip, BaseIndex, RegRex64, RegEip +rip, BaseIndex, RegRex64, RegRip, Dw2Inval, 16 +eip, BaseIndex, RegRex64, RegEip, 8, Dw2Inval // No type will make these registers rejected for all purposes except // for addressing. -eiz, BaseIndex, 0, RegEiz -riz, BaseIndex, 0, RegRiz +eiz, BaseIndex, 0, RegEiz, Dw2Inval, Dw2Inval +riz, BaseIndex, 0, RegRiz, Dw2Inval, Dw2Inval // fp regs. -st(0), FloatReg|FloatAcc, 0, 0 -st(1), FloatReg, 0, 1 -st(2), FloatReg, 0, 2 -st(3), FloatReg, 0, 3 -st(4), FloatReg, 0, 4 -st(5), FloatReg, 0, 5 -st(6), FloatReg, 0, 6 -st(7), FloatReg, 0, 7 +st(0), FloatReg|FloatAcc, 0, 0, 11, 33 +st(1), FloatReg, 0, 1, 12, 34 +st(2), FloatReg, 0, 2, 13, 35 +st(3), FloatReg, 0, 3, 14, 36 +st(4), FloatReg, 0, 4, 15, 37 +st(5), FloatReg, 0, 5, 16, 38 +st(6), FloatReg, 0, 6, 17, 39 +st(7), FloatReg, 0, 7, 18, 40 +// Pseudo-register names only used in .cfi_* directives +eflags, 0, 0, 0, 9, 49 +rflags, 0, 0, 0, Dw2Inval, 49 +fs.base, 0, 0, 0, Dw2Inval, 58 +gs.base, 0, 0, 0, Dw2Inval, 59 +tr, 0, 0, 0, 48, 62 +ldtr, 0, 0, 0, 49, 63 +// st0...7 for backward compatibility +st0, 0, 0, 0, 11, 33 +st1, 0, 0, 1, 12, 34 +st2, 0, 0, 2, 13, 35 +st3, 0, 0, 3, 14, 36 +st4, 0, 0, 4, 15, 37 +st5, 0, 0, 5, 16, 38 +st6, 0, 0, 6, 17, 39 +st7, 0, 0, 7, 18, 40 +fcw, 0, 0, 0, 37, 65 +fsw, 0, 0, 0, 38, 66 +mxcsr, 0, 0, 0, 39, 64 diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h index 8c8f715..128502b 100644 --- a/opcodes/i386-tbl.h +++ b/opcodes/i386-tbl.h @@ -16994,857 +16994,942 @@ const reg_entry i386_regtab[] = { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 0 }, + 0, 0, { 11, 33 } }, { "al", { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 0 }, + 0, 0, { Dw2Inval, Dw2Inval } }, { "cl", { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 1 }, + 0, 1, { Dw2Inval, Dw2Inval } }, { "dl", { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 2 }, + 0, 2, { Dw2Inval, Dw2Inval } }, { "bl", { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 3 }, + 0, 3, { Dw2Inval, Dw2Inval } }, { "ah", { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 4 }, + 0, 4, { Dw2Inval, Dw2Inval } }, { "ch", { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 5 }, + 0, 5, { Dw2Inval, Dw2Inval } }, { "dh", { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 6 }, + 0, 6, { Dw2Inval, Dw2Inval } }, { "bh", { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 7 }, + 0, 7, { Dw2Inval, Dw2Inval } }, { "axl", { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex64, 0 }, + RegRex64, 0, { Dw2Inval, Dw2Inval } }, { "cxl", { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex64, 1 }, + RegRex64, 1, { Dw2Inval, Dw2Inval } }, { "dxl", { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex64, 2 }, + RegRex64, 2, { Dw2Inval, Dw2Inval } }, { "bxl", { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex64, 3 }, + RegRex64, 3, { Dw2Inval, Dw2Inval } }, { "spl", { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex64, 4 }, + RegRex64, 4, { Dw2Inval, Dw2Inval } }, { "bpl", { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex64, 5 }, + RegRex64, 5, { Dw2Inval, Dw2Inval } }, { "sil", { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex64, 6 }, + RegRex64, 6, { Dw2Inval, Dw2Inval } }, { "dil", { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex64, 7 }, + RegRex64, 7, { Dw2Inval, Dw2Inval } }, { "r8b", { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex|RegRex64, 0 }, + RegRex|RegRex64, 0, { Dw2Inval, Dw2Inval } }, { "r9b", { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex|RegRex64, 1 }, + RegRex|RegRex64, 1, { Dw2Inval, Dw2Inval } }, { "r10b", { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex|RegRex64, 2 }, + RegRex|RegRex64, 2, { Dw2Inval, Dw2Inval } }, { "r11b", { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex|RegRex64, 3 }, + RegRex|RegRex64, 3, { Dw2Inval, Dw2Inval } }, { "r12b", { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex|RegRex64, 4 }, + RegRex|RegRex64, 4, { Dw2Inval, Dw2Inval } }, { "r13b", { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex|RegRex64, 5 }, + RegRex|RegRex64, 5, { Dw2Inval, Dw2Inval } }, { "r14b", { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex|RegRex64, 6 }, + RegRex|RegRex64, 6, { Dw2Inval, Dw2Inval } }, { "r15b", { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex|RegRex64, 7 }, + RegRex|RegRex64, 7, { Dw2Inval, Dw2Inval } }, { "ax", { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 0 }, + 0, 0, { Dw2Inval, Dw2Inval } }, { "cx", { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 1 }, + 0, 1, { Dw2Inval, Dw2Inval } }, { "dx", { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 2 }, + 0, 2, { Dw2Inval, Dw2Inval } }, { "bx", { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 3 }, + 0, 3, { Dw2Inval, Dw2Inval } }, { "sp", { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 4 }, + 0, 4, { Dw2Inval, Dw2Inval } }, { "bp", { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 5 }, + 0, 5, { Dw2Inval, Dw2Inval } }, { "si", { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 6 }, + 0, 6, { Dw2Inval, Dw2Inval } }, { "di", { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 7 }, + 0, 7, { Dw2Inval, Dw2Inval } }, { "r8w", { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex, 0 }, + RegRex, 0, { Dw2Inval, Dw2Inval } }, { "r9w", { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex, 1 }, + RegRex, 1, { Dw2Inval, Dw2Inval } }, { "r10w", { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex, 2 }, + RegRex, 2, { Dw2Inval, Dw2Inval } }, { "r11w", { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex, 3 }, + RegRex, 3, { Dw2Inval, Dw2Inval } }, { "r12w", { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex, 4 }, + RegRex, 4, { Dw2Inval, Dw2Inval } }, { "r13w", { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex, 5 }, + RegRex, 5, { Dw2Inval, Dw2Inval } }, { "r14w", { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex, 6 }, + RegRex, 6, { Dw2Inval, Dw2Inval } }, { "r15w", { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex, 7 }, + RegRex, 7, { Dw2Inval, Dw2Inval } }, { "eax", { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 0 }, + 0, 0, { 0, Dw2Inval } }, { "ecx", { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 1 }, + 0, 1, { 1, Dw2Inval } }, { "edx", { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 2 }, + 0, 2, { 2, Dw2Inval } }, { "ebx", { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 3 }, + 0, 3, { 3, Dw2Inval } }, { "esp", { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 4 }, + 0, 4, { 4, Dw2Inval } }, { "ebp", { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 5 }, + 0, 5, { 5, Dw2Inval } }, { "esi", { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 6 }, + 0, 6, { 6, Dw2Inval } }, { "edi", { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 7 }, + 0, 7, { 7, Dw2Inval } }, { "r8d", { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex, 0 }, + RegRex, 0, { Dw2Inval, Dw2Inval } }, { "r9d", { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex, 1 }, + RegRex, 1, { Dw2Inval, Dw2Inval } }, { "r10d", { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex, 2 }, + RegRex, 2, { Dw2Inval, Dw2Inval } }, { "r11d", { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex, 3 }, + RegRex, 3, { Dw2Inval, Dw2Inval } }, { "r12d", { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex, 4 }, + RegRex, 4, { Dw2Inval, Dw2Inval } }, { "r13d", { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex, 5 }, + RegRex, 5, { Dw2Inval, Dw2Inval } }, { "r14d", { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 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0, 6 }, + 0, 6, { Dw2Inval, Dw2Inval } }, { "cr7", { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 7 }, + 0, 7, { Dw2Inval, Dw2Inval } }, { "cr8", { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex, 0 }, + RegRex, 0, { Dw2Inval, Dw2Inval } }, { "cr9", { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex, 1 }, + RegRex, 1, { Dw2Inval, Dw2Inval } }, { "cr10", { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex, 2 }, + RegRex, 2, { Dw2Inval, Dw2Inval } }, { "cr11", { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex, 3 }, + RegRex, 3, { Dw2Inval, Dw2Inval } }, { "cr12", { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 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RegRex, 0 }, + RegRex, 0, { Dw2Inval, Dw2Inval } }, { "db9", { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex, 1 }, + RegRex, 1, { Dw2Inval, Dw2Inval } }, { "db10", { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex, 2 }, + RegRex, 2, { Dw2Inval, Dw2Inval } }, { "db11", { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex, 3 }, + RegRex, 3, { Dw2Inval, Dw2Inval } }, { "db12", { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex, 4 }, + RegRex, 4, { Dw2Inval, Dw2Inval } }, { "db13", { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex, 5 }, + RegRex, 5, { Dw2Inval, Dw2Inval } }, { "db14", { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex, 6 }, + RegRex, 6, { Dw2Inval, Dw2Inval } }, { "db15", { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex, 7 }, + RegRex, 7, { Dw2Inval, Dw2Inval } }, { "dr0", { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 0 }, + 0, 0, { Dw2Inval, Dw2Inval } }, { "dr1", { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 1 }, + 0, 1, { Dw2Inval, Dw2Inval } }, { "dr2", { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 2 }, + 0, 2, { Dw2Inval, Dw2Inval } }, { "dr3", { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 3 }, + 0, 3, { Dw2Inval, Dw2Inval } }, { "dr4", { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 4 }, + 0, 4, { Dw2Inval, Dw2Inval } }, { "dr5", { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 5 }, + 0, 5, { Dw2Inval, Dw2Inval } }, { "dr6", { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 6 }, + 0, 6, { Dw2Inval, Dw2Inval } }, { "dr7", { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 7 }, + 0, 7, { Dw2Inval, Dw2Inval } }, { "dr8", { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex, 0 }, + RegRex, 0, { Dw2Inval, Dw2Inval } }, { "dr9", { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex, 1 }, + RegRex, 1, { Dw2Inval, Dw2Inval } }, { "dr10", { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex, 2 }, + RegRex, 2, { Dw2Inval, Dw2Inval } }, { "dr11", { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex, 3 }, + RegRex, 3, { Dw2Inval, Dw2Inval } }, { "dr12", { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex, 4 }, + RegRex, 4, { Dw2Inval, Dw2Inval } }, { "dr13", { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex, 5 }, + RegRex, 5, { Dw2Inval, Dw2Inval } }, { "dr14", { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex, 6 }, + RegRex, 6, { Dw2Inval, Dw2Inval } }, { "dr15", { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex, 7 }, + RegRex, 7, { Dw2Inval, Dw2Inval } }, { "tr0", { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 0 }, + 0, 0, { Dw2Inval, Dw2Inval } }, { "tr1", { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 1 }, + 0, 1, { Dw2Inval, Dw2Inval } }, { "tr2", { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 2 }, + 0, 2, { Dw2Inval, Dw2Inval } }, { "tr3", { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 3 }, + 0, 3, { Dw2Inval, Dw2Inval } }, { "tr4", { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 4 }, + 0, 4, { Dw2Inval, Dw2Inval } }, { "tr5", { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 5 }, + 0, 5, { Dw2Inval, Dw2Inval } }, { "tr6", { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 6 }, + 0, 6, { Dw2Inval, Dw2Inval } }, { "tr7", { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 7 }, + 0, 7, { Dw2Inval, Dw2Inval } }, { "mm0", { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 0 }, + 0, 0, { 29, 41 } }, { "mm1", { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 1 }, + 0, 1, { 30, 42 } }, { "mm2", { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 2 }, + 0, 2, { 31, 43 } }, { "mm3", { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 3 }, + 0, 3, { 32, 44 } }, { "mm4", { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 4 }, + 0, 4, { 33, 45 } }, { "mm5", { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 5 }, + 0, 5, { 34, 46 } }, { "mm6", { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 6 }, + 0, 6, { 35, 47 } }, { "mm7", { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 7 }, + 0, 7, { 36, 48 } }, { "xmm0", { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 0 }, + 0, 0, { 21, 17 } }, { "xmm1", { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 1 }, + 0, 1, { 22, 18 } }, { "xmm2", { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 2 }, + 0, 2, { 23, 19 } }, { "xmm3", { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 3 }, + 0, 3, { 24, 20 } }, { "xmm4", { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 4 }, + 0, 4, { 25, 21 } }, { "xmm5", { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 5 }, + 0, 5, { 26, 22 } }, { "xmm6", { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 6 }, + 0, 6, { 27, 23 } }, { "xmm7", { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 7 }, + 0, 7, { 28, 24 } }, { "xmm8", { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex, 0 }, + RegRex, 0, { Dw2Inval, 25 } }, { "xmm9", { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex, 1 }, + RegRex, 1, { Dw2Inval, 26 } }, { "xmm10", { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex, 2 }, + RegRex, 2, { Dw2Inval, 27 } }, { "xmm11", { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex, 3 }, + RegRex, 3, { Dw2Inval, 28 } }, { "xmm12", { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex, 4 }, + RegRex, 4, { Dw2Inval, 29 } }, { "xmm13", { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex, 5 }, + RegRex, 5, { Dw2Inval, 30 } }, { "xmm14", { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex, 6 }, + RegRex, 6, { Dw2Inval, 31 } }, { "xmm15", { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex, 7 }, + RegRex, 7, { Dw2Inval, 32 } }, { "rip", { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex64, RegRip }, + RegRex64, RegRip, { Dw2Inval, 16 } }, { "eip", { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - RegRex64, RegEip }, + RegRex64, RegEip, { 8, Dw2Inval } }, { "eiz", { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, RegEiz }, + 0, RegEiz, { Dw2Inval, Dw2Inval } }, { "riz", { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, RegRiz }, + 0, RegRiz, { Dw2Inval, Dw2Inval } }, { "st(0)", { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 0 }, + 0, 0, { 11, 33 } }, { "st(1)", { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 1 }, + 0, 1, { 12, 34 } }, { "st(2)", { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 2 }, + 0, 2, { 13, 35 } }, { "st(3)", { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 3 }, + 0, 3, { 14, 36 } }, { "st(4)", { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 4 }, + 0, 4, { 15, 37 } }, { "st(5)", { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 5 }, + 0, 5, { 16, 38 } }, { "st(6)", { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 6 }, + 0, 6, { 17, 39 } }, { "st(7)", { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 7 }, + 0, 7, { 18, 40 } }, + { "eflags", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0 } }, + 0, 0, { 9, 49 } }, + { "rflags", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0 } }, + 0, 0, { Dw2Inval, 49 } }, + { "fs.base", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0 } }, + 0, 0, { Dw2Inval, 58 } }, + { "gs.base", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0 } }, + 0, 0, { Dw2Inval, 59 } }, + { "tr", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0 } }, + 0, 0, { 48, 62 } }, + { "ldtr", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0 } }, + 0, 0, { 49, 63 } }, + { "st0", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0 } }, + 0, 0, { 11, 33 } }, + { "st1", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0 } }, + 0, 1, { 12, 34 } }, + { "st2", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0 } }, + 0, 2, { 13, 35 } }, + { "st3", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0 } }, + 0, 3, { 14, 36 } }, + { "st4", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0 } }, + 0, 4, { 15, 37 } }, + { "st5", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0 } }, + 0, 5, { 16, 38 } }, + { "st6", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0 } }, + 0, 6, { 17, 39 } }, + { "st7", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0 } }, + 0, 7, { 18, 40 } }, + { "fcw", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0 } }, + 0, 0, { 37, 65 } }, + { "fsw", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0 } }, + 0, 0, { 38, 66 } }, + { "mxcsr", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0 } }, + 0, 0, { 39, 64 } }, }; const unsigned int i386_regtab_size = ARRAY_SIZE (i386_regtab); |