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authorNick Clifton <nickc@redhat.com>2007-11-07 14:40:40 +0000
committerNick Clifton <nickc@redhat.com>2007-11-07 14:40:40 +0000
commit92c8bd791d129c01e425e0c7b711193517cf7a41 (patch)
tree9682a2b4d50460a27b5394bd0458366368b210e4 /opcodes
parenta25795624bbda603d486ae8cd2f04c92cc5150b4 (diff)
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* arm-dis.c (arm_opcodes): Remove superflous escapes of percent operators.
Diffstat (limited to 'opcodes')
-rw-r--r--opcodes/ChangeLog5
-rw-r--r--opcodes/arm-dis.c8
2 files changed, 9 insertions, 4 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index e9452c8..e881a8a 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2007-11-07 David O'Brien <obrien@FreeBSD.org>
+
+ * arm-dis.c (arm_opcodes): Remove superflous escapes of percent
+ operators.
+
2007-11-06 Peter Bergner <bergner@vnet.ibm.com>
* ppc-opc.c (powerpc_opcodes): Remove the dcffix and dcffix. opcodes
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 18aad64..e9a48e5 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -866,10 +866,10 @@ static const struct opcode32 arm_opcodes[] =
{ARM_EXT_V6, 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15r, %16-19r, %0-3r"},
{ARM_EXT_V6, 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15r, %16-19r, %0-3r"},
{ARM_EXT_V6, 0x06500f50, 0x0ff00ff0, "usubaddx%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06bf0f30, 0x0fff0ff0, "rev%c\t\%12-15r, %0-3r"},
- {ARM_EXT_V6, 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t\%12-15r, %0-3r"},
- {ARM_EXT_V6, 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t\%12-15r, %0-3r"},
- {ARM_EXT_V6, 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t\%16-19r%21'!"},
+ {ARM_EXT_V6, 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15r, %0-3r"},
+ {ARM_EXT_V6, 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15r, %0-3r"},
+ {ARM_EXT_V6, 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15r, %0-3r"},
+ {ARM_EXT_V6, 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
{ARM_EXT_V6, 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15r, %0-3r"},
{ARM_EXT_V6, 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15r, %0-3r, ror #8"},
{ARM_EXT_V6, 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15r, %0-3r, ror #16"},