diff options
| author | Jeff Law <law@redhat.com> | 1997-03-06 23:52:48 +0000 |
|---|---|---|
| committer | Jeff Law <law@redhat.com> | 1997-03-06 23:52:48 +0000 |
| commit | c654d69e0396165099cbcd6edfd893b4262481fb (patch) | |
| tree | 8eff8f6f8e94cba44f7aaf4a6e2cbea6b320d846 /opcodes | |
| parent | 39c65f8d83cc778e344a2a524bdaa3aa79e5821f (diff) | |
| download | gdb-c654d69e0396165099cbcd6edfd893b4262481fb.zip gdb-c654d69e0396165099cbcd6edfd893b4262481fb.tar.gz gdb-c654d69e0396165099cbcd6edfd893b4262481fb.tar.bz2 | |
* mn10300-opc.c (IMM16_PCREL, SD8N_PCREL, D16_SHIFT): Mark these
as relaxable.
For the relaxing assembler.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 11 | ||||
| -rw-r--r-- | opcodes/mn10300-opc.c | 6 |
2 files changed, 13 insertions, 4 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 90134c8..32bb4e8 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,12 @@ +Thu Mar 6 16:51:11 1997 Jeffrey A Law (law@cygnus.com) + + * mn10300-opc.c (IMM16_PCREL, SD8N_PCREL, D16_SHIFT): Mark these + as relaxable. + +Tue Mar 4 06:10:36 1997 J.T. Conklin <jtc@cygnus.com> + + * m68k-opc.c (m68k_opcodes): Fix last change for the mc68010. + Mon Mar 3 07:45:20 1997 J.T. Conklin <jtc@cygnus.com> * m68k-opc.c (m68k_opcodes): Added entries for the tst insns on @@ -202,7 +211,7 @@ Thu Jan 30 11:30:45 1997 Martin M. Hunt <hunt@pizza.cygnus.com> Wed Jan 29 09:39:17 1997 Jeffrey A Law (law@cygnus.com) * mn10200-opc.c (mn10200_operands): Make 8 and 16 bit pc-relative - branchs relaxable. + branches relaxable. Tue Jan 28 15:57:34 1997 Ian Lance Taylor <ian@cygnus.com> diff --git a/opcodes/mn10300-opc.c b/opcodes/mn10300-opc.c index 906f8a4..eae6eb8 100644 --- a/opcodes/mn10300-opc.c +++ b/opcodes/mn10300-opc.c @@ -84,7 +84,7 @@ const struct mn10300_operand mn10300_operands[] = { /* 16 bit pc-relative immediate which may promote to a 16bit pc-relative immediate. */ #define IMM16_PCREL (IMM16+1) - {16, 0, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_PCREL}, + {16, 0, MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX | MN10300_OPERAND_SIGNED}, /* 16bit unsigned dispacement in a memory operation which may promote to a 32bit displacement. */ @@ -163,7 +163,7 @@ const struct mn10300_operand mn10300_operands[] = { /* 8 bit pc-relative displacement. */ #define SD8N_PCREL (SD8N+1) - {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PCREL}, + {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX}, /* 8 bit signed displacement shifted left 8 bits in the instruction. */ #define SD8N_SHIFT8 (SD8N_PCREL+1) @@ -192,7 +192,7 @@ const struct mn10300_operand mn10300_operands[] = { /* 16bit pc-relative displacement which may promote to 32bit pc-relative displacement. */ #define D16_SHIFT (AN01+1) - {16, 8, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_PCREL}, + {16, 8, MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX | MN10300_OPERAND_SIGNED}, /* 8 bit immediate found in the extension word. */ #define IMM8E (D16_SHIFT+1) |