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authorTomer Levi <Tomer.Levi@nsc.com>2004-10-28 10:29:56 +0000
committerTomer Levi <Tomer.Levi@nsc.com>2004-10-28 10:29:56 +0000
commit343cbeea1ea0e4f964a130f02ced0b467ff839e3 (patch)
tree8adadfa573c00bf6b416c70ae491c51e95e61721 /opcodes
parent49c4a1800a5e50d7fdf09c41806b30fea9b002dc (diff)
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2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
* crx-opc.c (REV_COP_INST): New macro, reverse operand order of COP_INST macro.
Diffstat (limited to 'opcodes')
-rw-r--r--opcodes/crx-opc.c22
1 files changed, 13 insertions, 9 deletions
diff --git a/opcodes/crx-opc.c b/opcodes/crx-opc.c
index 34a21bf..c409316 100644
--- a/opcodes/crx-opc.c
+++ b/opcodes/crx-opc.c
@@ -513,15 +513,19 @@ const inst crx_instruction[] =
#define COP_INST(NAME, OPC, TYPE, REG1, REG2) \
/* opc12 c4 opc8 REG1 REG2 */ \
{NAME, 2, 0x301030+OPC, 8, TYPE | FMT_2, {{ui4,16}, {REG1,4}, {REG2,0}}}
-
- COP_INST ("mtcr", 0, COP_REG_INS, regr, copregr),
- COP_INST ("mfcr", 1, COP_REG_INS, copregr, regr),
- COP_INST ("mtcsr", 2, COPS_REG_INS, regr, copsregr),
- COP_INST ("mfcsr", 3, COPS_REG_INS, copsregr, regr),
- COP_INST ("ldcr", 4, COP_REG_INS, regr, copregr),
- COP_INST ("stcr", 5, COP_REG_INS, copregr, regr),
- COP_INST ("ldcsr", 6, COPS_REG_INS, regr, copsregr),
- COP_INST ("stcsr", 7, COPS_REG_INS, copsregr, regr),
+/* A reverse form of the above macro. */
+#define REV_COP_INST(NAME, OPC, TYPE, REG1, REG2) \
+ /* opc12 c4 opc8 REG2 REG1 */ \
+ {NAME, 2, 0x301030+OPC, 8, TYPE | FMT_2, {{ui4,16}, {REG1,0}, {REG2,4}}}
+
+ COP_INST ("mtcr", 0, COP_REG_INS, regr, copregr),
+ COP_INST ("mfcr", 1, COP_REG_INS, copregr, regr),
+ COP_INST ("mtcsr", 2, COPS_REG_INS, regr, copsregr),
+ COP_INST ("mfcsr", 3, COPS_REG_INS, copsregr, regr),
+ COP_INST ("ldcr", 4, COP_REG_INS, regr, copregr),
+ REV_COP_INST ("stcr", 5, COP_REG_INS, copregr, regr),
+ COP_INST ("ldcsr", 6, COPS_REG_INS, regr, copsregr),
+ REV_COP_INST ("stcsr", 7, COPS_REG_INS, copsregr, regr),
/* Create a memory-related CO-processor instruction. */
#define COPMEM_INST(NAME, OPC, TYPE) \